Having Transistor Structure Patents (Class 257/187)
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Patent number: 6348704Abstract: Each layer of a three-layer structure composed of semiconductor (collector layer 13)/metal (base layer 14)/semiconductor (emitter layer 15) is formed from a nitride. By so doing, one identical constituent element (N) is contained in both semiconductor layers and the metal layer. Because Nb of the NbN base layer 14 combines with N to form a nitride at a stoichiometric ratio of 1:1, the resulting metal nitride and nitride semiconductor exhibit the same stoichiometric ratio. Therefore, it becomes possible to form the base layer 14 and the emitter layer 15 spatially continuously (interface bonding of 1:1), so that a successful Schottky junction can be obtained. As a result, an MBT superior in electrical characteristics can be obtained. Thus, the semiconductor device has successful Schottky characteristics so that superior characteristics can be obtained.Type: GrantFiled: August 18, 2000Date of Patent: February 19, 2002Assignee: Sharp Kabushiki KaishaInventor: Nobuaki Teraguchi
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Patent number: 6337508Abstract: A transistor having an electron quantum-wave interference layer with plural periods of a pair of a first layer W and a second layer B in a p-layer of a pn junction structure. The second layer B has wider band gap than the first layer W. Each thicknesses of the first layer W and the second layer B is determined by multiplying by an odd number one fourth of quantum-wave wavelength of carriers in each of the first layer W and the second layer B, the carriers existing around the lowest energy level of the second layer B. The quantum-wave interference layer functions as an electron reflecting layer, and enables to lower a dynamic resistance of the transistor notably. An amplification factor of a bipolar transistor of an npn junction structure, having the electron reflecting layer is improved compared with a transistor without an electrode reflecting layer. Similarly, a transistor having a hole reflecting layer, which has a larger amplification factor, can be obtained.Type: GrantFiled: October 22, 1999Date of Patent: January 8, 2002Assignee: Canare Electric Co., Ltd.Inventor: Hiroyuki Kano
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Patent number: 6300166Abstract: A method for packaging a BGA and the structure of the BGA for using the method are disclosed. The structure of the substrate of the BGA includes multiple pairs of aligned slots (11, 12) defined along the X-axis thereof, and a passage (13) corresponding to and perpendicular to one pair of aligned slots (11, 12). While using the method to package the substrate, one side of the substrate will be entirely covered by a first protective layer to protect the chips and the other side of the substrate will form multiple lines of a second protective layers to protect the bonding wires.Type: GrantFiled: August 30, 1999Date of Patent: October 9, 2001Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Su Tao, Yu-Ching Tsai, Meng-Hui Lin, Chin-Ming Chung
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Patent number: 6184100Abstract: In a light receiving element and a semiconductor device manufacturing method, the low density PN junction is formed by constructing the internal composition of the photodiode with N+ type diffusion layer, N− type epitaxial layer, P− type epitaxial layer, P+ type deposit layer, and P type Si from the light receiving surface, the vacant layer to be occurred when the photodiode is reverse biased will be widened and the light receiving sensitivity and the frequency characteristic will be improved. Furthermore, since the separation of bipolar elements will be conducted by P− epitaxial layer, the efficiency in density control at the time of P− type epitaxial growth can be improved.Type: GrantFiled: June 13, 1997Date of Patent: February 6, 2001Assignee: Sony CorporationInventor: Chihiro Arai
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Patent number: 6137123Abstract: A GaN/AlGaN heterojunction bipolar phototransistor having AlGaN contact, i-GaN absorbing, p-GaN base and n-GaN emitter layers formed, in that order, on a UV transparent substrate. The phototransistor has a gain greater than 10.sup.5. From 360 nm to 400 nm, eight orders of magnitude drop in responsivity was achieved. The phototransistor features a rapid electrical quenching of persistent photoconductivity, and exhibits high dark impedance and no DC drift. By changing the frequency of the quenching cycles, the detection speed of the phototransistor can be adjusted to accommodate specific applications. These results represent an internal gain UV detector with significantly improved performance over GaN based photo conductors.Type: GrantFiled: August 17, 1999Date of Patent: October 24, 2000Assignee: Honeywell International Inc.Inventors: Wei Yang, Thomas E. Nohava, Scott A. McPherson, Robert C. Torreano, Holly A. Marsh, Subash Krishnankutty
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Patent number: 6100547Abstract: A first electrode layer composed of Pt is formed on an operating layer, and a second electrode layer composed of a material which is different from Pt is formed on the operating layer so as to cover the first electrode layer. A buried electrode layer composed of Pt is formed in the operating layer under the first electrode layer. The first electrode layer, the second electrode layer and the buried electrode layer constitute a gate electrode.Type: GrantFiled: July 10, 1998Date of Patent: August 8, 2000Assignee: Sanyo Electric Co., Ltd.Inventor: Shigeharu Matsushita
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Patent number: 6078070Abstract: A composite-layer semiconductor device includes a gate above a host substrate, an n++ contact layer above the gate, and source and drain ohmic contacts applied to the n++ contact layer. The source and drain ohmic contacts define a central gate location which is recessed through the n++ contact layer toward the gate. The source and drain ohmic contacts create a barrier to chemical etching so that a current path below the central gate location can be incrementally recessed in repeated steps to precisely tailor the operating mode of the device for depletion or enhancement applications. The composite-layer semiconductor device is fabricated by depositing a gate on an n++ contact layer above a semi-insulating substrate. The semi-insulating substrate and gate are flipped onto an epoxy layer on the host substrate so that the gate is secured to the epoxy layer and the semi-insulating substrate presents an exposed backside. A portion of the exposed backside is removed.Type: GrantFiled: January 7, 1998Date of Patent: June 20, 2000Assignee: W. L. Gore & Associates, Inc.Inventor: Gerald D. Robinson
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Patent number: 6049118Abstract: A circuit built-in light-receiving element includes a buried diffusion layer of the second conductivity type, a buried diffusion layer of the first conductivity type, an epitaxial layer of the second conductivity type, a diffusion layer of the first conductivity type, and a signal processing circuit element. The buried diffusion layer of the second conductivity type is formed in a first region on a substrate of the first conductivity type. The buried diffusion layer of the first conductivity type is selectively formed in the buried diffusion layer of the second conductivity type. The epitaxial layer of the second conductivity type is formed on the buried diffusion layer of the first conductivity type. The buried diffusion layer of the first conductivity type and the epitaxial layer of the second conductivity type constitute a light-receiving element.Type: GrantFiled: July 17, 1997Date of Patent: April 11, 2000Assignee: NEC CorporationInventor: Hiroki Nagano
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Patent number: 6037242Abstract: A method of preparing an AlInAs/GaAs hetero-structure includes forming an Al.sub.1-x In.sub.x As (0<x<1) buffer layer in an amorphous state on a GaAs substrate, annealing the amorphous buffer layer to crystallize the buffer layer into a single crystal buffer layer, and forming a single crystal Al.sub.1-x' In.sub.x' As (0<x'<1) active layer on the single crystal buffer layer.Type: GrantFiled: July 15, 1997Date of Patent: March 14, 2000Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Norio Hayafuji, Yoshitsugu Yamamoto
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Patent number: 6002142Abstract: Novel semiconductor devices are monolithically defined with p-type and/or n-type wide bandgap material formed by impurity induced layer disordering of selected regions of multiple semiconductor layers. The devices are beneficially fabricated by simultaneously forming the n-type and/or p-type layer disordered regions with sufficiently abrupt transitions from disordered to ordered material. The novel devices include laterally and vertically oriented P-i-N or N-i-P photodetectors integrated with laterally oriented P-N-P or N-P-N bipolar transistors, respectively, an N-P-N or P-N-P bipolar transistor monolithically integrated with an edge emitting semiconductor laser, and laterally and vertically oriented P-i-N or N-i-P photodetectors integrated with the monolithically integrated bipolar transistor and edge emitting semiconductor laser.Type: GrantFiled: September 30, 1996Date of Patent: December 14, 1999Assignee: Xerox CorporationInventor: Thomas L. Paoli
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Patent number: 5998817Abstract: A multicell transistor for use in a circuit has an input ground plane for an input waveguide and an output ground plane for an output waveguide. The multicell transistor includes a gate electrode coupled to the input waveguide, a drain electrode coupled to the output waveguide, and a source electrode coupled to the input ground plane. An output ground strap spaced from the drain electrode couples the output ground plane to the source electrode. A pair of transmission lines are orthogonally connected to and extend from the gate electrode to form a pair of inductors for matching the impedances of the gate electrode and the input waveguide.Type: GrantFiled: November 3, 1997Date of Patent: December 7, 1999Assignee: Raytheon CompanyInventors: Cheng P. Wen, Peter Chu, Michael R. Cole, Wah S. Wong, Robert F. Wang, Liping D. Hou
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Patent number: 5990490Abstract: An optical-electronic integrated circuit combining photo detection with an integrated circuit is provided where a light signal input thereto can be directly translated into an electronic signal. The electronic signal can be received and processed by the same integrated circuit. For this optical-electronic integrated circuit, the photo detection circuit is made by a metal-semiconductor-metal process. A current is generated when the photo detection circuit is impinged by photons.Type: GrantFiled: June 29, 1998Date of Patent: November 23, 1999Assignee: Miracle Technology Co., Ltd.Inventor: Wen-Chin Tsay
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Patent number: 5889313Abstract: A radiation-damage resistant radiation detector is formed on a substrate formed of a material doped with a first conductivity type dopant. The detector includes at least one first electrode formed of first conductivity type dopant, and at least one second electrode that is spaced-apart from the first electrode and formed of a second conductivity type dopant. Each first and second electrode penetrates into the substrate from a substrate surface, and one or more electrodes may penetrate entirely through the substrate, that is traversing from one surface to the other surface. Particulate and/or electromagnetic radiation penetrating at least a surface of the substrate releases electrons and holes in substrate regions. Because the electrodes may be formed entirely through the substrate thickness, the released charges will be a relatively small distance from at least a portion of such an electrode, e.g., a distance less than the substrate thickness.Type: GrantFiled: February 7, 1997Date of Patent: March 30, 1999Assignee: University of HawaiiInventor: Sherwood Parker
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Patent number: 5889296Abstract: A photodetection device includes a collector layer, a collector electrode connected electrically to the collector layer, a base layer free from a junction region for contacting with an electrode, an emitter layer including at least two, mutually separated emitter regions; and at least two emitter electrodes provided respectively on the emitter regions, wherein the base layer is exposed optically to an external optical radiation.Type: GrantFiled: May 30, 1997Date of Patent: March 30, 1999Assignee: Fujitsu LimitedInventors: Kenichi Imamura, Naoki Yokoyama
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Patent number: 5889288Abstract: A semiconductor quantum dot device using a semiconductor quantum dot comprises a semiconductor quantum dot formed on a semiconductor wafer, a field effect transistor formed on said semiconductor wafer and comprising a gate electrode formed in a vicinity of said semiconductor quantum dot, and a coupling means to couple said gate electrode and said semiconductor quantum dot capacitively.Type: GrantFiled: July 22, 1996Date of Patent: March 30, 1999Assignee: Fujitsu LimitedInventor: Toshiro Futatsugi
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Patent number: 5831295Abstract: A semiconductor device including a plurality of layers of material defining a diffusion barrier. A defect generator positioned on the plurality of layers in overlying relationship to the diffusion barrier so as to produce a collection of defects at the diffusion barrier that operates as a current restriction. In a typical example, an ohmic contact is positioned around the mesa of a ridge VCSEL, which ohmic contact generates defects that accumulate at a hetero-interface near the active area and confine the current flow to a lasing volume of the VCSEL.Type: GrantFiled: December 1, 1995Date of Patent: November 3, 1998Assignee: Motorola, Inc.Inventors: Jenn-Hwa Huang, Saied N. Tehrani
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Patent number: 5770872Abstract: In a light receiving element and a semiconductor device manufacturing method, the low density PN junction is formed by constructing the internal composition of the photodiode with N.sup.+ type diffusion layer, N.sup.- type epitaxial layer, P.sup.- type epitaxial layer, P.sup.+ type deposit layer, and P type Si from the light receiving surface, the vacant layer to be occurred when the photodiode is reverse biased will be widened and the light receiving sensitivity and the frequency characteristic will be improved. Furthermore, since the separation of bipolar elements will be conducted by P.sup.- epitaxial layer, the efficiency in density control at the time of P.sup.- type epitaxial growth can be improved.Type: GrantFiled: December 5, 1996Date of Patent: June 23, 1998Inventor: Chihiro Arai
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Patent number: 5767560Abstract: A photoelectric conversion device including: a photoelectric conversion portion having a light absorbing layer disposed between charge injection inhibition layers and having a predetermined forbidden band width Eg.sub.1, and a carrier multiplication portion including a single or a plurality of inclined band gap layers, the inclined band gap layer including a minimum forbidden band width Eg.sub.2 and a maximum forbidden band width Eg.sub.3 which are disposed to be in contact with each other to form a hetero junction and having, at the two ends thereof, forbidden band widths Eg.sub.4 which holds a relationship Eg.sub.2 <Eg.sub.4 <Eg.sub.3 in such a manner that the forbidden band width is continuously changed from the two forbidden band widths Eg.sub.2 and Eg.sub.3 to the forbidden band width Eg.sub.4, and the energy step in a conductive band of the hetero junction portion is larger than the energy step in a valence electron band, wherein at least the minimum forbidden band width Eg.sub.Type: GrantFiled: November 30, 1994Date of Patent: June 16, 1998Assignee: Canon Kabushiki KaishaInventor: Ihachiro Gofuku
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Patent number: 5739557Abstract: A heterostructure field effect transistor and method including at least one passivation layer (20) and at least one etch stop layer (22). Enhancement, depletion and combined devices with both enhancement mode and depletion mode devices are possible with minor process variations. Refractory gate (40) and non-gold refractory ohmic contact (52) metallization combined with other features allows non-liftoff metal patterning.Type: GrantFiled: February 6, 1995Date of Patent: April 14, 1998Assignee: Motorola, Inc.Inventors: Vernon Patrick O'Neil, II, Jonathan K. Abrokwah, Majid M. Hashemi, Jenn-Hwa Huang, Vijay K. Nair, Farideh Nikpourian, Saied Nikoo Tehrani
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Patent number: 5710439Abstract: In an optoelectronic integrated device having an optical element section in the wavelength region of 1.33 to 1.55 .mu.m and an electronic element section such as an HEMT integrated in a monolithic form on a GaAs substrate, the optical element section includes light receiving elements or light emitting elements, and an optical absorption layer of the light receiving element or a semiconductor layer forming an active layer of the light emitting element is formed of GaAsN-series compound semiconductor which is lattice-matching with the GaAs substrate, particularly, one of GaAsN, InGaAsN, InGaAsPN, GaAlAsN, InGalAsN, AlGaAsPN and InGaAlAsPN.Type: GrantFiled: December 23, 1996Date of Patent: January 20, 1998Assignee: The Furukawa Electric Co., Ltd.Inventor: Michio Ohkubo
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Patent number: 5684308Abstract: A digital photoreceiver is formed monolithically on an InP semiconductor substrate and comprises a p-i-n photodetector formed from a plurality of InP/InGaAs layers deposited by an epitaxial growth process and an adjacent heterojunction bipolar transistor (HBT) amplifier formed from the same InP/InGaAs layers. The photoreceiver amplifier operates in a large-signal mode to convert a detected photocurrent signal into an amplified output capable of directly driving integrated circuits such as CMOS. In combination with an optical transmitter, the photoreceiver may be used to establish a short-range channel of digital optical communications between integrated circuits with applications to multi-chip modules (MCMs). The photoreceiver may also be used with fiber optic coupling for establishing longer-range digital communications (i.e. optical interconnects) between distributed computers or the like.Type: GrantFiled: February 15, 1996Date of Patent: November 4, 1997Assignee: Sandia CorporationInventors: Michael L. Lovejoy, Benny H. Rose, David C. Craft, Paul M. Enquist, David B. Slater, Jr.
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Patent number: 5677552Abstract: The invention provides an optical functioning device which emits and receives light, and a driver circuit for controlling the device with light. In the device, elements, in which semiconductor multilayer-film reflecting mirrors are provided at both the upper and lower ends of a pnpn structure of semiconductors and which have light-emitting and light-receiving functions to act as optical resonators, are integrated two-dimensionally each with electrodes which are provided for the and the transistors act as phototransistors into which light is introduced.Type: GrantFiled: February 26, 1993Date of Patent: October 14, 1997Assignee: NEC CorporationInventor: Ichiro Ogura
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Patent number: 5677551Abstract: A photodetection device includes a collector layer, a collector electrode connected electrically to the collector layer, a base layer free from a junction region for contacting with an electrode, an emitter layer including at least two, mutually separated emitter regions; and at least two emitter electrodes provided respectively on the emitter regions, wherein the base layer is exposed optically to an external optical radiation.Type: GrantFiled: August 17, 1995Date of Patent: October 14, 1997Assignee: Fujitsu LimitedInventors: Kenichi Imamura, Naoki Yokoyama
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Patent number: 5610409Abstract: An optical FET includes one or more light-responsive diodes stacked on the gate. Each diode includes a planar (horizontal) junction. The number of diodes is chosen to achieve a desired gate to source potential difference. An electrical connection connects the diode(s) to the source of the FET.Type: GrantFiled: May 6, 1996Date of Patent: March 11, 1997Assignee: International Business Machines CorporationInventors: James M. Leas, Jack A. Mandelman
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Patent number: 5608255Abstract: A photo FET device having a large area backside optical energy reception surface is disclosed. The photo FET device is fabricated in the source gate and drain upward configuration using a lattice determining surrogate substrate and a mesa-forming deep etch processing sequence and then inverted onto a new permanent substrate member and the surrogate substrate member removed in order to expose the active area backside optical energy reception surface. Fabrication of the device from two possible indium-inclusive semiconductor materials and a particular gate metal alloy is also disclosed.Type: GrantFiled: May 17, 1995Date of Patent: March 4, 1997Assignee: The United States of America as represented by the Secretary of the Air ForceInventors: Eric A. Martin, Kenneth Vaccaro, William Waters, Joseph P. Lorenzo, Stephen Spaziani
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Patent number: 5598014Abstract: A photoconductor has an active layer of gallium nitride having approximately 10.sup.15 to 5.times.10.sup.15 net donor sites per cubic centimeter and is sensitive to UV radiation. This photoconductor has at least one of a sheet resistance in the approximate range of 10.sup.4 to 5.times.10.sup.6 ohms/unit area and a relatively low level of photoluminescence in the range from about 430-450 nm when excited with light of energy higher than the bandgap energy of 3.4 eV. These criteria tend to define similar semiconductor materials which can form the active layer of an ultraviolet (UV) photodetector having the improved characteristics of a relatively low dark resistance, high sensitivity over at least a range of UV radiation intensity, and decreasing gain with increasing UV radiation.Type: GrantFiled: February 28, 1995Date of Patent: January 28, 1997Assignee: Honeywell Inc.Inventors: Barbara G. Barany, Scott T. Reimer, Robert P. Ulmer, J. David Zook
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Patent number: 5565690Abstract: A method for doping a strained heterojunction semiconductor device includes heating a substrate (16) having a strained mono-crystalline semiconductor region (22) to a temperature above room temperature. While the substrate (16) is heated, dopants are ion implanted into the strained mono-crystalline semiconductor region (22) to minimize implant related damage. Thereafter the substrate (16) is heated under non-steady state conditions for a time sufficient to activate the implanted dopant and anneal implant related damage while minimizing relaxation of the strained heterojunction.Type: GrantFiled: February 2, 1995Date of Patent: October 15, 1996Assignee: Motorola, Inc.Inventors: N. David Theodore, Donald Y. C. Lie, T. C. Smith, John W. Steele
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Patent number: 5557120Abstract: A full wafer to full wafer integrated circuit apparatus wherein substrate removal and replacement on one wafer has been used to enable an accurate alignment of this wafer with features of a receiving wafer during a see through alignment step. The invention is disclosed in terms of a wafer of photo field effect transistors being combined with a wafer of circuit devices that attend the photo feed effect transistor devices. Use of the invention with the different material combination option desired for a photodetector device and its attending circuitry is also disclosed. Advantages over the more conventional chip by chip combination of wafer devices are also disclosed.Type: GrantFiled: May 17, 1995Date of Patent: September 17, 1996Assignee: The United States of America as represented by the Secretary of the Air ForceInventors: Eric A. Martin, Kenneth Vaccaro, Joseph P. Lorenzo, Andrew Davis
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Patent number: 5557117Abstract: A heterojunction bipolar transistor includes a collector contact layer constituted by a high-concentration first semiconductor layer of a first conductivity type formed on a semiconductor substrate, a collector region stacked on the collector contact layer, a base layer constituted by a fifth semiconductor layer of a second conductivity type formed on the collector region, and an emitter layer constituted by a semiconductor layer of the first conductivity type formed on the base layer.Type: GrantFiled: May 11, 1994Date of Patent: September 17, 1996Assignee: Nippon Telegraph and Telephone CorporationInventors: Yutaka Matsuoka, Eiichi Sano, Kenji Kurishima, Hiroki Nakajima, Tadao Ishibashi
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Patent number: 5536954Abstract: An optically coupled FET comprised of bottom layer, a top layer in which FET is formed and an intermediate layer having a waveguide communicating with a grating in registration with the FET.Type: GrantFiled: August 17, 1994Date of Patent: July 16, 1996Assignee: The United States of America as represented by the Secretary of the ArmyInventors: Arye Rosen, Arthur C. Paolella, Peter R. Herczfeld, Joseph H. Abeles
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Patent number: 5528059Abstract: An amplification-type photoelectric conversion device utilizes a JFET and is capable of amplifying charges generated by photoelectric conversion with a high amplification factor and improves the S/N ratio. The device is provided with a drive circuit for respectively applying driving signals to a source region, a drain region and a gate electrode of the JFET. The drive circuit has a first signal mode for accumulating charges generated by incident light on the JFET, and a second signal mode for causing the flow of current between the source and the drain and raising a potential difference between the source and the drain to a high level thereby causing an impact-ionization effect corresponding to an amount of the charges accumulated by the first mode to accumulate the resulting charges. A signal output corresponding to a total amount of the charges accumulated by the first and second modes is delivered from the drain.Type: GrantFiled: November 30, 1994Date of Patent: June 18, 1996Assignee: Nikon CorporationInventor: Tadao Isogai
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Patent number: 5485018Abstract: A nanofabricated logic device, operable at multiple (more than two) logic levels comprises asymmetrically coupled quantum point contacts provided with respective sources and drains and a coupling region between gate electrodes. The quantum mechanical carrier wavefunction in the region of QPC1, 2 is spatially asmmetric with alternate quantised energy levels lying either in QPC1, or QPC2, so that by changing the energy level, the conductance of the device can be switched between multiple stable conductance levels. The device can be used to provide a multilevel output switched in response to terahertz pulses provided by an array of optical detectors.Type: GrantFiled: May 27, 1994Date of Patent: January 16, 1996Assignee: Hitachi, Ltd.Inventors: Kensuke Ogawa, Jeremy Allam
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Patent number: 5473172Abstract: A hetero junction bipolar transistor which is high both in operating speed and in gain. The hetero junction bipolar transistor has a base layer consisting of Si (silicon) grown laterally by epitaxial growth, which isolates a collector region and an external base region from each other.Type: GrantFiled: October 5, 1994Date of Patent: December 5, 1995Assignee: Rohm Co., Ltd.Inventor: Keita Nii
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Patent number: 5468978Abstract: Active semiconductor devices including heterojunction diodes and thin film transistors are formed by PECVD deposition of a boron carbide thin film on an N-type substrate. The boron to carbon ratio of the deposited material is controlled so that the film has a suitable band gap energy. Boron carbides such as B.sub.4.7 C, B.sub.7.2 C and B.sub.19 C have suitable band gap energies between 0.8 and 1.7 eV. The stoichiometry of the film can be selected by varying the partial pressure of precursor gases, such as nido pentaborane and methane. The precursor gas or gases are energized, e.g., in a plasma reactor. The heterojunction diodes retain good rectifying properties at elevated temperature, e.g., up to 400.degree. C.Type: GrantFiled: July 7, 1993Date of Patent: November 21, 1995Inventor: Peter A. Dowben
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Patent number: 5466954Abstract: A phototransistor is provided with a first resistor that operates as a shunt and a second resistor that operates to protect the device from damage that could be caused by a reverse bias condition. The possible damage results from the creation of a PN junction relationship caused by the doping of N conductivity type material with P.sup.+ conductivity type material in order to form the first resistor. This junction relationship creates a parasitic diode that provides a current path between the emitter and collector terminals of the phototransistor. In order to prevent damage that might occur during a reverse voltage connection, a second resistor is connected between the emitter of transistor Q.sub.1 and the first resistor. The second resistor is in series with the junction relationship resulting from the structure used to form the first resistor and therefore serves to limit the current flowing between the emitter and collector terminals of the transistor under reversed bias conditions.Type: GrantFiled: December 21, 1994Date of Patent: November 14, 1995Assignee: Honeywell Inc.Inventors: Jose J. Aizpuru, Walter T. Matzen
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Patent number: 5455451Abstract: Superconductized electronic devices, such as a Josephson junction device, or superconductized optical devices represented by a light emitting and receiving devices of semiconductor laser are available using semiconductor materials which normally have no superconducting characteristics. The devices can operate by controlling the behavior of a Cooper pair in an active region which is formed in the semiconductor in advance using the penetrating phenomenon of the Cooper pair caused in the semiconductor proximate to the superconductor.Type: GrantFiled: April 22, 1993Date of Patent: October 3, 1995Assignee: Hitachi, Ltd.Inventors: Toshiyuki Usagawa, Masashi Kawasaki, Kensuke Ogawa, Toshiyuki Aida
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Patent number: 5453630Abstract: An optical detector comprised of a MESFET having a larger than usual separation between its source and drain electrodes and a channel between the source and drain electrodes doped with carriers having a density of at least 10.sup.18 /cm.sup.3 whereby variation in the voltage of the gate electrode changes the optical gain.Type: GrantFiled: August 19, 1994Date of Patent: September 26, 1995Assignee: The United States of America as represented by the Secretary of the ArmyInventors: Arthur Paolella, Peter R. Herczfeld
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Patent number: 5453629Abstract: A photoelectric conversion device includes a plurality of photoelectric conversion units and a signal output unit. The signal output unit has at least one storage device for storing electrical signals generated by the photoelectric conversion device. A scanning device scans the electrical signals generated by the electric conversion units, and a reading device reads out electrical signals generated by the photoelectric conversion units. Each of the photoelectric conversion units includes a light absorption layer and a multiplication layer. The multiplication layer includes at least one step-back structure which multiplies carriers produced by absorption of light, and in which a forbidden band width changes continuously from a minimum to a maximum width.Type: GrantFiled: November 12, 1993Date of Patent: September 26, 1995Assignee: Canon Kabushiki KaishaInventors: Ihachiro Gofuku, Masato Yamanobe, Izumi Tabata, Hiraku Kozuka
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Patent number: 5414282Abstract: The invention provides a heterostructure optoelectronic switching device showing a switch operation in response to a light injection for a subsequent light emission. The switching device comprises a pair of first and second bipolar transistors made of semiconductors showing a direct band-to-band transition. Each of the first and second bipolar transistors comprises collector and emitter layers and a base layer having a narrower energy band gap than energy band gaps of the collector and emitter layers. The base layers of the first and second bipolar transistors are connected to the collector layers of the second and first bipolar transistors respectively to allow the device to have a positive feedback feature. The emitter layers of the first and second bipolar transistors are connected to a first terminal.Type: GrantFiled: July 20, 1993Date of Patent: May 9, 1995Assignee: NEC CorporationInventor: Ichiro Ogura
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Patent number: 5399880Abstract: A long wavelength (6 to 20 .mu.m) phototransistor is described which has n-doped silicon as emitter and collector regions bracketing a base region having a quantum well structure made up of alternating layers of p-doped silicon germanium and undoped silicon, The silicon germanium layer adjacent to the emitter region is thicker and has a higher percentage of germanium in order to provide a quantum well that is wider and deeper than the other quantum wells in the base region thereby resulting in a larger current and optical gain. The silicon barrier layer of the quantum well closest to the collector region is p-doped in order to reduce the leakage current of the base-collector junction.Type: GrantFiled: August 10, 1993Date of Patent: March 21, 1995Assignee: AT&T Corp.Inventor: Naresh Chand
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Patent number: 5389797Abstract: A photodetector that is responsive to a wavelength or wavelengths of interest which have heretofore been unrealized. The photodetector includes a resonant cavity structure bounded by first and second reflectors, the resonant cavity structure being resonant at the wavelength or wavelengths of interest for containing a plurality of standing waves therein. The photodetector further includes a radiation absorbing region disposed within the resonant cavity structure, the radiation absorbing region including a plurality of radiation absorbing layers spaced apart from one another by a distance substantially equal to a distance between antinodes of adjacent ones of the standing waves. Each of radiation absorbing layers is spatially positioned at a location of one of the antinodes of one of the standing waves such that radiation absorption is enhanced. The radiation absorbing layers may be either bulk layers or quantum wells includes a plurality of layers, each of which is comprised of a strained layer of InGaAs.Type: GrantFiled: February 24, 1993Date of Patent: February 14, 1995Assignee: The United States of America as represented by the Secretary of the Department of EnergyInventors: Robert P. Bryan, Gregory R. Olbright, Thomas M. Brennan, Jeffrey Y. Tsao
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Monolithic in-based III-V compound semiconductor focal plane array cell with single stage CCD output
Patent number: 5386128Abstract: A monolithic semiconductor imager includes an indium-based III-V compound semiconductor monolithic active layer of a first conductivity type, an array of plural focal plane cells on the active layer, each of the focal plane cells including a photogate over a top surface of the active layer, a readout circuit dedicated to the focal plane cell including plural transistors formed monolithically with the monolithic active layer and a single-stage charge coupled device formed monolithically with the active layer between the photogate and the readout circuit for transferring photo-generated charge accumulated beneath the photogate during an integration period to the readout circuit. The photogate includes thin epitaxial semiconductor layer of a second conductivity type overlying the active layer and an aperture electrode overlying a peripheral portion of the thin epitaxial semiconductor layer, the aperture electrode being connectable to a photogate bias voltage.Type: GrantFiled: January 21, 1994Date of Patent: January 31, 1995Assignee: The United States of America as represented by the Administrator of the National Aeronautics and Space AdministrationInventors: Eric R. Fossum, Thomas J. Cunningham, Timothy N. Krabach, Craig O. Staller -
Patent number: 5367177Abstract: An optical device which uses a heterojunction field effect detector (HFED) having wavelength selectivity through the use of ion-implantation, and a wavelength selective grating. The device incorporates a Grinsch layer structure with a single GaAs quantum well. The optical power from the lens couples into a guided mode. The absorbing region is the quantum well itself. In the operation of the HFED, a positive bias is applied to the gate, and the depleted GaAs quantum well below the gate absorbs the photons, generating electron-hole pairs. The photocarriers are separated by the electric field before recombination can occur. The photocurrent is then produced in the external circuit by appropriately biasing the device. For collecting the electrons, a positive bias is applied to both the source and drain contacts, which act as dual drain contacts. The holes are removed via the collector which is maintained at ground. To maximize the responsivity (i.e.Type: GrantFiled: May 28, 1993Date of Patent: November 22, 1994Assignee: The United States of America as represented by the Secretary of the Air ForceInventors: Geoffrey W. Taylor, Steve Sargood
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Patent number: 5365477Abstract: A vertically integrated DRAM cell having a storage time of at least 4.5 hours at room temperature, formed from a wide-bandgap semiconductor such as GaAs or AlGaAs, in which an n-p-n bipolar access transistor is merged with a p-n-p storage capacitor, with the middle p-n layers being common to both. Similarly, a p-n-p transistor can be merged with an n-p-n storage capacitor.Type: GrantFiled: June 16, 1992Date of Patent: November 15, 1994Assignee: The United States of America as represented by the Secretary of the NavyInventors: James A. Cooper, Jr., Michael R. Melloch, Theresa B. Stellwag
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Patent number: 5345097Abstract: A heterojunction bipolar transistor includes a collector region made of first-conduction-type InP. and a base region connected to the collector region and made of second-conduction-type In.sub.x (Ga.sub.y Al.sub.1-y).sub.1-x As where the letters "x" and "y" denote predetermined atomic fractions. The atomic fraction "x" is in the range of 0.52 to 0.53. The atomic fraction "y" is in the range of 0.35 to 0.72.Type: GrantFiled: September 23, 1992Date of Patent: September 6, 1994Assignee: Matsushita Electric Industrial, Co., Ltd.Inventor: Atsushi Nakagawa
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Patent number: 5343054Abstract: According to this invention, a phototransistor includes an n-type InP emitter layer formed on an n.sup.+ -type InP substrate, a p.sup.- -type InGaAsP base layer, and a light-absorbing n.sup.- -type InGaAsP collector layer. An undoped InGaAs multiple quantum well layer is interposed between the emitter and base layers. An emitter electrode is in contact with the substrate, and a collector electrode is in contact with an n.sup.+ -type InP cap layer for covering the collector layer. A reverse bias voltage is applied across the emitter and collector electrodes. The rate at which electrons injected from the emitter layer to the quantum well layer and holes injected from the collector layer to the quantum well layer are combined with each other and disappear in a state wherein detection light is not incident is higher than that in a state wherein the detection light is incident. For this reason, a digital output signal can be directly obtained from the transistor action of this invention.Type: GrantFiled: September 14, 1993Date of Patent: August 30, 1994Assignee: Kabushiki Kaisha ToshibaInventors: James T. Maroney, III, Hideto Furuyama
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Patent number: 5332911Abstract: A semiconductor radiation detector with layer-wise construction and a contive region having a two-dimensional or quasi one-dimensional electron or hole gas is provided in which adiabatic transport in edge channels occurs at least regionally and in which at least two contacts are provided to this conductive region. The transport in the edge channels is disturbed by interaction with the electromagnetic radiation to be detected, i.e. an increase of the scattering rate between the edge channels is caused. This leads to a change of the resistance measurable between the contacts, with a means being provided for measuring the change of resistance to thereby detect the incident radiation.Type: GrantFiled: January 17, 1992Date of Patent: July 26, 1994Assignee: Max-Planck-Gesellschaft zur Foerderung der Wissenschaften, e.V.Inventors: Klaus von Klitzing, Gerhard Mueller, Edgar Diessel, Dieter Weiss
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Patent number: 5329137Abstract: An optical switch comprises a heterojunction transistor having a source electrode, a gate, a mesa, and three self-aligned waveguides, the mesa being ion implanted and having a single quantum well under the gate electrode, the single quantum well being comprises of undoped, narrow bandgap material bound on both sides by regions p-doped, wide bandgap material, both of said p-doped regions have symmetrically graded bandgaps, being most narrow next to the quantum well and increasing out to a wide and constant value away from the quantum well. A highly n-doped and totally depleted charge sheet is placed in a wide bandgap material, very near the gate side of the quantum well heterojunction. The charge sheet serves to induce a voltage controllable inversion channel within the quantum well.Type: GrantFiled: May 21, 1993Date of Patent: July 12, 1994Assignee: The United States of America as represented by the Secretary of the Air ForceInventors: Geoffrey W. Taylor, Tim Vang
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Patent number: 5321294Abstract: A shift register according to the present invention includes: a plurality of first electrodes; at least one second electrode; a voltage application unit for applying a voltage to each of the plurality of first electrodes; a plurality of optically bistable elements connected to each of the plurality of first electrodes and at least one second electrode; and an optical waveguide layer for optically coupling the plurality of optically bistable elements to each other.Type: GrantFiled: June 24, 1993Date of Patent: June 14, 1994Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Toyoji Chino, Kenichi Matsuda
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Patent number: 5311047Abstract: An amorphous Si/SiC heterojunction color-sensitive phototransistor was successfully fabricated by plasma-enhanced chemical vapor deposition. The structure is glass/ITO/a-Si(n.sup.+ -i-p.sup.+)/a-SiC(i-n.sup.+)/Al. The device is a bulk barrier transistor with a wide-bandgap amorphous SiC emitter. The phototransistor revealed a very high optical gain of 40 and a response speed of 10 us at an input light power of 5 uW and a collector current of 0.12 mA at a voltage of 14 V. The peak response occurs at 610 nm under 1 V bias and changes to 420 and 540 nm under 7- and 13-V biases, respectively.Type: GrantFiled: November 16, 1988Date of Patent: May 10, 1994Assignee: National Science CouncilInventor: Chun-Yen Chang