Abstract: A porous substrate for epitaxial growth includes an underlying layer made of III-nitride semiconductor which is grown on a sapphire substrate, a void-formation preventive layer which is grown on the underlying layer, a porous III-nitride semiconductor layer and a porous metallic layer on the porous III-nitride semiconductor layer.

Abstract: An interline transfer type image sensing device that can be operated at high speed and with low image smear is described. The device incorporates a refractory metal layer which is used for both a light shield over the vertical charge transfer region and as a wiring layer for low resistance strapping of poly crystalline silicon (polysilicon) gate electrodes for the vertical charge transfer region. Plugs provided by a separate metallization layer connect the refractory light shield to the polysilicon gate electrode. These plugs allow high temperature processing after refractory light shield patterning for improved sensor performance without degradation of the polysilicon gate electrode or the refractory lightshield layer.

Abstract: The present invention includes a photodiode having a first p-type semiconductor layer and an n-type semiconductor layer coupled by a second p-type semiconductor layer. The second p-type semiconductor layer has graded doping along the path of the carriers. In particular, the doping is concentration graded from a high value near the anode to a lower p concentration towards the cathode. By grading the doping in this way, an increase in absorption is achieved, improving the responsivity of the device. Although this doping increases the capacitance relative to an intrinsic semiconductor of the same thickness, the pseudo electric field that is created by the graded doping gives the electrons a very high velocity which more than compensates for this increased capacitance.

Abstract: An avalanche photodiode having a reduced capacitance is provided. The avalanche photodiode includes a wide band gap layer in its depletion region. The width of the wide band gap layer increases the extent of the depletion region, thereby reducing the capacitance while minimizing the impact on the dark current.

Abstract: A method of forming a low-defect, substantially relaxed SiGe-on-insulator substrate material is provided. The method includes first forming a Ge-containing layer on a surface of a first single crystal Si layer which is present atop a barrier layer that is resistant to Ge diffusion. A heating step is then performed at a temperature that approaches the melting point of the final SiGe alloy and retards the formation of stacking fault defects while retaining Ge. The heating step permits interdiffusion of Ge throughout the first single crystal Si layer and the Ge-containing layer thereby forming a substantially relaxed, single crystal SiGe layer atop the barrier layer. Moreover, because the heating step is carried out at a temperature that approaches the melting point of the final SiGe alloy, defects that persist in the single crystal SiGe layer as a result of relaxation are efficiently annihilated therefrom.

Abstract: According to the present invention, there is provided a new GaN-based field effect transistor of a normally-off type, which has an extremely small ON resistance during operation and is capable of a large-current operation.

Abstract: According to the present invention, there is a provided a semiconductor device having, a collector contact layer made of an n-type GaAs layer; a first collector layer formed on the collector contact layer and made of an n-type GaAs layer; a second collector layer formed on the first collector layer and made of a p-type GaAs layer; a third collector layer formed on the second collector layer and made of an n-type InGaP layer; a fourth collector layer formed on the third collector layer and made of an n-type InGaP layer having an impurity concentration higher than that of the third collector layer; a fifth collector layer formed on the fourth collector layer and made of an n-type GaAs layer; a base layer formed on the fifth collector layer and made of a p-type GaAs layer; and an emitter layer formed on the base layer and made of an n-type InGaP layer.

Abstract: A semiconductor device includes: a first semiconductor layer represented by a composition formula AlxGa1-xN (0?x?1) a first conductivity type or non-doped second semiconductor layer represented by a composition formula AlyGa1-yN (0?y?1, x<y) and formed on the first semiconductor layer; a second conductivity type third semiconductor layer represented by a composition formula AlxGa1-xN (0?x?1) and selectively formed on the second semiconductor layer; a gate electrode formed on the third semiconductor layer; a source electrode electrically connected to the second semiconductor layer; and a drain electrode electrically connected to the second semiconductor layer. The distance between the drain electrode and the third semiconductor layer is longer than the distance between the source electrode and the third semiconductor layer.

Abstract: An apparatus includes a crystalline substrate having a top surface, a crystalline semiconductor layer located on the top surface, and a plurality of dielectric regions. The crystalline semiconductor layer includes group III-nitride and has first and second surfaces. The first surface is in contact with the top surface. The second surface is separated from the top surface by semiconductor of the crystalline semiconductor layer. The dielectric regions are located on the second surface. Each dielectric region is distant from the other dielectric regions and covers an end of an associated lattice defect. Each lattice defect threads the crystalline semiconductor layer.

Abstract: The present invention relates to a high voltage and high power gallium nitride (GaN) transistor structure. In general, the GaN transistor structure includes a sub-buffer layer that serves to prevent injection of electrons into a substrate during high voltage operation, thereby improving performance of the GaN transistor structure during high voltage operation. Preferably, the sub-buffer layer is aluminum nitride, and the GaN transistor structure further includes a transitional layer, a GaN buffer layer, and an aluminum gallium nitride Schottky layer.

Abstract: The present invention provides the photodetector comprising a lower cladding layer including a n-type doped region, an absorbing layer, an upper cladding layer including a p-type doped region, and ohmic electrodes connected to said lower cladding layer and said upper cladding layer, wherein said p-type doped region extends to be formed into said absorbing layer by a predetermined length. In accordance with present invention, by reducing effect of the hetero junction barrier where holes move in the intrinsic region, the operating voltage can be decreased and the bandwidth can be improved.

Abstract: An active region 30 is formed on a substrate 3, which is made of SiC, GaN, or GaAs, for example, by alternately layering undoped layers 22 with a thickness of for example about 50 nm and n-type doped layers 23 with a thickness (for example, about 10 nm) that is thin enough that quantum effects can be achieved. Carriers spread out into the undoped layers 22 from sub-bands of the n-type doped layers 23 that occur due to quantum effects. In the undoped layers 22, which have a low concentration of impurities, the scattering of impurities is reduced, and therefore a high carrier mobility can be obtained there, and when the entire active region 30 has become depleted, a large withstand voltage value can be obtained due to the undoped layers 22 by taking advantage of the fact that there are no more carriers in the active region 30.

Abstract: High quality epitaxial layers of monocrystalline materials (26) can be grown overlying monocrystalline substrates (22) such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer (24) comprises a layer of monocrystalline oxide spaced apart from a silicon wafer by an amorphous interface layer (28) of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. In addition, formation of a compliant substrate may include utilizing surfactant enhanced epitaxy and epitaxial growth of single crystal silicon onto single crystal oxide materials. A microresonator device is formed overlying the monocrystalline substrate.

Abstract: An implant-free enhancement mode metal-oxide semiconductor field effect transistor (EMOSFET) is provided. The EMOSFET has a III-V compound semiconductor substrate and an epitaxial layer structure overlying the III-V compound semiconductor substrate. The epitaxial material layer has a channel layer and at least one doped layer. A gate oxide layer overlies the epitaxial layer structure. The EMOSFET further includes a metal gate electrode overlying the gate oxide layer and source and drain ohmic contacts overlying the epitaxial layer structure.

Abstract: The invention includes providing gallium nitride materials including thermally conductive regions and methods to form such materials. The gallium nitride materials may be used to form semiconductor devices. The thermally conductive regions may include heat spreading layers and heat sinks. Heat spreading layers distribute beat generated during device operation over relatively large areas to prevent excessive localized heating. Heat sinks typically are formed at either the backside or topside of the device and facilitate heat dissipation to the environment. It may be preferable for devices to include a heat spreading layer which is connected to a heat sink at the backside of the device. A variety of semiconductor devices may utilize features of the invention including devices on silicon substrates and devices which generate large amounts of heat such as power transistors.

Abstract: The invention concerns an optoelectronic device comprising at alteration of at least three semiconductor layers with selected shape, and two air layers. The semiconductor layers having N-type or P-type doping which may differ or not from one layer to the next layer, are separated by spacers whereof the doping is non-intentional (I-type) or intentional (N-type or P-type) to define a PINIP or NIPIN structure with air cavities, and are adapted to be set at selected respective electric potentials. The respective thicknesses and compositions of the layers and the spacers are selected so that the structure has at least an optical transfer function adapted to light to be treated and adjustable in accordance with the selected potentials applied to the semiconductor layers.

Abstract: The invention is to realize such a semiconductor light-emitting element which is higher in external quantum efficiency than an existing LED, and lower in production cost than an existing semiconductor laser. The light transmission insulating film is formed on a continuously incline face comprising the semiconductor layers having an opening angle etched in right angled V. The V shape incline is formed by a known technique, and both left and right inclined faces have the angle of 45°. Depending on the length of ? or the position of the light reflecting portion, probability that the light in duration of resonance is reflected may be made optimum or preferable. According to this structure, it is no longer necessary to carry out processing treatments of high degree, high precision, or high cost such as, e.g.

Abstract: A highly reflecting back illuminated diode structure allows light that has not been absorbed by a semiconductor absorbing region to be back reflected for at least a second pass into the absorbing region. The diode structure in a preferred embodiment provides a highly reflecting layer of gold to be supported in part by a conducting alloyed electrode ring contact and in part by a passivation layer of SixNy. Conveniently this structure provides a window within the contact which allows light to pass between the absorbing region and the reflecting layer of gold.

Abstract: A compound tetrahedrally coordinated semiconductor structure, whose chemical formula is generally of the form IInIIImIVlVpVIq, where n, m, l, p, q represent the relative abundance of each element associated with a particular group of the periodic table. The flexibility of the chemical formula may be used to adjust the lattice constant and polarity to eliminate mismatches from substrates. Other properties, such as those of band gaps, can also be tuned. The design is amenable to layer-by-layer heteroepitaxial growth. In exemplary embodiments, a structure is provided that matches lattice constant and polarity with a Si(100) surface, while having a direct band gap of 1.59 ?m.

Abstract: A photodiode (111) and resistors (121) are formed on a semi-insulating InP substrate (101). The photodiode (111) is formed by subjecting a layered structure formed by successively depositing an n+-type InP cladding layer (102), an n-type InGaAsP core layer (103), a nondoped InGaAs active layer (104), a p-type InGaAsP core layer (105), and a p+-type InP cladding layer 106 on the InP substrate (101) to a selective etching process. The resistors (121) have the same layered structure as the photodiode (111). Photodiode (111) is connected to n-type wiring lines (131) and a p-type wiring line (141). Resistors (121) are connected to the n-type wiring lines (131) and the p-type wiring line (141) in parallel to the photodiode (111). A side surface on the side of the photodiode (111) of the InP substrate (101) is a cleavage plane, and the cleavage plane is coated with an antireflection film (161).

Abstract: A heterojunction bipolar transistor is presented, comprising a substrate having formed thereon a heterojunction bipolar transistor layer structure, and including an emitter layer. The emitter layer includes a strained, n-doped compound of indium arsenic and phosphorus. The transistor further comprises, between the substrate and emitter layer, a subcollector layer, a collector layer, a base layer, and an optional spacer layer. The emitter layer may include a graded portion. A contact layer is formed on the emitter layer to provide contacts for the device.

Abstract: An optical semiconductor device with a multiple quantum well structure, is set out in which well layers and barrier layers, comprising various types of semiconductor layers, are alternately layered. The device well layers comprise a first composition based on a nitride semiconductor material with a first electron energy. The barrier layers comprise a second composition of a nitride semiconductor material with electron energy which is higher in comparison to the first electron energy. The well and barrier layers are in the direction of growth, by a radiation-active quatum well layer which with the essentially non-radiating well layers (6a) and the barrier layers (6b), arranged in front, form a supperlattice.

Abstract: An AlGaInP layer is formed on a substrate made of GaAs, and an AlGaAs layer is formed on the AlGaInP layer via a buffer layer therebetween. The buffer layer has a thickness of about 1.1 nm and is made of AlGaInP whose Ga content is smaller than that of the AlGaInP layer. The buffer layer may alternatively be made of AlGaAs whose Al content is smaller than that of the AlGaAs layer.

Abstract: The present invention provides a method of manufacturing Group III nitride crystals that are of high quality, are manufactured highly efficiently, and are useful and usable as a substrate that is used in semiconductor manufacturing processes.

Abstract: A transistor structure having an gallium arsenide (GaAs) semiconductor substrate; a lattice match layer; an indium aluminum arsenide (InAlAs) barrier layer disposed over the lattice match layer; an InyGa1-yAs lower channel layer disposed on the barrier layer, where y is the mole fraction of In content in the lower channel layer; an InxGa1-xAs upper channel layer disposed on the lower channel layer, where x is the mole fraction of In content in the upper channel layer and where x is different from y; and an InAlAs Schottky layer on the InxGa1-xAs upper channel layer. The lower channel layer has a bandgap greater that the bandgap of the upper channel layer. The lower channel layer has a bulk electron mobility lower than the bulk electron mobility of the upper channel layer where.

Abstract: A unipolar photodiode and methods of making and using employ a Schottky contact as a cathode contact. The Schottky cathode contact is created directly on a carrier traveling or collector layer of the unipolar photodiode resulting in a simpler overall structure to use and make. The unipolar photodiode comprises a light absorption layer, the collector layer adjacent to the light absorption layer, the Schottky cathode contact in direct contact with the collector layer, and an anode contact either directly or indirectly interfaced to the light absorption layer. The light absorption layer has a doping concentration that is greater than a doping concentration of the collector layer. The light absorption layer has a band gap energy that is less than that of the collector layer. The light absorption layer and the collector layer may be of the same or opposite conduction type.

Abstract: A hetero-bipolar transistor according to the present invention enhances reliability that relates to the breaking of wiring metal. The transistor comprises a semiconductor substrate, a sub-collector layer formed on a (100) surface of the substrate, a collector mesa formed on the sub-collector layer, and an emitter contact layer. The transistor further includes a collector electrode and wiring metal connected to the collector electrode. The edge of the sub-collector layer forms a step S, the angle of which is in obtuse relative to the substrate. Therefore, the wiring metal traversing the step S bends in obtuse angle at the step S, thus reducing the breaking of the wiring metal.

Abstract: A heterojunction for a semiconductor device. The heterojunction has a first region formed from a first semiconductor material having a first conductivity type, a second region formed from a second semiconductor material having a second conductivity type, and an intermediate layer between the first region and the second region. The band line-up of the first region, the intermediate layer, and the second region has no bound states in its conduction band and no bound states in its valence band. The intermediate layer has a thickness small enough to allow electrons to tunnel from the first region to the second region with negligible attenuation. The semiconductor device may be a heterojunction bipolar transistor. The conduction band of the intermediate layer has a higher energy level than the conduction bands of the first and second regions.

Abstract: A gallium nitride-based multilayered reflective membrane with an excellent crystallinity while keeping a high reflectivity and a gallium nitride-based light emitting element using such a multilayered reflective are provided. The multilayered reflective membrane includes an AlaGa1−aN layer (0<a<1) having a thickness of (&agr;1·&lgr;)/(4n1) (&lgr;: incident light wavelength, n1: a reflectivity) and a GaN layer having a thickness of (&agr;2·&lgr;)/(4n2) (n2: a reflectivity) which are deposited alternately and satisfy the relationship of 0<&agr;1<1 and &agr;1+&agr;2=2.

Abstract: In aiming at cost lowering of an optical module and an optical transmission apparatus and with the objective of providing a semiconductor light receiving element that has a good coherence with the other edge emitting/incidence type optical devices and is capable of performing the positioning easily and with a high accuracy, in the edge emitting/incidence type light receiving element in which the light absorbing layer 19 has been formed, the space region is formed so as to provide at least 100 &mgr;m2 of the marker detecting region 24, thereby facilitating detection of marker 23 on the optical device 26 and executing the positioning of the light receiving element with a high accuracy, the space region resulting from eliminating a part of the light absorbing layer 19 that absorbs the detection light of the light receiving element, the transmission amount of the detection light toward the marker detecting region that is parallel to a primary plane being equal to 30% or higher, the detection light having penetrat

Abstract: An oxide layer on an indium phosphide semiconductor substrate is doped with silicon. This enables epitaxial layers to be deposited upon the substrate in a conventional manner, including mesa etching and overgrowth, to form a semiconductor structure. The doped oxide layer is thought to reduce diffusion of phosphorus out of the substrate and thus to reduce the zinc levels in the active region of the structure. Additionally, or as an alternative, after mesa etching oxide can be formed on the mesa sides and then doped with silicon. Conventional blocking layers can then be formed over the doped oxide, reducing the diffusion of zinc from the blocking layers into the rest of the structure.

Abstract: A quantum well made out of a the stack of layers of III-V semiconductor materials comprises, in addition to the quantum well, an electron storage layer separated from the quantum well by a transfer barrier layer. The barrier layer has a thickness that is greater than the thickness of the quantum well by about one order of magnitude. This barrier thus enables the separation of the absorption function (in the quantum well) and the function of reading the photocarriers (in the storage layer) and therefore the limiting of the rate of recombination of the carriers, thus improving the performance characteristics of the detector.

Abstract: A Group III-V compound semiconductor epitaxial layer has a tilt angle of at most 100 seconds and/or a tilt angle of at most 100 seconds. The layer is epitaxially grown by use of a mask, wherein the mask satisfies the equation (1): h≧(w/2)tan &thgr;  (1) where “&thgr;” is a base angle of a facet structure of the Group III-V compound semiconductor layer on the epitaxial growth; “h” is a thickness of the mask; and “w” is an opening width of the mask at its lower level, and the opening width is defined in a direction included in a plane which is vertical to both the surface of the base layer and the side face of the facet structure.

Abstract: A semiconductor light emitting diode. The semiconductor light emitting diode includes a substrate on which an n-type semiconductor layer, an active layer, and a p-type semiconductor layer are sequentially stacked, and a p-type electrode, which includes a first metallic layer formed on the p-type semiconductor layer and a second metallic layer that is formed on the first metallic layer and reflects light generated from the active layer.

Abstract: A high frequency, low power dissipation electronic device capable of operating at low voltage, and optoelectronic devices which includes a barium fluoride substrate, particularly BaF2 substrate having crystallographic (100) contact surface, and at least two semiconducting layers disposed thereon particularly selected from compounds of elements of Groups II, III, IV, V and VI of the Periodic Table.

Abstract: A Group III nitride compound semiconductor light-emitting element (flip chip type light-emitting element) provided with a p-side electrode and an n-side electrode formed on one surface side, wherein the p-side electrode includes: a first metal layer containing Ag and formed on a p-type semiconductor layer; a protective film with which the first metal layer except a part region is covered; and a second metal layer not containing Ag and formed on the protective film.

Abstract: A semiconductor device comprises: a semiconductor substrate on which a silicon germanium film, a carbon-containing silicon film and a silicon film are formed in this order and a gate electrode on the semiconductor substrate with intervention of a gate oxide film, wherein a channel region of the semiconductor device the is formed in the carbon-containing silicon film or wherein a channel region of the semiconductor device is formed in the silicon germanium film.

Abstract: An undoped In0.52Al0.48As buffer layer (thickness: 500 nm), an undoped In0.53Ga0.47As channel layer (thickness: 30 nm), an n-type delta doped layer for shortening the distance between the channel layer and a gate electrode and attaining a desired carrier density, an undoped In0.52Al0.48As Schottky layer, and an n-type In0.53Ga0.47As cap layer doped with Si (thickness: 50 nm) are formed in this order on the principal surface of an Fe-doped InP semi-insulating substrate. An n-type GaAs protective layer doped with Si (thickness: 7.5 nm) is formed between the cap layer and source/drain electrodes for protecting the cap layer.

Abstract: An avalanche photodiode charge-carrier multiplication region comprises a first region fabricated from a first material having a first impact ionization threshold and a second region joined to the first region at an interface and fabricated from a second material having a second impact ionization threshold lower than the first impact ionization threshold. The first region includes, in the presence of an applied reverse-bias, first and second oppositely charged layers to establish an elevated, localized electric field within a sub-region of the first region. The first and second charged layers are arranged such that preferred charge carriers are accelerated by the localized electric field just prior to being injected into the second material where they impact ionize at predetermined statistical rate.

Abstract: The group III-V semiconductor device comprises a quantum well layer, barrier layers sandwiching the quantum well layer and a region of a third semiconductor material formed by spatially-selective intermixing of atoms on the group V sublattice between the first semiconductor material of the quantum well layer and the second semiconductor material of the barrier layer. The quantum well layer is a layer of a first semiconductor material that has a band gap energy and a refractive index. The barrier layers are layers of a second semiconductor material that has a higher band gap energy and a lower refractive index than the first semiconductor material. The third semiconductor material has a band gap energy and a refractive index intermediate between the band gap energy and the refractive index, respectively, of the first semiconductor material and the second semiconductor material.

Abstract: A semiconductor light receiving element having a light receiving layer (1) formed from a GaN group semiconductor, and an electrode (2) formed on one surface of the light receiving layer as a light receiving surface (1a) in such a way that the light (L) can enter the light receiving layer is provided. When the light receiving element is of a Schottky barrier type, the aforementioned electrode (2) contains at least a Schottky electrode, which is formed in such a way that, on the light receiving surface (1a), the total length of the boundary lines between areas covered with the Schottky electrode and exposed areas is longer than the length of the outer periphery of the light receiving surface (1a).

Abstract: A semiconductor integrated circuit device includes a silicon substrate having a first region and a second region identical in conductivity type to the first region and having a lower dopant concentration than the first region, a second MOS transistor on a main surface of the second region as a radio frequency switch circuit switching on and off input and output of a radio frequency signal, and a first MOS transistor on a main surface of the first region in a radio frequency circuit other than the radio frequency switch circuit. A high performance, highly reliable semiconductor integrated circuit with an RE switch circuit provided on a silicon substrate as a system on a chip.

Abstract: A p-n tunnel junction between a p-type semiconductor layer and a n-type semiconductor layer provides current injection for an edge-emitting nitride based semiconductor laser structure. The amount of p-type material in the nitride based semiconductor laser structure can be minimized, with attendant advantages in electrical, thermal, and optical performance, and in fabrication.

Abstract: A semiconductor optical device includes a semiconductor substrate and a stacked body formed by at least a first cladding layer, an active region and a second cladding layer; wherein both sides of the stacked body are buried by a burying layer formed by a semi-insulating semiconductor crystal; the burying layer includes a first layer that is placed adjacent to both sides of the stacked body and a second layer that is placed adjacent to the first layer; the first layer includes Ru as a dopant; composition of the second layer is different from the composition of the first layer, or a dopant of the second layer is different from the dopant of the first layer. The device can also be configured such that the width of the active region is smaller than the width of the cladding layers of the stacked body; and a Ru-doped semi-insulating layer is provided in a space between the burying layer and the active region in both sides of the active region.

Abstract: Device for photodetection with a vertical metal semiconductor microresonator and procedure for the manufacture of this device. According to the invention, in order to detect an incident light, at least one element is formed over an insulating layer (2) that does not absorb this light, including a semiconductor material (6) and at least two electrodes (4) holding the element, with the element and electrode unit being suitable for absorbing this light and designed to incease the light intensity with respect to the incident light, in particular by making a surface plasmon mode resonate between the unit interfaces with the layer and the propagation medium for the incident light, with the resonance of this mode taking place in teh interface between the element and atleast one of the electrodes, with this mode being excited by the component of the magnetic field of the light, parallel to the electrodes. Application for optical telecommunications.

Abstract: High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer comprises a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline material layer. A monocrystalline layer is then formed over the accommodating buffer layer, such that a lattice constant of the monocrystalline layer substantially matches the lattice constant of a subsequently grown monocrystalline film.

Abstract: A structure with an optically active layer embedded in a Si wafer, such that the outermost epitaxial layer exposed to the CMOS processing equipment is always Si or another CMOS-compatible material such as SiO2. Since the optoelectronic layer is completely surrounded by Si, the wafer is fully compatible with standard Si CMOS manufacturing. For wavelengths of light longer than the bandgap of Si (1.1 &mgr;m), Si is completely transparent and therefore optical signals can be transmitted between the embedded optoelectronic layer and an external waveguide using either normal incidence (through the Si substrate or top Si cap layer) or in-plane incidence (edge coupling).

Abstract: A bipolar transistor is provided, which is low in collector-to-emitter saturation voltage, small in size and to be manufactured by a reduced number of processes, and a semiconductor device formed with such a bipolar transistor and a MOS transistor on a same substrate. A high concentration region for reducing the collector-to-emitter saturation voltage VCE(sat) is formed in a manner surrounding a base region of an NPN transistor. This high concentration region is not necessarily formed in such a depth as reaching a buried layer, and can be reduced in the spread in a lateral direction Because a high concentration region can be formed in a same process as upon forming source and drain regions for an NMOS transistor to be formed together with an NPN transistor on a same silicon substrate, it is possible to omit a diffusion process exclusive for forming a high concentration region and hence to manufacture a semiconductor device through a reduced number of processes.

Abstract: An integrated circuit is provided that includes a substrate incorporating a semiconductor photodiode device having a p-n junction. The photodiode device includes at least one capacitive trench buried in the substrate and connected in parallel with the junction. In a preferred embodiment, the substrate is formed from silicon, and the capacitive trench includes an internal doped silicon region partially enveloped by an insulating wall that laterally separates the internal region from the substrate. Also provided is a method for fabricating an integrated circuit including a substrate that incorporates a semiconductor photodiode device having a p-n junction.

Abstract: A hot-electron bolometric mixer/detector, which uses the nonlinearities of the heated two-dimensional electron gas medium, is described. Electrons in the illustrative embodiment of the present invention are “velocity-cooled” rather than “diffusion-cooled” or “phonon-cooled” like hot-electron bolometric mixer/detectors in the prior art. The illustrative embodiment is velocity-cooled when the elastic mean-free path of the electrons is greater than the channel length, L, of the mixer/detector. In this case, the motion of the hot electrons is more accurately modeled by their speed rather than in accordance with diffusion models. This leads to a mixer/detector with a wider modulation bandwidth at a lower power than is exhibited by mixer/detectors in the prior art.