Si X Ge 1-x Patents (Class 257/19)
  • Patent number: 11428690
    Abstract: A plasmonic photoconductor sensing platform is provided. The plasmonic photoconductor sensing platform includes an insulating substrate; a semiconducting film placed on top of the insulating substrate; two metal contacts placed at least in part on the semiconducting film to enforce an electric field; a plurality of plasmonic nanostructures deposited on the semiconducting film and physically separated from metal contacts; an insulating layer, the insulating electrically isolating the plasmonic nanostructures from semiconductor; at least one energy source; and at least one microfluidic channel disposed on the insulating layer.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: August 30, 2022
    Assignee: University of Miami
    Inventors: Xu Han, Hossein Shokri Kojori, Roger M. LeBlanc, Sung Jin Kim
  • Patent number: 11404575
    Abstract: Techniques are disclosed for forming diverse transistor channel materials enabled by a thin, inverse-graded, germanium (Ge)-based layer. The thin, inverse-graded, Ge-based layer (e.g., having a thickness of at most 500 nm) can then serve as a template for the growth of compressively strained PMOS channel material and tensile strained NMOS channel material to achieve gains in hole and electron mobility, respectively, in the channel regions of the devices. Such a relatively thin Ge-based layer can be formed with suitable surface quality/relaxation levels due to the inverse grading of the Ge concentration in the layer, where the Ge concentration is relatively greatest near the substrate and relatively lowest near the overlying channel material layer. In addition to the inverse-graded Ge concentration, the Ge-based layer may be characterized by the nucleation, and predominant containment, of defects at/near the interface between the substrate and the Ge-based layer.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: August 2, 2022
    Assignee: Intel Corporation
    Inventors: Karthik Jambunathan, Cory C. Bomberger, Glenn A. Glass, Anand S. Murthy, Ju H. Nam, Tahir Ghani
  • Patent number: 11404590
    Abstract: The present disclosure provides a photo sensing device, the photo sensing device includes a substrate, including a silicon layer at a front surface, a photosensitive member extending into and at least partially surrounded by the silicon layer, and a composite layer disposed between the photosensitive member and the silicon layer and surrounding the photosensitive member, wherein the composite layer includes a first material and a second material different from the first material.
    Type: Grant
    Filed: March 24, 2020
    Date of Patent: August 2, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventor: Chan-Hong Chern
  • Patent number: 11393939
    Abstract: The present disclosure provides a photo sensing device, the photo sensing device includes a substrate, including a silicon layer at a front surface, a photosensitive member extending into and at least partially surrounded by the silicon layer, and a superlattice layer disposed between the photosensitive member and the silicon layer, wherein the superlattice layer includes a first material and a second material different from the first material, a first concentration of the second material at a portion of the superlattice layer proximal to the photosensitive member is greater than a second concentration of the second material at a portion of the superlattice layer distal to the photosensitive member.
    Type: Grant
    Filed: July 6, 2020
    Date of Patent: July 19, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chan-Hong Chern, Weiwei Song, Chih-Chang Lin, Lan-Chou Cho, Min-Hsiang Hsu
  • Patent number: 11393765
    Abstract: A heterogeneous semiconductor structure, including a first integrated circuit and a second integrated circuit, the second integrated circuit being a photonic integrated circuit. The heterogeneous semiconductor structure may be fabricated by bonding a multi-layer source die, in a flip-chip manner, to the first integrated circuit, removing the substrate of the source die, and fabricating one or more components on the source die, using etch and/or deposition processes, to form the second integrated circuit. The second integrated circuit may include components fabricated from cubic phase gallium nitride compounds, and configured to operate at wavelengths shorter than 450 nm.
    Type: Grant
    Filed: February 14, 2020
    Date of Patent: July 19, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Daniel N. Carothers
  • Patent number: 11393940
    Abstract: A photodetector is provided. The photodetector includes a semiconductor layer, a first superlattice structure in the semiconductor layer, and a light absorption material above the first superlattice structure. The first superlattice structure includes vertically stacked pairs of silicon layer/first silicon germanium layer. The first silicon germanium layers are made of Si1-xGex, and x is the atomic percentage of germanium and 0.1?x?0.9.
    Type: Grant
    Filed: August 17, 2020
    Date of Patent: July 19, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Chan-Hong Chern
  • Patent number: 11361581
    Abstract: An optical sensor includes: a sensing unit including a first sensing electrode, a second sensing electrode spaced apart from the first sensing electrode, and a sensing layer between the first sensing electrode and the second sensing electrode, the sensing layer containing amorphous silicon and germanium (Ge) ions impregnated in the amorphous silicon; and an optical pattern unit on the sensing unit and including a light shielding pattern and a plurality of transmission patterns in the light shielding pattern, wherein the sensing layer includes a first region, a second region, and a third region sequentially arranged from a boundary between the second sensing electrode and the sensing layer toward the first electrode, and a concentration of the germanium (Ge) ions in the amorphous silicon is relatively higher in the second region than in the first region and the third region.
    Type: Grant
    Filed: August 21, 2020
    Date of Patent: June 14, 2022
    Assignee: Samsung Display Co., Ltd.
    Inventors: SangJin Park, Cha-Dong Kim, Heena Kim, Inkyung Yoo, SungBae Ju, Taehyeok Choi
  • Patent number: 11342457
    Abstract: Strained thin film transistors are described. In an example, an integrated circuit structure includes a strain inducing layer on an insulator layer above a substrate. A polycrystalline channel material layer is on the strain inducing layer. A gate dielectric layer is on a first portion of the polycrystalline channel material. A gate electrode is on the gate dielectric layer, the gate electrode having a first side opposite a second side. A first conductive contact is adjacent the first side of the gate electrode, the first conductive contact on a second portion of the polycrystalline channel material. A second conductive contact adjacent the second side of the gate electrode, the second conductive contact on a third portion of the polycrystalline channel material.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: May 24, 2022
    Assignee: Intel Corporation
    Inventors: Prashant Majhi, Willy Rachmady, Brian S. Doyle, Abhishek A. Sharma, Elijah V. Karpov, Ravi Pillarisetty, Jack T. Kavalieros
  • Patent number: 11302823
    Abstract: A method for making a semiconductor device may include forming a superlattice on a semiconductor substrate and including a plurality of stacked groups of layers. Each group of layers of the superlattice may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. A first at least one non-semiconductor monolayer may be constrained within the crystal lattice of a first pair of adjacent base semiconductor portions and comprise a first non-semiconductor material, and a second at least one non-semiconductor monolayer may be constrained within the crystal lattice of a second pair of adjacent base semiconductor portions and comprise a second non-semiconductor material different than the first non-semiconductor material.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: April 12, 2022
    Assignee: ATOMERA INCORPORATED
    Inventors: Keith Doran Weeks, Nyles Wynn Cody
  • Patent number: 11255792
    Abstract: A surface enhanced Raman spectroscopy (SERS) sensor may include a nano structured surface and a nonstoichiometric oxide layer. The nano structured surfers may include a first peak, a second peak and a valley between the first peak and the second peak. The non-stoichiometric oxide layer may include a first portion on the first peak and a second portion on the second peak.
    Type: Grant
    Filed: July 21, 2016
    Date of Patent: February 22, 2022
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Ning Ge, Anita Rogacs, Steven J. Simske, Milo Overbay, Viktor Shkolnikov
  • Patent number: 11239368
    Abstract: In an embodiment, a device includes: a semiconductor substrate having a channel region; a gate stack over the channel region; and an epitaxial source/drain region adjacent the gate stack, the epitaxial source/drain region including: a main portion in the semiconductor substrate, the main portion including a semiconductor material doped with gallium, a first concentration of gallium in the main portion being less than the solid solubility of gallium in the semiconductor material; and a finishing portion over the main portion, the finishing portion doped with gallium, a second concentration of gallium in the finishing portion being greater than the solid solubility of gallium in the semiconductor material.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: February 1, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Martin Christopher Holland, Blandine Duriez, Marcus Johannes Henricus van Dal, Yasutoshi Okuno
  • Patent number: 11198951
    Abstract: A method of fabricating at least one single-crystal alloy semiconductor structure. At least one seed, containing an alloying material, on a substrate for growth of at least one single-crystal alloy semiconductor structure is formed. At least one structural form, formed of a host material, on the substrate is crystallized to form the at least one single-crystal alloy semiconductor structure. The at least one structural form is heated such that the material of the at least one structural form has a liquid state. Also, the at least one structural form is cooled, such that the material of the at least one structural form nucleates at the least one seed and crystallizes as a single crystal to provide at least one single-crystal alloy semiconductor structure, with a growth front of the single crystal propagating in a main body of the respective structural form away from the respective seed.
    Type: Grant
    Filed: June 5, 2015
    Date of Patent: December 14, 2021
    Assignee: University of Southampton
    Inventors: Frederic Yannick Gardes, Graham Trevor Reed, Callum George Littlejohns
  • Patent number: 11159246
    Abstract: A grating- and fiber-coupled multi-beam coherent receiving system in a mid- and far-infrared band includes a mid- and far-infrared local oscillator signal source, a phase grating, a multi-beam fiber coupling system, a 2×2 pixel mid- and far-infrared superconducting HEB mixer, a multi-channel DC bias source, a multi-channel cryogenic low-noise amplifier, and a room-temperature intermediate-frequency and high-resolution spectrum processing unit. In a 2×2 multi-beam superconducting receiving system, an echelle grating and a cryogenic optical fiber are used to distribute and couple the local oscillator signal, and the mid- and far-infrared band high-sensitivity superconducting HEB mixer is used to realize efficient local oscillator signal distribution and coupling, and ultimately achieve high-sensitivity and high-resolution multi-beam spectrum reception in the mid- and far-infrared band.
    Type: Grant
    Filed: July 16, 2020
    Date of Patent: October 26, 2021
    Assignee: PURPLE MOUNTAIN OBSERVATORY, CHINESE ACADEMY OF SCIENCES
    Inventors: Yuan Ren, Shengcai Shi, Daixi Zhang
  • Patent number: 11121235
    Abstract: A structure and a manufacturing method of a metal-oxide-semiconductor field-effect transistor with an element of IVA group ion implantation are disclosed. The element of IVA group ion implantation layer is disposed in a body and close to an interface between a gate oxide layer and the body. The element of IVA group ion implantation layer is utilized to change a property of a channel of the structure.
    Type: Grant
    Filed: July 24, 2019
    Date of Patent: September 14, 2021
    Assignee: National Tsing Hua University
    Inventors: Chih-Fang Huang, Jheng-Yi Jiang, Sheng-Hong Wang, Jia-Qing Hung
  • Patent number: 11121254
    Abstract: A transistor with strained superlattices as source/drain regions includes a substrate. A gate structure is disposed on the substrate. Two superlattices are respectively disposed at two sides of the gate structure and embedded in the substrate. The superlattices are strained. Each of the superlattices is formed by a repeated alternating stacked structure including a first epitaxial silicon germanium and a second epitaxial silicon germanium. The superlattices serve as source/drain regions of the transistor.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: September 14, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Bo-Shiun Chen, Chun-Jen Chen, Chung-Ting Huang, Chi-Hsuan Tang, Jhong-Yi Huang, Guan-Ying Wu
  • Patent number: 11099078
    Abstract: An acoustic sensor has a MEMS die with MEMS structure. Among other things, the MEMS structure includes a diaphragm configured to mechanically respond to incident acoustic signals, and a temperature sensor member configured to detect temperature.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: August 24, 2021
    Assignee: Vesper Technologies, Inc.
    Inventors: Robert Littrell, Yu Hui, Craig Core, Ronald Gagnon
  • Patent number: 11063053
    Abstract: An SRAM structure comprises first and second semiconductor fins, and a gate structure. The first semiconductor fin is formed within a P-well region. The second semiconductor fin is formed within an N-well region abutting the P-well region. The gate structure extends across the first semiconductor fin and the second semiconductor fin, and forms a pull-down transistor with the first semiconductor fin and a pull-up transistor with the second semiconductor fin. The gate structure comprises a first work function metal layer extending within the P-well region and a second work function metal layer extending from the first work function metal layer to within the N-well region, and the second work function metal layer is thicker than the first work function metal layer.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: July 13, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Jhon-Jhy Liaw
  • Patent number: 11049939
    Abstract: A device structure with multiple layers of low temperature epitaxy is disclosed that eliminates source and drain and extension implants, providing a planar interface with abrupt junctions between epitaxial extensions and substrate, mitigating electrostatic coupling between transistor drain and transistor channel and reducing short channel effects. The reduction of channel doping results in improved device performance from reduced impurity scattering and reduction of random dopant induced threshold voltage variations (sigma-Vt). Avoiding implants further reduces device sigma-Vt due to random dopants' diffusion from source and drain extensions, which creates device channel length variations during thermal activation anneal of implanted dopants. The defined transistor structure employs at least two levels of low-temperature epitaxy, and creates a planar interface with various types of transistor substrates resulting in performance improvement.
    Type: Grant
    Filed: August 2, 2016
    Date of Patent: June 29, 2021
    Assignee: SemiWise Limited
    Inventor: Asen Asenov
  • Patent number: 11004878
    Abstract: Structures including a photodiode and methods of fabricating such structures. A substrate has a top surface, a well, and a trench extending from the top surface to the well. A photodiode is positioned in the trench. The photodiode includes an electrode that is provided by a first portion of the well. A bipolar junction transistor has an emitter that is positioned over the top surface of the substrate and a subcollector that is positioned below the top surface of the substrate. The subcollector is provided by a second portion of the well.
    Type: Grant
    Filed: August 19, 2019
    Date of Patent: May 11, 2021
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Anthony K. Stamper, Vibhor Jain, Steven M. Shank, John J. Ellis-Monaghan, John J. Pekarik
  • Patent number: 10991655
    Abstract: An e-fuse and a manufacturing method thereof, and a memory cell are provided. The method includes: providing a semiconductor substrate including a preset active region; forming an isolating region on the substrate, where the isolating region and the preset active region have a height difference and are connected by at least one side wall; forming a negative electrode and a positive electrode on the preset active region; and forming a fuse link on the side wall for connecting the negative electrode and the positive electrode. Accordingly, the line width of the fuse link is out of the limitation of the limit line width of the semiconductor process, the actual line width of the e-fuse may be smaller than the limit line width of the semiconductor process, and low fusing current is required for fusing.
    Type: Grant
    Filed: October 25, 2019
    Date of Patent: April 27, 2021
    Assignee: SHENZHEN WEITONGBO TECHNOLOGY CO., LTD.
    Inventors: Wenxuan Wang, Jian Shen, Hongchao Wang
  • Patent number: 10978353
    Abstract: An integrated circuit containing an n-channel finFET and a p-channel finFET is formed by forming a first polarity fin epitaxial layer for a first polarity finFET, and subsequently forming a hard mask which exposes an area for a second, opposite, polarity fin epitaxial layer for a second polarity finFET. The second polarity fin epitaxial layer is formed in the area exposed by the hard mask. A fin mask defines the first polarity fin and second polarity fin areas, and a subsequent fin etch forms the respective fins. A layer of isolation dielectric material is formed over the substrate and fins. The layer of isolation dielectric material is planarized down to the fins. The layer of isolation dielectric material is recessed so that the fins extend at least 10 nanometers above the layer of isolation dielectric material. Gate dielectric layers and gates are formed over the fins.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: April 13, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Manoj Mehrotra, Charles Frank Machala, III, Rick L. Wise, Hiroaki Niimi
  • Patent number: 10957540
    Abstract: A method includes providing a semiconductor structure having an active region and an isolation structure adjacent to the active region, the active region having source and drain regions sandwiching a channel region for a transistor, the semiconductor structure further having a gate structure over the channel region. The method further includes etching a trench in one of the source and drain regions, wherein the trench exposes a portion of a sidewall of the isolation structure, epitaxially growing a first semiconductor layer in the trench, epitaxially growing a second semiconductor layer over the first semiconductor layer, changing a crystalline facet orientation of a portion of a top surface of the second semiconductor layer by an etching process, and epitaxially growing a third semiconductor layer over the second semiconductor layer after the changing of the crystalline facet orientation.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: March 23, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wen-Chin Chen, Cheng-Yi Wu, Yu-Hung Cheng, Ren-Hua Guo, Hsiang Liu, Chin-Szu Lee
  • Patent number: 10937868
    Abstract: A method for making a semiconductor device may include forming a hyper-abrupt junction region above a substrate and including a first semiconductor layer having a first conductivity type, a first superlattice layer on the first semiconductor layer, a second semiconductor layer on the first superlattice layer and having a second conductivity type different than the first conductivity type, and a second superlattice layer on the second semiconductor layer. The method may further include forming a gate dielectric layer on the second superlattice layer of the hyper-abrupt junction region, forming a gate electrode on the gate dielectric layer, and forming spaced apart source and drain regions adjacent the hyper-abrupt junction region.
    Type: Grant
    Filed: July 17, 2019
    Date of Patent: March 2, 2021
    Assignee: ATOMERA INCORPORATED
    Inventors: Richard Burton, Marek Hytha, Robert J. Mears
  • Patent number: 10886406
    Abstract: The present disclosure provides a semiconductor structure and a method for preparing the semiconductor structure. The semiconductor structure includes a substrate having a pattern-dense region and a pattern-loose region; a first drain stressor disposed in the pattern-dense region; a first source stressor disposed in the pattern-dense region; a buried gate structure disposed in the pattern-dense region, between the first drain stressor and the first source stressor; a second drain stressor disposed in the pattern-loose region; a second source stressor disposed in the pattern-loose region; and a planar gate structure disposed in the pattern-loose region, between the second drain stressor and the second source stressor.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: January 5, 2021
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Chang-Chieh Lin
  • Patent number: 10879396
    Abstract: A method for forming a semiconductor device is provided. The method includes forming a gate stack to partially cover a semiconductor structure. The method also includes forming a first semiconductor material over the semiconductor structure. The method further includes forming a second semiconductor material over the first semiconductor material. In addition, the method includes forming a third semiconductor material over the second semiconductor material. The first semiconductor material and the third semiconductor material together surround the second semiconductor material. The second semiconductor material has a greater dopant concentration than that of the first semiconductor material or that of the third semiconductor material.
    Type: Grant
    Filed: April 17, 2020
    Date of Patent: December 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shahaji B. More, Zheng-Yang Pan, Chun-Chieh Wang, Cheng-Han Lee, Shih-Chieh Chang
  • Patent number: 10879353
    Abstract: Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. The techniques can be implemented, for example, using a standard contact stack such as a series of metals on, for example, silicon or silicon germanium (SiGe) source/drain regions. In accordance with one example such embodiment, an intermediate boron doped germanium layer is provided between the source/drain and contact metals to significantly reduce contact resistance. Numerous transistor configurations and suitable fabrication processes will be apparent in light of this disclosure, including both planar and non-planar transistor structures (e.g., FinFETs), as well as strained and unstrained channel structures. Graded buffering can be used to reduce misfit dislocation. The techniques are particularly well-suited for implementing p-type devices, but can be used for n-type devices if so desired.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: December 29, 2020
    Assignee: Intel Corporation
    Inventors: Glenn A. Glass, Anand S. Murthy, Tahir Ghani
  • Patent number: 10868175
    Abstract: Some embodiments of the present disclosure provide a method for fabricating a semiconductor structure. The method includes forming a recess in a substrate and forming an epitaxy region, comprising a multilayer structure with a substance having a first lattice constant larger than a second lattice constant of the substrate. Forming the epitaxy region further includes forming a first layer in proximity to an interface between the epitaxy region and the substrate with an average concentration of the substance from about 20 to about 32 percent by an in situ growth, and forming a second layer over the first layer, a bottom portion of the second layer having a concentration of the substance from about 27 percent to about 37 percent by an in situ growth operation.
    Type: Grant
    Filed: February 12, 2018
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Shin-Jiun Kuang, Tsung-Hsing Yu, Yi-Ming Sheu
  • Patent number: 10861896
    Abstract: In some embodiments, a semiconductor device is provided. The semiconductor device includes an epitaxial structure having a group IV chemical element disposed in a semiconductor substrate, where the epitaxial structure extends into the semiconductor substrate from a first side of the semiconductor substrate. A photodetector is at least partially arranged in the epitaxial structure. A first capping structure having a first capping structure chemical element that is different than the first group IV chemical element covers the epitaxial structure on the first side of the semiconductor substrate. A second capping structure is arranged between the first capping structure and the epitaxial structure, where the second capping structure includes the group IV chemical element and the first capping structure chemical element.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: December 8, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Chun Liu, Chung-Yi Yu, Eugene Chen
  • Patent number: 10854450
    Abstract: The present disclosure describes patterned devices and methods for repairing substrate lattice damage in a patterned device. The patterned device includes a substrate, an alternating conductor and dielectric stack atop the substrate, a channel hole extending through the alternating conductor and dielectric stack to the substrate, and an epitaxial grown layer at a bottom of the channel hole and a top surface of the substrate. A part of the substrate in contact with the epitaxial grown layer has a dopant or doping concentration different from an adjacent part of the substrate. The method includes forming a channel hole in an insulating layer atop a substrate, forming an amorphous layer in a top side of the substrate below the channel hole, heating to crystallize the amorphous layer, and growing an epitaxial layer on the crystallized layer in the channel hole.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: December 1, 2020
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Xiao Jun Wang, Wei Zhou, Lin Kang Xu, Guan Nan Li
  • Patent number: 10825920
    Abstract: Energy-filtered cold electron devices use electron energy littering through discrete energy levels of quantum wells or quantum dots that are formed through band bending of tunneling barrier conduction band. These devices can obtain low effective electron temperatures of less than or equal to 45K at room temperature, steep electrical current turn-on/turn-off capabilities with a steepness of less than or equal to 10 mV/decade at room temperature, subthreshold swings of less than or equal to 10 mV/decade at room temperature, and/or supply voltages of less than or equal to 0.1 V.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: November 3, 2020
    Assignee: Board of Regents, The University of Texas System
    Inventors: Seong Jin Koh, Pradeep Bhadrachalam, Liang-Chieh Ma
  • Patent number: 10804203
    Abstract: The semiconductor device includes: a transistor having a gate electrode formed on a semiconductor substrate and first and second source/drain regions formed in portions of the semiconductor substrate on both sides of the gate electrode; a gate interconnect formed at a position opposite to the gate electrode with respect to the first source/drain region; and a first silicon-germanium layer formed on the first source/drain region to protrude above the top surface of the semiconductor substrate. The gate interconnect and the first source/drain region are connected via a local interconnect structure that includes the first silicon-germanium layer.
    Type: Grant
    Filed: August 17, 2017
    Date of Patent: October 13, 2020
    Assignee: Pannova Semic
    Inventors: Tsutomu Oosuka, Hisashi Ogawa, Yoshihiro Sato
  • Patent number: 10797137
    Abstract: A method for controlling Schottky barrier height in a semiconductor device includes forming an alloy layer including at least a first element and a second element on a first surface of a semiconductor substrate. The semiconductor substrate is a first element-based semiconductor substrate, and the first element and the second element are Group IV elements. A first thermal anneal of the alloy layer and the first element-based substrate is performed. The first thermal anneal causes the second element in the alloy layer to migrate towards a surface of the alloy layer. A Schottky contact layer is formed on the alloy layer after the first thermal anneal.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: October 6, 2020
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Hung-Hsiang Cheng, Samuel C. Pan
  • Patent number: 10749559
    Abstract: A receiver receives a wide band signal in a range comprising a front end to the receiver including a complementary metal-oxide-semiconductor (CMOS). The CMOS includes a dipole antenna that receives a received signal; a hybrid-based broadband isolation structure that receives the received signal and a local oscillator LO signal and passes through the LO signal to a sub-harmonic mixer. The sub-harmonic mixer mixes the received signal with the local oscillator signal to generate an intermediate frequency (IF) signal to the hybrid-based broadband isolation structure.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: August 18, 2020
    Assignee: Board of Regents, The University of Texas System
    Inventors: Qian Zhong, Kenneth K. O, Wooyeol Choi
  • Patent number: 10720496
    Abstract: FinFETs and methods of forming finFETs are described. According to some embodiments, a structure includes a channel region, first and second source/drain regions, a dielectric layer, and a gate electrode. The channel region includes semiconductor layers above a substrate. Each of the semiconductor layers is separated from neighboring ones of the semiconductor layers, and each of the semiconductor layers has first and second sidewalls. The first and second sidewalls are aligned along a first and second plane, respectively, extending perpendicularly to the substrate. The first and second source/drain regions are disposed on opposite sides of the channel region. The semiconductor layers extend from the first source/drain region to the second source/drain region. The dielectric layer contacts the first and second sidewalls of the semiconductor layers, and the dielectric layer extends into a region between the first plane and the second plane. The gate electrode is over the dielectric layer.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: July 21, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Yi Peng, Chih Chieh Yeh, Tsung-Lin Lee
  • Patent number: 10600786
    Abstract: Manufacture of a transistor device with at least one P type transistor with channel structure strained in uniaxial compression strain starting from a silicon layer strained in biaxial tension, by amorphization recrystallization then germanium condensation.
    Type: Grant
    Filed: March 7, 2017
    Date of Patent: March 24, 2020
    Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, STMICROELECTRONICS Inc
    Inventors: Sylvain Maitrejean, Emmanuel Augendre, Pierre Morin, Shay Reboh
  • Patent number: 10600870
    Abstract: A semiconductor structure is provided that includes a silicon germanium alloy fin having a second germanium content located on a first portion of a substrate. The structure further includes a laterally graded silicon germanium alloy material portion located on a second portion of the substrate. The laterally graded silicon germanium alloy material portion is spaced apart from the silicon germanium alloy fin and has end portions having the second germanium content and a middle portion located between the end portions that has a first germanium content that is less than the second germanium content.
    Type: Grant
    Filed: August 22, 2017
    Date of Patent: March 24, 2020
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek
  • Patent number: 10580866
    Abstract: A semiconductor device may include a semiconductor layer, spaced apart source and drain regions in the semiconductor layer with a channel region extending therebetween, and at least one dopant diffusion blocking superlattice dividing at least one of the source and drain regions into a lower region and an upper region with the upper region having a same conductivity and higher dopant concentration than the lower region. The at least one dopant diffusion blocking superlattice comprising a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The semiconductor device may further include a gate on the channel region.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: March 3, 2020
    Assignee: ATOMERA INCORPORATED
    Inventors: Hideki Takeuchi, Daniel Connelly, Marek Hytha, Richard Burton, Robert J. Mears
  • Patent number: 10580867
    Abstract: A FINFET may include a semiconductor fin, spaced apart source and drain regions in the semiconductor fin with a channel region extending therebetween, and at least one dopant diffusion blocking superlattice dividing at least one of the source and drain regions into a lower region and an upper region with the upper region having a same conductivity and higher dopant concentration than the lower region. The dopant diffusion blocking superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The semiconductor device may further include a gate on the channel region.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: March 3, 2020
    Assignee: ATOMERA INCORPORATED
    Inventors: Hideki Takeuchi, Daniel Connelly, Marek Hytha, Richard Burton, Robert J. Mears
  • Patent number: 10546858
    Abstract: Monolithic finFETs including a majority carrier channel in a first III-V compound semiconductor material disposed on a second III-V compound semiconductor. While a mask, such as a sacrificial gate stack, is covering the channel region, a source of an amphoteric dopant is deposited over exposed fin sidewalls and diffused into the first III-V compound semiconductor material. The amphoteric dopant preferentially activates as a donor within the first III-V material and an acceptor with the second III-V material, providing transistor tip doping with a p-n junction between the first and second III-V materials. A lateral spacer is deposited to cover the tip portion of the fin. Source/drain regions in regions of the fin not covered by the mask or spacer electrically couple to the channel through the tip region. The channel mask is replaced with a gate stack.
    Type: Grant
    Filed: June 27, 2015
    Date of Patent: January 28, 2020
    Assignee: Intel Corporation
    Inventors: Jack T. Kavalieros, Chandra S. Mohapatra, Anand S. Murthy, Willy Rachmady, Matthew V. Metz, Gilbert Dewey, Tahir Ghani, Harold W. Kennel
  • Patent number: 10546963
    Abstract: Methods and systems for germanium-on-silicon photodetectors without germanium layer contacts are disclosed and may include, in a semiconductor die having a photodetector, where the photodetector includes an n-type silicon layer, a germanium layer, a p-type silicon layer, and a metal contact on each of the n-type silicon layer and the p-type silicon layer: receiving an optical signal, absorbing the optical signal in the germanium layer, generating an electrical signal from the absorbed optical signal, and communicating the electrical signal out of the photodetector via the n-type silicon layer and the p-type silicon layer. The photodetector may include a horizontal or vertical junction double heterostructure where the germanium layer is above the n-type and p-type silicon layers. An intrinsically-doped silicon layer may be below the germanium layer between the n-type silicon layer and the p-type silicon layer. A top portion of the germanium layer may be p-doped.
    Type: Grant
    Filed: October 29, 2015
    Date of Patent: January 28, 2020
    Assignee: Luxtera, Inc.
    Inventors: Kam-Yan Hon, Gianlorenzo Masini, Subal Sahni
  • Patent number: 10541176
    Abstract: A method of forming vertical fin field effect transistors, including, forming a silicon-germanium cap layer on a substrate, forming at least four vertical fins and silicon-germanium caps from the silicon-germanium cap layer and the substrate, where at least two of the at least four vertical fins is in a first subset and at least two of the at least four vertical fins is in a second subset, forming a silicon-germanium doping layer on the plurality of vertical fins and silicon-germanium caps, removing the silicon-germanium doping layer from the at least two of the at least four vertical fins in the second subset, and removing the silicon-germanium cap from at least one of the at least two vertical fins in the first subset, and at least one of the at least two vertical fins in the second subset.
    Type: Grant
    Filed: April 6, 2018
    Date of Patent: January 21, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Zhenxing Bi, Kangguo Cheng, Juntao Li, Peng Xu
  • Patent number: 10529738
    Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. An exemplary method for fabricating an integrated circuit includes providing a substrate including a semiconductor layer over an insulator layer. The method includes selectively replacing portions of the semiconductor layer with insulator material to define an isolated semiconductor layer region. Further, the method includes selectively forming a relaxed layer on the isolated semiconductor layer region. Also, the method includes selectively forming a strained layer on the relaxed layer. The method forms a device over the strained layer.
    Type: Grant
    Filed: April 28, 2016
    Date of Patent: January 7, 2020
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Raj Verma Purakh, Shaoqiang Zhang, Rui Tze Toh
  • Patent number: 10529835
    Abstract: Energy-filtered cold electron devices use electron energy filtering through discrete energy levels of quantum wells or quantum dots that are formed through band bending of tunneling barrier conduction band. These devices can obtain low effective electron temperatures of less than or equal to 45K at room temperature, steep electrical current turn-on/turn-off capabilities with a steepness of less than or equal to 10 mV/decade at room temperature, subthreshold swings of less than or equal to 10 mV/decade at room temperature, and/or supply voltages of less than or equal to 0.1 V.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: January 7, 2020
    Inventors: Seong Jin Koh, Pradeep Bhadrachalam, Liang-Chieh Ma
  • Patent number: 10510871
    Abstract: Methods are disclosed for forming a multi-layer structure including highly controlled diffusion interfaces between alternating layers of different semiconductor materials. According to embodiments, during a deposition of semiconductor layers, the process is controlled to remain at low temperatures such that an inter-diffusion rate between the materials of the deposited layers is managed to provide diffusion interfaces with abrupt Si/SiGe interfaces. The highly controlled interfaces and first and second layers provide a multi-layer structure with improved etching selectivity. In an embodiment, a gate all-around (GAA) transistor is formed with horizontal nanowires (NWs) from the multi-layer structure with improved etching selectivity. In embodiments, horizontal NWs of a GAA transistor may be formed with substantially the same size diameters and silicon germanium (SiGe) NWs may be formed with “all-in-one” silicon (Si) caps.
    Type: Grant
    Filed: August 16, 2018
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shahaji B. More, Shih-Chieh Chang
  • Patent number: 10481090
    Abstract: Differential, plasmonic, non-dispersive infrared gas sensors are provided. In one aspect, a gas sensor includes: a plasmonic resonance detector including a differential plasmon resonator array that is resonant at different wavelengths of light; and a light source incident on the plasmonic resonance detector. The differential plasmon resonator array can include: at least one first set of plasmonic resonators interwoven with at least one second set of plasmonic resonators, wherein the at least one first set of plasmonic resonators is configured to be resonant with light at a first wavelength, and wherein the at least one second set of plasmonic resonators is configured to be resonant with light at a second wavelength. A method for analyzing a target gas and a method for forming a plasmonic resonance detector are also provided.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: November 19, 2019
    Assignee: International Business Machines Corporation
    Inventors: Abram L. Falk, Damon B. Farmer, Shu-Jen Han
  • Patent number: 10461203
    Abstract: A semiconductor device comprises a plurality of quantum structures comprising predominantly germanium. The plurality of quantum structures are formed on a first semiconductor layer structure. The quantum structures of the plurality of quantum structures have a lateral dimension of less than 15 nm and an area density of at least 8×1011 quantum structures per cm2. The plurality of quantum structures are configured to emit light with a light emission maximum at a wavelength of between 2 ?m and 10 ?m or to absorb light with a light absorption maximum at a wavelength of between 2 ?m and 10 ?m.
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: October 29, 2019
    Assignee: Infineon Technologie AG
    Inventors: Stefan Clara, Thomas Grille, Ursula Hedenig, Peter Irsigler, Bernhard Jakoby, Ventsislav M. Lavchiev, Thomas Ostermann, Thomas Popp
  • Patent number: 10453945
    Abstract: A semiconductor device may include at least one double-barrier resonant tunneling diode (DBRTD). The at least one DBRTD may include a first doped semiconductor layer and a first barrier layer on the first doped semiconductor layer and including a superlattice. The superlattice may include stacked groups of layers, each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The at least one DBRTD may further include an intrinsic semiconductor layer on the first barrier layer, a second barrier layer on the intrinsic semiconductor layer, and a second doped semiconductor layer on the second superlattice layer.
    Type: Grant
    Filed: August 7, 2017
    Date of Patent: October 22, 2019
    Assignee: ATOMERA INCORPORATED
    Inventors: Robert J. Mears, Hideki Takeuchi, Marek Hytha
  • Patent number: 10453960
    Abstract: Field-effect transistor, the source and drain regions whereof are formed from a crystalline structure comprising: a first layer comprising two main faces parallel to one another and two lateral faces parallel to one another, the main faces being perpendicular to the lateral faces, a second layer overlapping the first layer, the second layer comprising a first main face and a second main face parallel to one another and two lateral faces, the first main face being in contact with the first layer, the lateral faces forming an angle ? in the range 50° to 59°, and preferably a 53° angle, with the first main face.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: October 22, 2019
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Vincent Mazzocchi, Laurent Grenouillet
  • Patent number: 10446392
    Abstract: A method of forming a 3D NAND structure having self-aligned nanodots includes depositing alternating layers of an oxide and a nitride on a substrate; at least partially recessing the nitride layers; and forming SiGe nanodots on the nitride layers. A method of forming a 3D NAND structure having self-aligned nanodots includes depositing alternating layers of an oxide and a nitride on a substrate; at least partially recessing the nitride layers; and forming SiGe nanodots on the nitride layers by a process including maintaining a temperature of the substrate below about 560° C.; flowing a silicon epitaxy precursor into the chamber; forming a silicon epitaxial layer on the substrate at the nitride layers; flowing germanium gas into the chamber with the silicon epitaxy precursor; and forming a silicon germanium epitaxial layer on the substrate at the nitride layers.
    Type: Grant
    Filed: January 26, 2018
    Date of Patent: October 15, 2019
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Sungwon Jun, Saurabh Chopra, Thomas Jongwan Kwon, Er-Xuan Ping
  • Patent number: 10396165
    Abstract: A strain relaxed silicon germanium layer that has a low defect density is formed on a surface of a silicon substrate without causing wafer bowing. The strain relaxed silicon germanium layer is formed using multiple epitaxial growing, bonding and transferring steps. In the present application, a thick silicon germanium layer having a low defect density is grown on a transferred portion of a topmost silicon germanium sub-layer of an initial strain relaxed silicon germanium graded buffer layer and then bonded to a silicon substrate. A portion of the thick silicon germanium layer is then transferred to the silicon substrate. Additional steps of growing a thick silicon germanium layer having a low defect density, bonding and layer transfer may be performed as necessary.
    Type: Grant
    Filed: February 22, 2018
    Date of Patent: August 27, 2019
    Assignee: International Business Machines Corporation
    Inventors: Praneet Adusumilli, Keith E. Fogel, Alexander Reznicek, Oscar van der Straten