Si X Ge 1-x Patents (Class 257/19)
  • Patent number: 11121254
    Abstract: A transistor with strained superlattices as source/drain regions includes a substrate. A gate structure is disposed on the substrate. Two superlattices are respectively disposed at two sides of the gate structure and embedded in the substrate. The superlattices are strained. Each of the superlattices is formed by a repeated alternating stacked structure including a first epitaxial silicon germanium and a second epitaxial silicon germanium. The superlattices serve as source/drain regions of the transistor.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: September 14, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Bo-Shiun Chen, Chun-Jen Chen, Chung-Ting Huang, Chi-Hsuan Tang, Jhong-Yi Huang, Guan-Ying Wu
  • Patent number: 11121235
    Abstract: A structure and a manufacturing method of a metal-oxide-semiconductor field-effect transistor with an element of IVA group ion implantation are disclosed. The element of IVA group ion implantation layer is disposed in a body and close to an interface between a gate oxide layer and the body. The element of IVA group ion implantation layer is utilized to change a property of a channel of the structure.
    Type: Grant
    Filed: July 24, 2019
    Date of Patent: September 14, 2021
    Assignee: National Tsing Hua University
    Inventors: Chih-Fang Huang, Jheng-Yi Jiang, Sheng-Hong Wang, Jia-Qing Hung
  • Patent number: 11099078
    Abstract: An acoustic sensor has a MEMS die with MEMS structure. Among other things, the MEMS structure includes a diaphragm configured to mechanically respond to incident acoustic signals, and a temperature sensor member configured to detect temperature.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: August 24, 2021
    Assignee: Vesper Technologies, Inc.
    Inventors: Robert Littrell, Yu Hui, Craig Core, Ronald Gagnon
  • Patent number: 11063053
    Abstract: An SRAM structure comprises first and second semiconductor fins, and a gate structure. The first semiconductor fin is formed within a P-well region. The second semiconductor fin is formed within an N-well region abutting the P-well region. The gate structure extends across the first semiconductor fin and the second semiconductor fin, and forms a pull-down transistor with the first semiconductor fin and a pull-up transistor with the second semiconductor fin. The gate structure comprises a first work function metal layer extending within the P-well region and a second work function metal layer extending from the first work function metal layer to within the N-well region, and the second work function metal layer is thicker than the first work function metal layer.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: July 13, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Jhon-Jhy Liaw
  • Patent number: 11049939
    Abstract: A device structure with multiple layers of low temperature epitaxy is disclosed that eliminates source and drain and extension implants, providing a planar interface with abrupt junctions between epitaxial extensions and substrate, mitigating electrostatic coupling between transistor drain and transistor channel and reducing short channel effects. The reduction of channel doping results in improved device performance from reduced impurity scattering and reduction of random dopant induced threshold voltage variations (sigma-Vt). Avoiding implants further reduces device sigma-Vt due to random dopants' diffusion from source and drain extensions, which creates device channel length variations during thermal activation anneal of implanted dopants. The defined transistor structure employs at least two levels of low-temperature epitaxy, and creates a planar interface with various types of transistor substrates resulting in performance improvement.
    Type: Grant
    Filed: August 2, 2016
    Date of Patent: June 29, 2021
    Assignee: SemiWise Limited
    Inventor: Asen Asenov
  • Patent number: 11004878
    Abstract: Structures including a photodiode and methods of fabricating such structures. A substrate has a top surface, a well, and a trench extending from the top surface to the well. A photodiode is positioned in the trench. The photodiode includes an electrode that is provided by a first portion of the well. A bipolar junction transistor has an emitter that is positioned over the top surface of the substrate and a subcollector that is positioned below the top surface of the substrate. The subcollector is provided by a second portion of the well.
    Type: Grant
    Filed: August 19, 2019
    Date of Patent: May 11, 2021
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Anthony K. Stamper, Vibhor Jain, Steven M. Shank, John J. Ellis-Monaghan, John J. Pekarik
  • Patent number: 10991655
    Abstract: An e-fuse and a manufacturing method thereof, and a memory cell are provided. The method includes: providing a semiconductor substrate including a preset active region; forming an isolating region on the substrate, where the isolating region and the preset active region have a height difference and are connected by at least one side wall; forming a negative electrode and a positive electrode on the preset active region; and forming a fuse link on the side wall for connecting the negative electrode and the positive electrode. Accordingly, the line width of the fuse link is out of the limitation of the limit line width of the semiconductor process, the actual line width of the e-fuse may be smaller than the limit line width of the semiconductor process, and low fusing current is required for fusing.
    Type: Grant
    Filed: October 25, 2019
    Date of Patent: April 27, 2021
    Assignee: SHENZHEN WEITONGBO TECHNOLOGY CO., LTD.
    Inventors: Wenxuan Wang, Jian Shen, Hongchao Wang
  • Patent number: 10978353
    Abstract: An integrated circuit containing an n-channel finFET and a p-channel finFET is formed by forming a first polarity fin epitaxial layer for a first polarity finFET, and subsequently forming a hard mask which exposes an area for a second, opposite, polarity fin epitaxial layer for a second polarity finFET. The second polarity fin epitaxial layer is formed in the area exposed by the hard mask. A fin mask defines the first polarity fin and second polarity fin areas, and a subsequent fin etch forms the respective fins. A layer of isolation dielectric material is formed over the substrate and fins. The layer of isolation dielectric material is planarized down to the fins. The layer of isolation dielectric material is recessed so that the fins extend at least 10 nanometers above the layer of isolation dielectric material. Gate dielectric layers and gates are formed over the fins.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: April 13, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Manoj Mehrotra, Charles Frank Machala, III, Rick L. Wise, Hiroaki Niimi
  • Patent number: 10957540
    Abstract: A method includes providing a semiconductor structure having an active region and an isolation structure adjacent to the active region, the active region having source and drain regions sandwiching a channel region for a transistor, the semiconductor structure further having a gate structure over the channel region. The method further includes etching a trench in one of the source and drain regions, wherein the trench exposes a portion of a sidewall of the isolation structure, epitaxially growing a first semiconductor layer in the trench, epitaxially growing a second semiconductor layer over the first semiconductor layer, changing a crystalline facet orientation of a portion of a top surface of the second semiconductor layer by an etching process, and epitaxially growing a third semiconductor layer over the second semiconductor layer after the changing of the crystalline facet orientation.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: March 23, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wen-Chin Chen, Cheng-Yi Wu, Yu-Hung Cheng, Ren-Hua Guo, Hsiang Liu, Chin-Szu Lee
  • Patent number: 10937868
    Abstract: A method for making a semiconductor device may include forming a hyper-abrupt junction region above a substrate and including a first semiconductor layer having a first conductivity type, a first superlattice layer on the first semiconductor layer, a second semiconductor layer on the first superlattice layer and having a second conductivity type different than the first conductivity type, and a second superlattice layer on the second semiconductor layer. The method may further include forming a gate dielectric layer on the second superlattice layer of the hyper-abrupt junction region, forming a gate electrode on the gate dielectric layer, and forming spaced apart source and drain regions adjacent the hyper-abrupt junction region.
    Type: Grant
    Filed: July 17, 2019
    Date of Patent: March 2, 2021
    Assignee: ATOMERA INCORPORATED
    Inventors: Richard Burton, Marek Hytha, Robert J. Mears
  • Patent number: 10886406
    Abstract: The present disclosure provides a semiconductor structure and a method for preparing the semiconductor structure. The semiconductor structure includes a substrate having a pattern-dense region and a pattern-loose region; a first drain stressor disposed in the pattern-dense region; a first source stressor disposed in the pattern-dense region; a buried gate structure disposed in the pattern-dense region, between the first drain stressor and the first source stressor; a second drain stressor disposed in the pattern-loose region; a second source stressor disposed in the pattern-loose region; and a planar gate structure disposed in the pattern-loose region, between the second drain stressor and the second source stressor.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: January 5, 2021
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Chang-Chieh Lin
  • Patent number: 10879396
    Abstract: A method for forming a semiconductor device is provided. The method includes forming a gate stack to partially cover a semiconductor structure. The method also includes forming a first semiconductor material over the semiconductor structure. The method further includes forming a second semiconductor material over the first semiconductor material. In addition, the method includes forming a third semiconductor material over the second semiconductor material. The first semiconductor material and the third semiconductor material together surround the second semiconductor material. The second semiconductor material has a greater dopant concentration than that of the first semiconductor material or that of the third semiconductor material.
    Type: Grant
    Filed: April 17, 2020
    Date of Patent: December 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shahaji B. More, Zheng-Yang Pan, Chun-Chieh Wang, Cheng-Han Lee, Shih-Chieh Chang
  • Patent number: 10879353
    Abstract: Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. The techniques can be implemented, for example, using a standard contact stack such as a series of metals on, for example, silicon or silicon germanium (SiGe) source/drain regions. In accordance with one example such embodiment, an intermediate boron doped germanium layer is provided between the source/drain and contact metals to significantly reduce contact resistance. Numerous transistor configurations and suitable fabrication processes will be apparent in light of this disclosure, including both planar and non-planar transistor structures (e.g., FinFETs), as well as strained and unstrained channel structures. Graded buffering can be used to reduce misfit dislocation. The techniques are particularly well-suited for implementing p-type devices, but can be used for n-type devices if so desired.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: December 29, 2020
    Assignee: Intel Corporation
    Inventors: Glenn A. Glass, Anand S. Murthy, Tahir Ghani
  • Patent number: 10868175
    Abstract: Some embodiments of the present disclosure provide a method for fabricating a semiconductor structure. The method includes forming a recess in a substrate and forming an epitaxy region, comprising a multilayer structure with a substance having a first lattice constant larger than a second lattice constant of the substrate. Forming the epitaxy region further includes forming a first layer in proximity to an interface between the epitaxy region and the substrate with an average concentration of the substance from about 20 to about 32 percent by an in situ growth, and forming a second layer over the first layer, a bottom portion of the second layer having a concentration of the substance from about 27 percent to about 37 percent by an in situ growth operation.
    Type: Grant
    Filed: February 12, 2018
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Shin-Jiun Kuang, Tsung-Hsing Yu, Yi-Ming Sheu
  • Patent number: 10861896
    Abstract: In some embodiments, a semiconductor device is provided. The semiconductor device includes an epitaxial structure having a group IV chemical element disposed in a semiconductor substrate, where the epitaxial structure extends into the semiconductor substrate from a first side of the semiconductor substrate. A photodetector is at least partially arranged in the epitaxial structure. A first capping structure having a first capping structure chemical element that is different than the first group IV chemical element covers the epitaxial structure on the first side of the semiconductor substrate. A second capping structure is arranged between the first capping structure and the epitaxial structure, where the second capping structure includes the group IV chemical element and the first capping structure chemical element.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: December 8, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Chun Liu, Chung-Yi Yu, Eugene Chen
  • Patent number: 10854450
    Abstract: The present disclosure describes patterned devices and methods for repairing substrate lattice damage in a patterned device. The patterned device includes a substrate, an alternating conductor and dielectric stack atop the substrate, a channel hole extending through the alternating conductor and dielectric stack to the substrate, and an epitaxial grown layer at a bottom of the channel hole and a top surface of the substrate. A part of the substrate in contact with the epitaxial grown layer has a dopant or doping concentration different from an adjacent part of the substrate. The method includes forming a channel hole in an insulating layer atop a substrate, forming an amorphous layer in a top side of the substrate below the channel hole, heating to crystallize the amorphous layer, and growing an epitaxial layer on the crystallized layer in the channel hole.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: December 1, 2020
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Xiao Jun Wang, Wei Zhou, Lin Kang Xu, Guan Nan Li
  • Patent number: 10825920
    Abstract: Energy-filtered cold electron devices use electron energy littering through discrete energy levels of quantum wells or quantum dots that are formed through band bending of tunneling barrier conduction band. These devices can obtain low effective electron temperatures of less than or equal to 45K at room temperature, steep electrical current turn-on/turn-off capabilities with a steepness of less than or equal to 10 mV/decade at room temperature, subthreshold swings of less than or equal to 10 mV/decade at room temperature, and/or supply voltages of less than or equal to 0.1 V.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: November 3, 2020
    Assignee: Board of Regents, The University of Texas System
    Inventors: Seong Jin Koh, Pradeep Bhadrachalam, Liang-Chieh Ma
  • Patent number: 10804203
    Abstract: The semiconductor device includes: a transistor having a gate electrode formed on a semiconductor substrate and first and second source/drain regions formed in portions of the semiconductor substrate on both sides of the gate electrode; a gate interconnect formed at a position opposite to the gate electrode with respect to the first source/drain region; and a first silicon-germanium layer formed on the first source/drain region to protrude above the top surface of the semiconductor substrate. The gate interconnect and the first source/drain region are connected via a local interconnect structure that includes the first silicon-germanium layer.
    Type: Grant
    Filed: August 17, 2017
    Date of Patent: October 13, 2020
    Assignee: Pannova Semic
    Inventors: Tsutomu Oosuka, Hisashi Ogawa, Yoshihiro Sato
  • Patent number: 10797137
    Abstract: A method for controlling Schottky barrier height in a semiconductor device includes forming an alloy layer including at least a first element and a second element on a first surface of a semiconductor substrate. The semiconductor substrate is a first element-based semiconductor substrate, and the first element and the second element are Group IV elements. A first thermal anneal of the alloy layer and the first element-based substrate is performed. The first thermal anneal causes the second element in the alloy layer to migrate towards a surface of the alloy layer. A Schottky contact layer is formed on the alloy layer after the first thermal anneal.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: October 6, 2020
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Hung-Hsiang Cheng, Samuel C. Pan
  • Patent number: 10749559
    Abstract: A receiver receives a wide band signal in a range comprising a front end to the receiver including a complementary metal-oxide-semiconductor (CMOS). The CMOS includes a dipole antenna that receives a received signal; a hybrid-based broadband isolation structure that receives the received signal and a local oscillator LO signal and passes through the LO signal to a sub-harmonic mixer. The sub-harmonic mixer mixes the received signal with the local oscillator signal to generate an intermediate frequency (IF) signal to the hybrid-based broadband isolation structure.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: August 18, 2020
    Assignee: Board of Regents, The University of Texas System
    Inventors: Qian Zhong, Kenneth K. O, Wooyeol Choi
  • Patent number: 10720496
    Abstract: FinFETs and methods of forming finFETs are described. According to some embodiments, a structure includes a channel region, first and second source/drain regions, a dielectric layer, and a gate electrode. The channel region includes semiconductor layers above a substrate. Each of the semiconductor layers is separated from neighboring ones of the semiconductor layers, and each of the semiconductor layers has first and second sidewalls. The first and second sidewalls are aligned along a first and second plane, respectively, extending perpendicularly to the substrate. The first and second source/drain regions are disposed on opposite sides of the channel region. The semiconductor layers extend from the first source/drain region to the second source/drain region. The dielectric layer contacts the first and second sidewalls of the semiconductor layers, and the dielectric layer extends into a region between the first plane and the second plane. The gate electrode is over the dielectric layer.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: July 21, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Yi Peng, Chih Chieh Yeh, Tsung-Lin Lee
  • Patent number: 10600786
    Abstract: Manufacture of a transistor device with at least one P type transistor with channel structure strained in uniaxial compression strain starting from a silicon layer strained in biaxial tension, by amorphization recrystallization then germanium condensation.
    Type: Grant
    Filed: March 7, 2017
    Date of Patent: March 24, 2020
    Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, STMICROELECTRONICS Inc
    Inventors: Sylvain Maitrejean, Emmanuel Augendre, Pierre Morin, Shay Reboh
  • Patent number: 10600870
    Abstract: A semiconductor structure is provided that includes a silicon germanium alloy fin having a second germanium content located on a first portion of a substrate. The structure further includes a laterally graded silicon germanium alloy material portion located on a second portion of the substrate. The laterally graded silicon germanium alloy material portion is spaced apart from the silicon germanium alloy fin and has end portions having the second germanium content and a middle portion located between the end portions that has a first germanium content that is less than the second germanium content.
    Type: Grant
    Filed: August 22, 2017
    Date of Patent: March 24, 2020
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek
  • Patent number: 10580867
    Abstract: A FINFET may include a semiconductor fin, spaced apart source and drain regions in the semiconductor fin with a channel region extending therebetween, and at least one dopant diffusion blocking superlattice dividing at least one of the source and drain regions into a lower region and an upper region with the upper region having a same conductivity and higher dopant concentration than the lower region. The dopant diffusion blocking superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The semiconductor device may further include a gate on the channel region.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: March 3, 2020
    Assignee: ATOMERA INCORPORATED
    Inventors: Hideki Takeuchi, Daniel Connelly, Marek Hytha, Richard Burton, Robert J. Mears
  • Patent number: 10580866
    Abstract: A semiconductor device may include a semiconductor layer, spaced apart source and drain regions in the semiconductor layer with a channel region extending therebetween, and at least one dopant diffusion blocking superlattice dividing at least one of the source and drain regions into a lower region and an upper region with the upper region having a same conductivity and higher dopant concentration than the lower region. The at least one dopant diffusion blocking superlattice comprising a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The semiconductor device may further include a gate on the channel region.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: March 3, 2020
    Assignee: ATOMERA INCORPORATED
    Inventors: Hideki Takeuchi, Daniel Connelly, Marek Hytha, Richard Burton, Robert J. Mears
  • Patent number: 10546858
    Abstract: Monolithic finFETs including a majority carrier channel in a first III-V compound semiconductor material disposed on a second III-V compound semiconductor. While a mask, such as a sacrificial gate stack, is covering the channel region, a source of an amphoteric dopant is deposited over exposed fin sidewalls and diffused into the first III-V compound semiconductor material. The amphoteric dopant preferentially activates as a donor within the first III-V material and an acceptor with the second III-V material, providing transistor tip doping with a p-n junction between the first and second III-V materials. A lateral spacer is deposited to cover the tip portion of the fin. Source/drain regions in regions of the fin not covered by the mask or spacer electrically couple to the channel through the tip region. The channel mask is replaced with a gate stack.
    Type: Grant
    Filed: June 27, 2015
    Date of Patent: January 28, 2020
    Assignee: Intel Corporation
    Inventors: Jack T. Kavalieros, Chandra S. Mohapatra, Anand S. Murthy, Willy Rachmady, Matthew V. Metz, Gilbert Dewey, Tahir Ghani, Harold W. Kennel
  • Patent number: 10546963
    Abstract: Methods and systems for germanium-on-silicon photodetectors without germanium layer contacts are disclosed and may include, in a semiconductor die having a photodetector, where the photodetector includes an n-type silicon layer, a germanium layer, a p-type silicon layer, and a metal contact on each of the n-type silicon layer and the p-type silicon layer: receiving an optical signal, absorbing the optical signal in the germanium layer, generating an electrical signal from the absorbed optical signal, and communicating the electrical signal out of the photodetector via the n-type silicon layer and the p-type silicon layer. The photodetector may include a horizontal or vertical junction double heterostructure where the germanium layer is above the n-type and p-type silicon layers. An intrinsically-doped silicon layer may be below the germanium layer between the n-type silicon layer and the p-type silicon layer. A top portion of the germanium layer may be p-doped.
    Type: Grant
    Filed: October 29, 2015
    Date of Patent: January 28, 2020
    Assignee: Luxtera, Inc.
    Inventors: Kam-Yan Hon, Gianlorenzo Masini, Subal Sahni
  • Patent number: 10541176
    Abstract: A method of forming vertical fin field effect transistors, including, forming a silicon-germanium cap layer on a substrate, forming at least four vertical fins and silicon-germanium caps from the silicon-germanium cap layer and the substrate, where at least two of the at least four vertical fins is in a first subset and at least two of the at least four vertical fins is in a second subset, forming a silicon-germanium doping layer on the plurality of vertical fins and silicon-germanium caps, removing the silicon-germanium doping layer from the at least two of the at least four vertical fins in the second subset, and removing the silicon-germanium cap from at least one of the at least two vertical fins in the first subset, and at least one of the at least two vertical fins in the second subset.
    Type: Grant
    Filed: April 6, 2018
    Date of Patent: January 21, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Zhenxing Bi, Kangguo Cheng, Juntao Li, Peng Xu
  • Patent number: 10529738
    Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. An exemplary method for fabricating an integrated circuit includes providing a substrate including a semiconductor layer over an insulator layer. The method includes selectively replacing portions of the semiconductor layer with insulator material to define an isolated semiconductor layer region. Further, the method includes selectively forming a relaxed layer on the isolated semiconductor layer region. Also, the method includes selectively forming a strained layer on the relaxed layer. The method forms a device over the strained layer.
    Type: Grant
    Filed: April 28, 2016
    Date of Patent: January 7, 2020
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Raj Verma Purakh, Shaoqiang Zhang, Rui Tze Toh
  • Patent number: 10529835
    Abstract: Energy-filtered cold electron devices use electron energy filtering through discrete energy levels of quantum wells or quantum dots that are formed through band bending of tunneling barrier conduction band. These devices can obtain low effective electron temperatures of less than or equal to 45K at room temperature, steep electrical current turn-on/turn-off capabilities with a steepness of less than or equal to 10 mV/decade at room temperature, subthreshold swings of less than or equal to 10 mV/decade at room temperature, and/or supply voltages of less than or equal to 0.1 V.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: January 7, 2020
    Inventors: Seong Jin Koh, Pradeep Bhadrachalam, Liang-Chieh Ma
  • Patent number: 10510871
    Abstract: Methods are disclosed for forming a multi-layer structure including highly controlled diffusion interfaces between alternating layers of different semiconductor materials. According to embodiments, during a deposition of semiconductor layers, the process is controlled to remain at low temperatures such that an inter-diffusion rate between the materials of the deposited layers is managed to provide diffusion interfaces with abrupt Si/SiGe interfaces. The highly controlled interfaces and first and second layers provide a multi-layer structure with improved etching selectivity. In an embodiment, a gate all-around (GAA) transistor is formed with horizontal nanowires (NWs) from the multi-layer structure with improved etching selectivity. In embodiments, horizontal NWs of a GAA transistor may be formed with substantially the same size diameters and silicon germanium (SiGe) NWs may be formed with “all-in-one” silicon (Si) caps.
    Type: Grant
    Filed: August 16, 2018
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shahaji B. More, Shih-Chieh Chang
  • Patent number: 10481090
    Abstract: Differential, plasmonic, non-dispersive infrared gas sensors are provided. In one aspect, a gas sensor includes: a plasmonic resonance detector including a differential plasmon resonator array that is resonant at different wavelengths of light; and a light source incident on the plasmonic resonance detector. The differential plasmon resonator array can include: at least one first set of plasmonic resonators interwoven with at least one second set of plasmonic resonators, wherein the at least one first set of plasmonic resonators is configured to be resonant with light at a first wavelength, and wherein the at least one second set of plasmonic resonators is configured to be resonant with light at a second wavelength. A method for analyzing a target gas and a method for forming a plasmonic resonance detector are also provided.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: November 19, 2019
    Assignee: International Business Machines Corporation
    Inventors: Abram L. Falk, Damon B. Farmer, Shu-Jen Han
  • Patent number: 10461203
    Abstract: A semiconductor device comprises a plurality of quantum structures comprising predominantly germanium. The plurality of quantum structures are formed on a first semiconductor layer structure. The quantum structures of the plurality of quantum structures have a lateral dimension of less than 15 nm and an area density of at least 8×1011 quantum structures per cm2. The plurality of quantum structures are configured to emit light with a light emission maximum at a wavelength of between 2 ?m and 10 ?m or to absorb light with a light absorption maximum at a wavelength of between 2 ?m and 10 ?m.
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: October 29, 2019
    Assignee: Infineon Technologie AG
    Inventors: Stefan Clara, Thomas Grille, Ursula Hedenig, Peter Irsigler, Bernhard Jakoby, Ventsislav M. Lavchiev, Thomas Ostermann, Thomas Popp
  • Patent number: 10453960
    Abstract: Field-effect transistor, the source and drain regions whereof are formed from a crystalline structure comprising: a first layer comprising two main faces parallel to one another and two lateral faces parallel to one another, the main faces being perpendicular to the lateral faces, a second layer overlapping the first layer, the second layer comprising a first main face and a second main face parallel to one another and two lateral faces, the first main face being in contact with the first layer, the lateral faces forming an angle ? in the range 50° to 59°, and preferably a 53° angle, with the first main face.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: October 22, 2019
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Vincent Mazzocchi, Laurent Grenouillet
  • Patent number: 10453945
    Abstract: A semiconductor device may include at least one double-barrier resonant tunneling diode (DBRTD). The at least one DBRTD may include a first doped semiconductor layer and a first barrier layer on the first doped semiconductor layer and including a superlattice. The superlattice may include stacked groups of layers, each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The at least one DBRTD may further include an intrinsic semiconductor layer on the first barrier layer, a second barrier layer on the intrinsic semiconductor layer, and a second doped semiconductor layer on the second superlattice layer.
    Type: Grant
    Filed: August 7, 2017
    Date of Patent: October 22, 2019
    Assignee: ATOMERA INCORPORATED
    Inventors: Robert J. Mears, Hideki Takeuchi, Marek Hytha
  • Patent number: 10446392
    Abstract: A method of forming a 3D NAND structure having self-aligned nanodots includes depositing alternating layers of an oxide and a nitride on a substrate; at least partially recessing the nitride layers; and forming SiGe nanodots on the nitride layers. A method of forming a 3D NAND structure having self-aligned nanodots includes depositing alternating layers of an oxide and a nitride on a substrate; at least partially recessing the nitride layers; and forming SiGe nanodots on the nitride layers by a process including maintaining a temperature of the substrate below about 560° C.; flowing a silicon epitaxy precursor into the chamber; forming a silicon epitaxial layer on the substrate at the nitride layers; flowing germanium gas into the chamber with the silicon epitaxy precursor; and forming a silicon germanium epitaxial layer on the substrate at the nitride layers.
    Type: Grant
    Filed: January 26, 2018
    Date of Patent: October 15, 2019
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Sungwon Jun, Saurabh Chopra, Thomas Jongwan Kwon, Er-Xuan Ping
  • Patent number: 10396165
    Abstract: A strain relaxed silicon germanium layer that has a low defect density is formed on a surface of a silicon substrate without causing wafer bowing. The strain relaxed silicon germanium layer is formed using multiple epitaxial growing, bonding and transferring steps. In the present application, a thick silicon germanium layer having a low defect density is grown on a transferred portion of a topmost silicon germanium sub-layer of an initial strain relaxed silicon germanium graded buffer layer and then bonded to a silicon substrate. A portion of the thick silicon germanium layer is then transferred to the silicon substrate. Additional steps of growing a thick silicon germanium layer having a low defect density, bonding and layer transfer may be performed as necessary.
    Type: Grant
    Filed: February 22, 2018
    Date of Patent: August 27, 2019
    Assignee: International Business Machines Corporation
    Inventors: Praneet Adusumilli, Keith E. Fogel, Alexander Reznicek, Oscar van der Straten
  • Patent number: 10373752
    Abstract: Disclosed herein are magnetic materials comprising rare earth nitrides and, more particularly, magnetic materials comprising multilayer-structured materials comprising one relatively soft and one relatively hard magnetic layer. The magnetic materials comprise a first ferromagnetic layer, a second ferromagnetic layer, and a blocking layer between and in contact with each of the first 5 and second ferromagnetic layers. The first and second ferromagnetic layers have different coercive fields. The first ferromagnetic layer comprises a first rare earth nitride material and the second ferromagnetic layer comprises a second rare earth nitride material. Also disclosed are methods for preparing the materials. The materials are useful in the fabrication of devices, such as GMR magnetic field sensors, MRAM devices, TMR magnetic field sensors, and magnetic 10 tunnel junctions.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: August 6, 2019
    Inventors: Franck Natali, Benjamin John Ruck, Harry Joseph Trodahl, Eva-maria Johanna Anton, James Francis McNulty, Simon Edward Granville
  • Patent number: 10355043
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to integrated vertical transistors and light emitting diodes and methods of manufacture. The structure includes a vertically oriented stack of material having a light emitting diode (LED) integrated with a source region and a drain region of a vertically oriented active device.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: July 16, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ajey P. Jacob, Deepak K. Nayak, Srinivasa R. Banna
  • Patent number: 10347764
    Abstract: A method includes providing a substrate having a gate structure over a first side of the substrate, forming a recess adjacent to the gate structure, and forming in the recess a first semiconductor layer having a dopant, the first semiconductor layer being non-conformal, the first semiconductor layer lining the recess and extending from a bottom of the recess to a top of the recess. The method further includes forming a second semiconductor layer having the dopant in the recess and over the first semiconductor layer, a second concentration of the dopant in the second semiconductor layer being higher than a first concentration of the dopant in the first semiconductor layer.
    Type: Grant
    Filed: October 5, 2017
    Date of Patent: July 9, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Yu Ma, Zheng-Yang Pan, Shahaji B. More, Shih-Chieh Chang, Cheng-Han Lee
  • Patent number: 10332981
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a first gate structure on a substrate; performing a first etching process to form a recess adjacent to the first gate structure; performing an ion implantation process to form an amorphous layer directly under the recess; performing a second etching process to remove the amorphous layer; and forming an epitaxial layer in the recess.
    Type: Grant
    Filed: April 2, 2018
    Date of Patent: June 25, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yu-Ying Lin, Yi-Liang Ye, Sung-Yuan Tsai, Chun-Wei Yu, Yu-Ren Wang, Zhen Wu, Tai-Yen Lin
  • Patent number: 10332979
    Abstract: Semiconductor devices including semiconductor junctions and semiconductor field effect transistors that exploit the straining of semiconductor materials to improve device performance are provided. Also described are methods for making semiconductor structures. Dislocation defect-free epitaxial grown structures that are embedded into a semiconductor base are provided. The epitaxial structures can extend beyond the surface of the semiconductor base and terminate at a faceted structure. The epitaxial structures are formed using a multilayer growth process that provides for continuous transitions between adjacent layers.
    Type: Grant
    Filed: October 8, 2015
    Date of Patent: June 25, 2019
    Assignee: SHANGHAI HUALI MICROELECTRONICS CORPORATION
    Inventors: Runling Li, Haifeng Zhou
  • Patent number: 10319736
    Abstract: The present disclosure relates to a semiconductor device including a stress control insulating layer or a stress control pattern to control a stress applied to an interlayer insulating layer or a stacked body in a desirable direction.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: June 11, 2019
    Assignee: SK hynix Inc.
    Inventors: Jeong Seob Oh, Dong Hyoub Kim
  • Patent number: 10297670
    Abstract: Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. The techniques can be implemented, for example, using a standard contact stack such as a series of metals on, for example, silicon or silicon germanium (SiGe) source/drain regions. In accordance with one example such embodiment, an intermediate boron doped germanium layer is provided between the source/drain and contact metals to significantly reduce contact resistance. Numerous transistor configurations and suitable fabrication processes will be apparent in light of this disclosure, including both planar and non-planar transistor structures (e.g., FinFETs), as well as strained and unstrained channel structures. Graded buffering can be used to reduce misfit dislocation. The techniques are particularly well-suited for implementing p-type devices, but can be used for n-type devices if so desired.
    Type: Grant
    Filed: October 31, 2016
    Date of Patent: May 21, 2019
    Assignee: INTEL CORPORATION
    Inventors: Glenn A. Glass, Anand S. Murthy, Tahir Ghani
  • Patent number: 10276695
    Abstract: A method for manufacturing a semiconductor device includes forming a stacked configuration of first and second semiconductor layers on a semiconductor substrate, wherein the stacked configuration comprises a repeating arrangement of a second semiconductor layer stacked on a first semiconductor layer, forming a plurality of dummy gates spaced apart from each other on the stacked configuration, wherein the plurality of dummy gates cover a portion of the stacked configuration in a channel region, performing an implantation of a semiconductor material on exposed portions of the stacked configuration in a source/drain region, wherein the implantation increases a concentration of the semiconductor material in the exposed portions of the stacked configuration, and selectively removing first semiconductor layers having an increased concentration of the semiconductor material from the source/drain region, wherein the removed first semiconductor layers correspond in position to the first semiconductor layers in the cha
    Type: Grant
    Filed: July 20, 2017
    Date of Patent: April 30, 2019
    Assignee: International Business Machines Corporation
    Inventors: Robin Hsin-Kuo Chao, Michael A. Guillorn, Chi-Chun Liu, Shogo Mochizuki, Chun W. Yeung
  • Patent number: 10233387
    Abstract: Described is a quantum dot film article comprising a quantum dot of a cured thiol-alkene-epoxy matrix. The matrix formulations resist ingress from water and/or oxygen, while also providing acceptable color stability upon aging.
    Type: Grant
    Filed: April 7, 2016
    Date of Patent: March 19, 2019
    Assignee: 3M INNOVATIVE PROPERTIES COMPANY
    Inventors: Zai-Ming Qiu, Joseph M. Pieper
  • Patent number: 10192739
    Abstract: A layered semiconductor substrate has a monocrystalline first layer based on silicon, having a first thickness and a first lattice constant a1 determined by a first dopant element and a first dopant concentration, and in direct contact therewith, a monocrystalline second layer based on silicon, having a second thickness and a second lattice constant a2, determined by a second dopant element and a second dopant concentration, and a monocrystalline third layer comprising a group III nitride, the second layer located between the first layer and the third layer, wherein a2>a1, wherein the crystal lattice of the first layer and the second layer are lattice-matched, and wherein the bow of the layered semiconductor substrate is in the range from ?50 ?m to 50 ?m.
    Type: Grant
    Filed: May 23, 2012
    Date of Patent: January 29, 2019
    Assignee: SILTRONIC AG
    Inventors: Peter Storck, Guenter Sachs, Ute Rothammer, Sarad Bahadur Thapa, Helmut Schwenk, Peter Dreier, Frank Muemmler, Rudolf Mayrhuber
  • Patent number: 10177236
    Abstract: A method of manufacturing a semiconductor device includes: setting a plurality of main semiconductor wafers and a plurality of sub semiconductor wafers in a load lock chamber of an electrode forming equipment; repeating a wafer-transfer and electrode-formation process of transferring at least one of the main semiconductor wafers from the load lock chamber to the film formation chamber in a state where the load lock chamber and the film formation chamber are decompressed and then forming a surface electrode on a surface of the at least one main semiconductor wafer transferred in the film formation chamber; removing the main semiconductor wafers on which the surface electrodes have been formed and the sub semiconductor wafers from the electrode forming equipment without forming an electrode on the sub semiconductor wafers by the electrode forming equipment; and making the surface electrodes Schottky-contact the main semiconductor wafers.
    Type: Grant
    Filed: October 16, 2017
    Date of Patent: January 8, 2019
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Teruaki Kumazawa, Narumasa Soejima, Yuichi Takeuchi
  • Patent number: 10170636
    Abstract: A method for fabricating a semiconductor device comprises forming a sacrificial layer of a first semiconductor material on a substrate, a layer of a second semiconductor material on the sacrificial layer, and a layer of a third semiconductor material on the layer of the second semiconductor material. Portions of the layer of the deposited material are removed to form a first nanowire arranged on the sacrificial fin and a second nanowire arranged on the first nanowire. An oxidizing process is performed that forms a first layer of oxide material on exposed portions of the second nanowire and a second layer of oxide material on exposed portions of the sacrificial fin, the first layer of oxide material having a first thickness and the second layer of oxide material having a second thickness, where the first thickness is less than the second thickness.
    Type: Grant
    Filed: May 24, 2017
    Date of Patent: January 1, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Josephine B. Chang, Michael A. Guillorn, Isaac Lauer, Xin Miao
  • Patent number: 10164013
    Abstract: Formation methods of a semiconductor device structure are provided. The method includes forming a gate stack over a semiconductor substrate and forming a source/drain structure adjacent to the gate stack. The method also includes forming a cap element over the source/drain structure. The cap element has a top surface and a side surface, and a width ratio of the top surface to the side surface of the cap element is in a range from about 0.125 to about 1.
    Type: Grant
    Filed: August 29, 2016
    Date of Patent: December 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shing-Huang Wu, Jian-Shian Chen