Strained Layer Superlattice Patents (Class 257/18)
  • Patent number: 11070029
    Abstract: Embodiments are directed to the fabrication of an electro-optical device. The device comprises the forming of an active region with a stack of III-V semiconductor gain materials stacked along a stacking direction z. The active region may be formed as a slab having several lateral surface portions, each extending parallel to the stacking direction z. The device further comprises selectively re-growing two paired elements, which include: a pair of doped layers of III-V semiconductor materials (an n-doped layer and a p-doped layer); and a pair of lateral waveguide cores. The two paired elements may be laterally arranged, two-by-two, on opposite sides of the slab. The elements distinctly adjoin respective ones of the lateral surface portions of the slab, so as for these elements to be separated from each other by the slab. The disclosure may be further directed to related silicon photonics devices.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: July 20, 2021
    Assignee: International Business Machines Corporation
    Inventors: Charles Caer, Lukas Czornomaz, Stefan Abel, Bert Jan Offrein
  • Patent number: 10937647
    Abstract: A semiconductor crystal substrate includes a crystal substrate that is formed of a material including GaSb or InAs, a first buffer layer that is formed on the crystal substrate and formed of a material including GaSb, the first buffer layer having n-type conductivity, and a second buffer layer that is formed on the first buffer layer and formed of a material including GaSb, the second buffer layer having p-type conductivity.
    Type: Grant
    Filed: February 11, 2019
    Date of Patent: March 2, 2021
    Assignee: FUJITSU LIMITED
    Inventors: Shigekazu Okumura, Shuichi Tomabechi, Ryo Suzuki
  • Patent number: 10937906
    Abstract: A semiconductor Fin FET device includes a fin structure disposed over a substrate. The fin structure includes a channel layer. The Fin FET device also includes a gate structure including a gate electrode layer and a gate dielectric layer, covering a portion of the fin structure. Side-wall insulating layers are disposed over both main sides of the gate electrode layer. The Fin FET device includes a source and a drain, each including a stressor layer disposed in a recess formed by removing the fin structure not covered by the gate structure. The stressor layer includes a first to a third stressor layer formed in this order. In the source, an interface between the first stressor layer and the channel layer is located under one of the side-wall insulating layers closer to the source or the gate electrode.
    Type: Grant
    Filed: May 8, 2018
    Date of Patent: March 2, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun Hsiung Tsai, Kei-Wei Chen
  • Patent number: 10884185
    Abstract: A semiconductor device may include a substrate having waveguides thereon, and a superlattice overlying the substrate and waveguides. The superlattice may include stacked groups of layers, with each group of layers comprising a stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The semiconductor device may further include an active device layer on the superlattice including at least one active semiconductor device.
    Type: Grant
    Filed: April 10, 2019
    Date of Patent: January 5, 2021
    Assignee: ATOMERA INCORPORATED
    Inventor: Robert John Stephenson
  • Patent number: 10833079
    Abstract: A semiconductor structure includes a substrate, a vertical fin disposed over a top surface of the substrate, a first vertical transport field-effect transistor (VTFET) disposed over the top surface of the substrate surrounding a first portion of the vertical fin, an isolation layer disposed over the first VTFET surrounding a second portion of the vertical fin, and a second VTFET disposed over a top surface of the isolation layer surrounding a third portion of the vertical fin. The first portion of the vertical fin includes a first semiconductor layer with a first crystalline orientation providing a first vertical transport channel for the first VTFET, the second portion of the vertical fin includes an insulator, and the third portion of the vertical fin includes a second semiconductor layer with a second crystalline orientation providing a second vertical transport channel for the second VTFET.
    Type: Grant
    Filed: January 2, 2019
    Date of Patent: November 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Tenko Yamashita, Chen Zhang, Kangguo Cheng, Heng Wu
  • Patent number: 10809547
    Abstract: A silicon based electro-optically active device and method of producing the same, the device comprising: a silicon-on-insulator (SOI) waveguide; an electro-optically active stack within a cavity of the SOI waveguide; and a channel between the electro-optically active stack and the SOI waveguide; wherein the channel is filled with a filling material with a refractive index greater than that of a material forming a sidewall of the cavity to form a bridge-waveguide in the channel between the SOI waveguide and the electro-optically active stack.
    Type: Grant
    Filed: November 23, 2017
    Date of Patent: October 20, 2020
    Assignee: ROCKLEY PHOTONICS LIMITED
    Inventors: Guomin Yu, Yi Zhang, Aaron Zilkie
  • Patent number: 10734787
    Abstract: Embodiments of the disclosure are directed to a lateral current injection electro-optical device. The device comprises an active region with a stack of III-V semiconductor gain materials stacked along a stacking direction z. The active region may be formed as a slab having several lateral surface portions, each extending parallel to the stacking direction z. The device further comprises two paired elements, which include: a pair of doped layers of III-V semiconductor materials (an n-doped layer and a p-doped layer); and a pair of lateral waveguide cores. The two paired elements may be laterally arranged, two-by-two, on opposite sides of the slab. The elements distinctly adjoin respective ones of the lateral surface portions of the slab, so as for these elements to be separated from each other by the slab. The disclosure may be further directed to related silicon photonics devices and fabrication methods.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: August 4, 2020
    Assignee: International Business Machines Corporation
    Inventors: Charles Caër, Lukas Czornomaz, Stefan Abel, Bert Jan Offrein
  • Patent number: 10679901
    Abstract: Integrated chips and methods of forming the same include etching a first stack of layers in a first region and etching a second stack of layers in a second region. The first stack of layers includes a first semiconductor layer having a first thickness over a first sacrificial layer having a second thickness. Etching the first stack of layers removes the first sacrificial layer from the first stack of layers and creates a first gap. The second stack of layers includes a second semiconductor layer having a third thickness over a second sacrificial layer having a fourth thickness. Etching the second stack of layers removes the second sacrificial layer from the second stack of layers and to create a second gap. A dielectric material fills the first gap and the second gap.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: June 9, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Huimei Zhou, Shogo Mochizuki, Gen Tsutsui, Ruqiang Bao
  • Patent number: 10679995
    Abstract: A semiconductor device including a cap layer and a method for forming the same are disclosed. In an embodiment, a method includes epitaxially growing a first semiconductor layer over an N-well; etching the first semiconductor layer to form a first recess; epitaxially growing a second semiconductor layer filling the first recess; etching the second semiconductor layer, the first semiconductor layer, and the N-well to form a first fin; forming a shallow trench isolation region adjacent the first fin; and forming a cap layer over the first fin, the cap layer contacting the second semiconductor layer, forming the cap layer including performing a pre-clean process to remove a native oxide from exposed surfaces of the second semiconductor layer; performing a sublimation process to produce a first precursor; and performing a deposition process wherein material from the first precursor is deposited on the second semiconductor layer to form the cap layer.
    Type: Grant
    Filed: February 14, 2019
    Date of Patent: June 9, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Chieh Wang, Yueh-Ching Pai, Huai-Tei Yang
  • Patent number: 10651305
    Abstract: A compound semiconductor device includes a substrate, a compound semiconductor layer formed over the substrate, a channel layer formed over the compound semiconductor layer, an electron supply layer formed over the channel layer, and a source electrode, a drain electrode, and a gate electrode that are formed apart from each other over the electron supply layer. A quantum well structure is formed by the compound semiconductor layer, the channel layer, and the electron supply layer.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: May 12, 2020
    Assignee: FUJITSU LIMITED
    Inventors: Junji Kotani, Norikazu Nakamura, Hisao Shigematsu
  • Patent number: 10615267
    Abstract: A method for forming a semiconductor device comprises forming a first buffer layer with a first melting point on a substrate. A second buffer layer is formed on the first buffer layer. The second buffer layer has a second melting point that is greater than the first melting point. Annealing process is performed that increases a temperature of the first buffer layer such that the first buffer layer partially liquefies and causes a strain in the second buffer layer to be substantially reduced.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: April 7, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Xin Miao, Wenyu Xu, Chen Zhang
  • Patent number: 10566191
    Abstract: A semiconductor device may include a substrate and a superlattice on the substrate including a plurality of stacked groups of layers. Each group of layers may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. Furthermore, an upper portion of at least one of the base semiconductor portions adjacent the respective at least one non-semiconductor monolayer may have a defect density less than or equal to 1×105/cm2.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: February 18, 2020
    Assignee: ATOMERA INCORPORATED
    Inventors: Keith Doran Weeks, Nyles Wynn Cody, Marek Hytha, Robert J. Mears, Robert John Stephenson
  • Patent number: 10541133
    Abstract: Disclosed is a preparation method for a GaAs thin film grown on an Si substrate, said method comprising the following steps: (1) Si (111) substrate cleaning; (2) Si (111) substrate preprocessing; (3) Si (111) substrate oxide film removal; (4) first InxGa1-xAs buffer layer growth; (5) first InxGa1-xAs buffer layer in situ annealing; (6) GaAs buffer layer growth; (7) GaAs buffer layer in situ annealing; (8) second InxGa1-xAs buffer layer growth; (9) second InxGa1-xAs buffer layer in situ annealing; (10) GaAs epitaxial thin film growth. Also disclosed is a GaAs thin film grown on an Si substrate. The GaAs thin film obtained by the present invention has a good crystal quality, an even surface, and a positive promotional significance with regard to the preparation of semiconductor devices, particularly in the field of solar cells.
    Type: Grant
    Filed: August 18, 2016
    Date of Patent: January 21, 2020
    Assignee: SOUTH CHINA UNIVERSITY OF TECHNOLOGY
    Inventors: Guoqiang Li, Fangliang Gao, Lei Wen, Shuguang Zhang, Jingling Li
  • Patent number: 10541177
    Abstract: A method for forming CMOS devices includes masking a first portion of a tensile-strained silicon layer of a SOI substrate, doping a second portion of the layer outside the first portion and growing an undoped silicon layer on the doped portion and the first portion. The undoped silicon layer becomes tensile-strained. Strain in the undoped silicon layer over the doped portion is relaxed by converting the doped portion to a porous silicon to form a relaxed silicon layer. The porous silicon is converted to an oxide. A SiGe layer is grown and oxidized to convert the relaxed silicon layer to a compressed SiGe layer. Fins are etched in the first portion from the tensile-strained silicon layer and the undoped silicon layer and in the second portion from the compressed SiGe layer.
    Type: Grant
    Filed: December 10, 2018
    Date of Patent: January 21, 2020
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Ramachandra Divakaruni, Jeehwan Kim, Juntao Li, Devendra K. Sadana
  • Patent number: 10529616
    Abstract: A method is provided for preparing semiconductor structure, e.g., a semiconductor on insulator structure, comprising a device layer having a smooth surface. The method provided involves smoothing a semiconductor substrate surface by making use of stress enhanced surface diffusion at elevated temperatures. The purpose of this method is to reach atomic scale surface smoothness (for example, smoothness in the range of between 1.0 and 1.5 angstroms as measured according to root mean square over a 30 um×30 um AFM measurement), which is required in advanced (sub 28 nm) CMOS device fabrication.
    Type: Grant
    Filed: November 15, 2016
    Date of Patent: January 7, 2020
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Gang Wang, Charles R. Lottes, Sasha Kweskin
  • Patent number: 10497718
    Abstract: Provided are a silicon-on-insulator structure having bipolar stress and a manufacturing method therefor. The manufacturing method comprises providing a composite substrate, wherein the composite substrate has a silicon substrate layer, a buried oxide layer and a silicon-on-insulator layer sequentially from bottom to top, epitaxially growing a silicon germanium layer on an upper surface of the silicon-on-insulator layer; depositing a hard mask layer to cover a portion of the silicon germanium layer corresponding to an N-type MOS transistor region; depositing a surface oxide layer to cover the silicon germanium layer and the hard mask layer; performing a high temperature annealing treatment so that a portion of the silicon-on-insulator layer corresponding to a P-type MOS transistor region is converted into a silicon-germanium-on-insulator layer, and the portion corresponding to the N-type MOS transistor region is converted into a tensile stress silicon-on-insulator layer.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: December 3, 2019
    Inventors: Yanfei Ma, Changfeng Wang, Duanquan Liao
  • Patent number: 10490697
    Abstract: A solution for fabricating a semiconductor structure is provided. The semiconductor structure includes a plurality of semiconductor layers grown over a substrate using a set of epitaxial growth periods. During each epitaxial growth period, a first semiconductor layer having one of: a tensile stress or a compressive stress is grown followed by growth of a second semiconductor layer having the other of: the tensile stress or the compressive stress directly on the first semiconductor layer.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: November 26, 2019
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Rakesh Jain, Wenhong Sun, Jinwei Yang, Maxim S. Shatalov, Alexander Dobrinsky, Remigijus Gaska, Michael Shur, Brandon Robinson
  • Patent number: 10407716
    Abstract: A sensor comprising a semiconductor layer having a two dimensional electron gas (2DEG) and an oxide layer in electronic contact with the semiconductor layer is provided. A method of detecting an analyte molecule using such sensor is also provided.
    Type: Grant
    Filed: March 13, 2015
    Date of Patent: September 10, 2019
    Assignee: Duke University
    Inventors: April S. Brown, Maria Losurdo, Chris Dwyer
  • Patent number: 10340661
    Abstract: Embodiments of the disclosure are directed to a lateral current injection electro-optical device. The device comprises an active region with a stack of III-V semiconductor gain materials stacked along a stacking direction z. The active region may be formed as a slab having several lateral surface portions, each extending parallel to the stacking direction z. The device further comprises two paired elements, which include: a pair of doped layers of III-V semiconductor materials (an n-doped layer and a p-doped layer); and a pair of lateral waveguide cores. The two paired elements may be laterally arranged, two-by-two, on opposite sides of the slab. The elements distinctly adjoin respective ones of the lateral surface portions of the slab, so as for these elements to be separated from each other by the slab. The disclosure may be further directed to related silicon photonics devices and fabrication methods.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: July 2, 2019
    Assignee: International Business Machines Corporation
    Inventors: Charles Caër, Lukas Czornomaz, Stefan Abel, Bert Jan Offrein
  • Patent number: 10276454
    Abstract: A semiconductor device, a semiconductor substrate and a method of forming the same are disclosed. The semiconductor substrate includes a first silicon-containing layer, a single crystalline III-V compound semiconductor layer and an amorphous III-V compound semiconductor layer. The first silicon-containing layer has a first region and a second region. The single crystalline III-V compound semiconductor layer is disposed on the first silicon-containing layer in the first region. The amorphous III-V compound semiconductor layer is disposed on the first silicon-containing layer in the second region.
    Type: Grant
    Filed: December 7, 2017
    Date of Patent: April 30, 2019
    Assignee: Nuvoton Technology Corporation
    Inventors: Fang-Chang Hsueh, Heng-Kuang Lin
  • Patent number: 10269945
    Abstract: A power transistor device including a substrate structure, a first conductive layer, a second conductive layer, and a third conductive layer is provided. The substrate structure has a base portion and fin portions. The fin portions protrude from a surface of the base portion. The first conductive layer is disposed across the fin portions and has a first side and a second side opposite to each other. The second conductive layer is disposed across the fin portions and is located at the first side of the first conductive layer. The third conductive layer is disposed across the fin portions and is located at the second side of the first conductive layer. The first conductive layer, the second conductive layer, the third conductive layer, and the fin portions are insulated from each other. An extending direction of the first, second, and third conductive layers intersects a length direction of the fin portions.
    Type: Grant
    Filed: January 18, 2018
    Date of Patent: April 23, 2019
    Assignee: UBIQ Semiconductor Corp.
    Inventor: Chin-Fu Chen
  • Patent number: 10234422
    Abstract: Methods of characterizing ion-exchanged chemically strengthened glass containing lithium are disclosed. The methods allow for performing quality control of the stress profile in chemically strengthened Li-containing glasses having a surface stress spike produced in a potassium-containing salt, especially in a salt having both potassium and sodium. The method allows the measurement of the surface compression and the depth of the spike, and its contribution to the center tension, as well as the compression at the bottom of the spike, and the total center tension and calculation of the stress at the knee where the spike and the deep region of the stress profile intersect. The measurements are for a commercially important profile that is near-parabolic in shape in most of the interior of the substrate apart from the spike.
    Type: Grant
    Filed: February 19, 2018
    Date of Patent: March 19, 2019
    Assignee: CORNING INCORPORATED
    Inventors: Ryan Claude Andrews, Rostislav Vatchev Roussev, Vitor Marino Schneider
  • Patent number: 10211048
    Abstract: A solution for fabricating a semiconductor structure is provided. The semiconductor structure includes a plurality of semiconductor layers grown over a substrate using a set of epitaxial growth periods. During each epitaxial growth period, a first semiconductor layer having one of: a tensile stress or a compressive stress is grown followed by growth of a second semiconductor layer having the other of: the tensile stress or the compressive stress directly on the first semiconductor layer. One or more of a set of growth conditions, a thickness of one or both of the layers, and/or a lattice mismatch between the layers can be configured to create a target level of compressive and/or shear stress within a minimum percentage of the interface between the layers.
    Type: Grant
    Filed: February 1, 2013
    Date of Patent: February 19, 2019
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Wenhong Sun, Rakesh Jain, Jinwei Yang, Maxim S. Shatalov, Alexander Dobrinsky, Remigijus Gaska, Michael Shur
  • Patent number: 10204836
    Abstract: A method for forming CMOS devices includes masking a first portion of a tensile-strained silicon layer of a SOI substrate, doping a second portion of the layer outside the first portion and growing an undoped silicon layer on the doped portion and the first portion. The undoped silicon layer becomes tensile-strained. Strain in the undoped silicon layer over the doped portion is relaxed by converting the doped portion to a porous silicon to form a relaxed silicon layer. The porous silicon is converted to an oxide. A SiGe layer is grown and oxidized to convert the relaxed silicon layer to a compressed SiGe layer. Fins are etched in the first portion from the tensile-strained silicon layer and the undoped silicon layer and in the second portion from the compressed SiGe layer.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: February 12, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Ramachandra Divakaruni, Jeehwan Kim, Juntao Li, Devendra K. Sadana
  • Patent number: 10199532
    Abstract: A light-emitting diode (LED) includes a first type semiconductor layer, a second type semiconductor layer, and an active layer. The first type semiconductor layer includes a low resistance portion and a high resistance portion. The low resistance portion is separated from at least one edge of the first type semiconductor layer by the high resistance portion, and the resistivity of the first type semiconductor layer is increased from the low resistance portion toward the high resistance portion. The active layer is disposed between the first type semiconductor layer and the second type semiconductor layer. The active layer has a first region and a second region, in which the first region has a threading dislocation density greater than that of the second region, and a vertical projection of the low resistance portion on the active layer at least partially overlaps with the second region.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: February 5, 2019
    Assignee: MIKRO MESA TECHNOLOGY CO., LTD.
    Inventors: Li-Yi Chen, Hsin-Wei Lee
  • Patent number: 10199485
    Abstract: A semiconductor device includes a substrate including a first semiconductor material, a gate structure formed on the substrate, and a source stressor and a drain stressor formed in the substrate respectively in a recess at two sides of the gate structure. The source stressor and the drain stressor respectively include at least a first quantum wire and at least a second quantum wire formed on the first quantum wire. The first quantum wire includes the first semiconductor material and a second semiconductor material, and a lattice constant of the second semiconductor material is larger than a lattice constant of the first semiconductor material. And the second quantum wire includes the second semiconductor material.
    Type: Grant
    Filed: January 18, 2017
    Date of Patent: February 5, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yu-Ying Lin, Chueh-Yang Liu, Yu-Ren Wang
  • Patent number: 10158044
    Abstract: A solution for fabricating a semiconductor structure is provided. The semiconductor structure includes a plurality of semiconductor layers grown over a substrate using a set of epitaxial growth periods. During each epitaxial growth period, a first semiconductor layer having one of: a tensile stress or a compressive stress is grown followed by growth of a second semiconductor layer having the other of: the tensile stress or the compressive stress directly on the first semiconductor layer.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: December 18, 2018
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Rakesh Jain, Wenhong Sun, Jinwei Yang, Maxim S. Shatalov, Alexander Dobrinsky, Remigijus Gaska, Michael Shur
  • Patent number: 10121656
    Abstract: Disclosed is a wafer or a material stack for semiconductor-based optoelectronic or electronic devices that minimizes or reduces misfit dislocation, as well as a method of manufacturing such wafer of material stack. A material stack according to the disclosed technology includes a substrate; a basis buffer layer of a first material disposed above the substrate; and a plurality of composite buffer layers disposed above the basis buffer layer sequentially along a growth direction. The growth direction is from the substrate to a last composite buffer layer of the plurality of composite buffer layers. Each composite buffer layer except the last composite buffer layer includes a first buffer sublayer of the first material, and a second buffer sublayer of a second material disposed above the first buffer sublayer. The thicknesses of the first buffer sublayers of the composite buffer layers decrease along the growth direction.
    Type: Grant
    Filed: February 14, 2017
    Date of Patent: November 6, 2018
    Assignee: Xiamen Changelight Co., Ltd.
    Inventors: Kaixuan Chen, Wei Jiang, Zhiwei Lin, Xiangjing Zhuo, Tianzu Fang, Yang Wang, Jichu Tong
  • Patent number: 10109709
    Abstract: A method of forming a semiconductor structure includes forming a dummy gate above a semiconductor substrate. The dummy gate defines a source-drain region adjacent to the dummy gate and a channel region below the dummy gate. A silicon-germanium layer is epitaxially grown above the source-drain region with a target concentration of germanium atoms. The semiconductor structure is annealed to diffuse the germanium atoms from the silicon-germanium layer into the channel region to form a silicon-germanium channel region.
    Type: Grant
    Filed: August 19, 2015
    Date of Patent: October 23, 2018
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Ali Khakifirooz, Alexander Reznicek, Ghavam G. Shahidi
  • Patent number: 10008575
    Abstract: A semiconductor device includes at least a first wire pattern, a gate electrode, a semiconductor pattern, a gate insulating layer, and a first spacer. The first wire pattern is on a substrate and isolated from the substrate. The gate electrode surrounds and intersects the first wire pattern. The semiconductor pattern is on both sides of the first wire pattern, and the semiconductor pattern includes a portion which overlaps the first wire pattern. The gate insulating layer is disposed between the gate electrode and the first wire pattern, and the gate insulating layer surrounds the first wire pattern. The first spacer is between the first wire pattern and the substrate, and the first spacer is between the gate insulating layer and the semiconductor pattern.
    Type: Grant
    Filed: October 20, 2016
    Date of Patent: June 26, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong Chan Suh, Yong Suk Tak, Gi Gwan Park, Mi Seon Park, Moon Seung Yang, Seung Hun Lee, Poren Tang
  • Patent number: 9953877
    Abstract: A method of forming a semiconductor device includes: providing a first substrate, forming at least one transistor on a first surface of the first substrate; forming a first dielectric cap layer covering the first surface of the first substrate; forming a first interconnect structure on the first dielectric cap layer; providing a carrier substrate; bonding the carrier substrate to the first substrate through the first dielectric cap layer; and from a second surface of the first substrate opposite to the first surface, thinning the first substrate to a second depth.
    Type: Grant
    Filed: January 14, 2016
    Date of Patent: April 24, 2018
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Herb He Huang, Haiting Li, Jiguang Zhu, Clifford Ian Drowley
  • Patent number: 9935125
    Abstract: On a semiconductor substrate having an SOI region and a bulk silicon region formed on its upper surface, epitaxial layers are formed in source and drain regions of a MOSFET formed in the SOI region, and no epitaxial layer is formed in source and drain regions of a MOSFET formed in the bulk silicon region. By covering the end portions of the epitaxial layers with silicon nitride films, even when diffusion layers are formed by implanting ions from above the epitaxial layers, it is possible to prevent the impurity ions from being implanted down to a lower surface of a silicon layer.
    Type: Grant
    Filed: April 9, 2013
    Date of Patent: April 3, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Takaaki Tsunomura, Yoshiki Yamamoto, Masaaki Shinohara, Toshiaki Iwamatsu, Hidekazu Oda
  • Patent number: 9922941
    Abstract: A strain relaxed silicon germanium layer that has a low defect density is formed on a surface of a silicon substrate without causing wafer bowing. The strain relaxed silicon germanium layer is formed using multiple epitaxial growing, bonding and transferring steps. In the present application, a thick silicon germanium layer having a low defect density is grown on a transferred portion of a topmost silicon germanium sub-layer of an initial strain relaxed silicon germanium graded buffer layer and then bonded to a silicon substrate. A portion of the thick silicon germanium layer is then transferred to the silicon substrate. Additional steps of growing a thick silicon germanium layer having a low defect density, bonding and layer transfer may be performed as necessary.
    Type: Grant
    Filed: September 21, 2016
    Date of Patent: March 20, 2018
    Assignee: International Business Machines Corporation
    Inventors: Praneet Adusumilli, Keith E. Fogel, Alexander Reznicek, Oscar van der Straten
  • Patent number: 9875896
    Abstract: A semiconductor device comprising a substrate having a region protruding from the substrate surface; a relaxed semiconductor disposed on the region; an additional semiconductor disposed on the relaxed semiconductor; and low density dielectric disposed next to and at least partially underneath the relaxed semiconductor and adjacent to the protruding region of the substrate.
    Type: Grant
    Filed: September 7, 2016
    Date of Patent: January 23, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi, Alexander Reznicek
  • Patent number: 9853054
    Abstract: A method for forming a semiconductor structure includes forming a strained silicon germanium layer on top of a substrate. At least one patterned hard mask layer is formed on and in contact with at least a first portion of the strained silicon germanium layer. At least a first exposed portion and a second exposed portion of the strained silicon germanium layer are oxidized. The oxidizing process forms a first oxide region and a second oxide region within the first and second exposed portions, respectively, of the strained silicon germanium.
    Type: Grant
    Filed: September 15, 2016
    Date of Patent: December 26, 2017
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Juntao Li, Zuoguang Liu, Xin Miao
  • Patent number: 9818826
    Abstract: A heterostructure for use in an electronic or optoelectronic device is provided. The heterostructure includes one or more composite semiconductor layers. The composite semiconductor layer can include sub-layers of varying morphology, at least one of which can be formed by a group of columnar structures (e.g., nanowires). Another sub-layer in the composite semiconductor layer can be porous, continuous, or partially continuous.
    Type: Grant
    Filed: October 21, 2014
    Date of Patent: November 14, 2017
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Maxim S. Shatalov, Rakesh Jain, Jinwei Yang, Alexander Dobrinsky, Michael Shur, Remigijus Gaska
  • Patent number: 9818875
    Abstract: A method of fabricating a vertical fin field effect transistor with a strained channel, including, forming a strained vertical fin on a substrate, forming a plurality of gate structures on the strained vertical fin, forming an interlevel dielectric on the strained vertical fin, forming a source/drain contact on the vertical fin adjacent to each of the plurality of gate structures, and selectively removing one or more of the source/drain contacts to form a trench adjacent to a gate structure.
    Type: Grant
    Filed: October 17, 2016
    Date of Patent: November 14, 2017
    Assignee: International Business Machines Corporation
    Inventors: Zhenxing Bi, Kangguo Cheng, Juntao Li, Peng Xu
  • Patent number: 9768289
    Abstract: A uni-terminal transistor device is described. In one embodiment, an n-channel transistor having p-terminal characteristics comprises a first semiconductor layer having a discrete hole level; a second semiconductor layer having a conduction band whose minimum level is lower than that of the first semiconductor layer; a wide bandgap semiconductor barrier layer disposed between the first and the second semiconductor layers; a gate dielectric layer disposed above the first semiconductor layer; and a gate metal layer disposed above the gate dielectric layer and having an effective workfunction selected to position the discrete hole level below the minimum level of the conduction band of the second semiconductor layer for zero bias applied to the gate metal layer and to obtain p-terminal characteristics.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: September 19, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD
    Inventor: Matthias Passlack
  • Patent number: 9752224
    Abstract: Embodiments of the present disclosures provide methods and apparatus for manufacturing semiconductor devices such as transistors used for amplifying or switching electronic signals. Specifically, embodiments of the present disclosure generally relate to a semiconductor device having a film stack including an interlayer of semiconductor material and a buffer layer of semiconductor material underneath an active device layer. In various embodiments, the interlayer may include group III-V semiconductor materials formed between a first surface of a silicon-based substrate and the buffer layer. In certain embodiments the buffer layer may comprise group IV semiconductor materials. The interlayer may have a lattice constant designed to mitigate lattice mismatch between the group IV buffer layer and the silicon-based substrate. The buffer layer may provide improved integration of the active device layer to improve the performance of the resulting device.
    Type: Grant
    Filed: July 14, 2016
    Date of Patent: September 5, 2017
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Zhiyuan Ye, Errol Antonio C. Sanchez, Keun-Yong Ban, Xinyu Bao
  • Patent number: 9742150
    Abstract: An optical amplifier device includes: an optical waveguide core; an active gain material layer stack; and a dielectric material between the active gain material layer stack and the optical waveguide core. The optical waveguide core includes an input portion, a middle portion, an output portion and tapers. The middle portion is connected to the input and output portions via the tapers. The tapers widen outwardly, whereby the middle portion has an effective refractive index that is smaller than an effective refractive index of any of the input and output portions. The active gain material layer stack includes III-V semiconductor material layers having different refractive indices so as to possess an effective refractive index that is larger than the effective refractive index of the middle portion. The active gain material layer stack extends relative to a subsection of the optical waveguide core that includes the middle portion and tapers.
    Type: Grant
    Filed: September 6, 2016
    Date of Patent: August 22, 2017
    Assignee: International Business Machines Corporation
    Inventors: Jens Hofrichter, Folkert Horst
  • Patent number: 9698268
    Abstract: Methods of forming a semiconductor device are provided. A method of forming a semiconductor device includes forming a semiconductor layer on a fin, where the fin and the semiconductor layer include first and second semiconductor materials, respectively. Moreover, the method includes defining first and second active fins that include the second semiconductor material, by removing at least a portion of the fin. Related semiconductor devices are also provided.
    Type: Grant
    Filed: May 19, 2016
    Date of Patent: July 4, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Shigenobu Maeda, Bo-Ram Kim
  • Patent number: 9685587
    Abstract: A superlattice and method for forming that superlattice are disclosed. In particular, an engineered layered single crystal structure forming a superlattice is disclosed. The superlattice provides p-type or n-type conductivity, and comprises alternating host layers and impurity layers, wherein: the host layers consist essentially of a semiconductor material; and the impurity layers consist essentially of a corresponding donor or acceptor material.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: June 20, 2017
    Assignee: The Silanna Group Pty Ltd
    Inventor: Petar Atanackovic
  • Patent number: 9680013
    Abstract: A method and a device made according to the method. The method comprises providing a substrate including a first material, and providing a fin including a second material, the fin being disposed on the substrate and having a device active portion, the first material and the second material presenting a lattice mismatch between respective crystalline structures thereof. Providing the fin includes providing a biaxially strained film including the second material on the substrate; and removing parts of the biaxially strained film to form a substantially uniaxially strained fin therefrom.
    Type: Grant
    Filed: September 5, 2013
    Date of Patent: June 13, 2017
    Assignee: Intel Corporation
    Inventors: Stephen M. Cea, Roza Kotlyar, Jack T. Kavalieros, Martin D. Giles, Tahir Ghani, Kelin J. Kuhn, Markus Kuhn, Nancy M. Zelick
  • Patent number: 9666669
    Abstract: A bipolar junction transistor includes an intrinsic base formed on a substrate. The intrinsic base includes a superlattice stack including a plurality of alternating layers of semiconductor material. A collector and emitter are formed adjacent to the intrinsic base on opposite sides of the base. An extrinsic base structure is formed on the intrinsic base.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: May 30, 2017
    Assignee: International Business Machines Corporation
    Inventors: Karthik Balakrishnan, Stephen W. Bedell, Pouya Hashemi, Bahman Hekmatshoartabari, Alexander Reznicek
  • Patent number: 9660032
    Abstract: A structure includes a substrate and a strain relaxed buffer (SRB) that has a bottom surface disposed on the substrate and an opposite top surface. The SRB is formed to have a plurality of pairs of layers, where a given pair of layers is composed of a layer of Si1-xGex and a layer of Si. The structure further includes a plurality of transistor devices formed above the top surface of the SRB and at least one contact disposed vertically through the top surface of the SRB and partially through a thickness of the SRB. The at least one contact is thermally coupled to at least one of the plurality of the Si layers for conducting heat out of the SRB via the at least one of the plurality of Si layers. A method to form the structure is also disclosed.
    Type: Grant
    Filed: June 22, 2015
    Date of Patent: May 23, 2017
    Assignee: International Business Machines Corporation
    Inventors: Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi, Alexander Reznicek
  • Patent number: 9633904
    Abstract: A method for manufacturing a semiconductor device with epitaxial structure includes following steps: A substrate including a plurality of gate structures formed thereon is provided, and a spacer is respectively formed on sidewalls of each gate structure. Next, a first etching process is performed to form a first recess respectively at two sides of the gate structures and followed by performing an ion implantation to the first recesses. After the ion implantation, a second etching process is performed to widen the first recesses to form widened first recesses and to form a second recess respectively at a bottom of each widened first recess. Then, an epitaxial structure is respectively formed in the widened first recesses and the second recesses.
    Type: Grant
    Filed: November 15, 2016
    Date of Patent: April 25, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yu-Ying Lin, Chueh-Yang Liu, Yu-Ren Wang, Neng-Hui Yang
  • Patent number: 9576798
    Abstract: Methods of fabricating a semiconductor structure include providing a semiconductor-on-insulator (SOI) substrate including a base substrate, a strained stressor layer above the base substrate, a surface semiconductor layer, and a dielectric layer between the stressor layer and the surface semiconductor layer. Ions are implanted into or through a first region of the stressor layer, and additional semiconductor material is formed on the surface semiconductor layer above the first region of the stressor layer. The strain state in the first region of the surface semiconductor layer above the first region of the stressor layer is altered, and a trench structure is formed at least partially into the base substrate. The strain state is altered in a second region of the surface semiconductor layer above the second region of the stressor layer. Semiconductor structures are fabricated using such methods.
    Type: Grant
    Filed: November 6, 2015
    Date of Patent: February 21, 2017
    Assignee: SOITEC
    Inventors: Bich-Yen Nguyen, Walter Schwarzenbach, Christophe Maleville
  • Patent number: 9537009
    Abstract: Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a fast etching region comprising phosphorous in an active region and forming a first trench in the active region by recessing the fast etching region. The methods may also include forming a second trench in the active region by enlarging the first trench using a directional etch process and forming a stressor in the second trench. The second trench may include a notched portion of the active region.
    Type: Grant
    Filed: December 1, 2015
    Date of Patent: January 3, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-Suk Shin, Chul-Woong Lee, Hoi-Sung Chung, Young-Tak Kim, Nae-In Lee
  • Patent number: 9536950
    Abstract: A semiconductor device may include a strain relaxed buffer layer provided on a substrate to contain silicon germanium, a semiconductor pattern provided on the strain relaxed buffer layer to include a source region, a drain region, and a channel region connecting the source region with the drain region, and a gate electrode enclosing the channel region and extending between the substrate and the channel region. The source and drain regions may contain germanium at a concentration of 30 at % or higher.
    Type: Grant
    Filed: January 27, 2015
    Date of Patent: January 3, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae-Hwan Lee, Sangsu Kim
  • Patent number: 9536772
    Abstract: The disclosure relates to a fin structure of a semiconductor device. An exemplary fin structure for a semiconductor device comprises a lower portion protruding from a major surface of a substrate, wherein the lower portion comprises a first semiconductor material having a first lattice constant; an upper portion having an interface with the lower portion, wherein the upper portion comprises a second semiconductor material having a second lattice constant different from the first lattice constant; a first pair of notches lower than the interface and extending into opposite sides of the lower portion, wherein each first notch have a first width; and a second pair of notches extending into opposite sides of the interface, wherein each second notch have a second width greater than the first width.
    Type: Grant
    Filed: July 7, 2015
    Date of Patent: January 3, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Hsien Chen, Tung Ying Lee, Yu-Lien Huang, Chi-Wen Liu