Abstract: Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. The techniques can be implemented, for example, using a standard contact stack such as a series of metals on, for example, silicon or silicon germanium (SiGe) source/drain regions. In accordance with one example such embodiment, an intermediate boron-doped germanium-tin alloy layer is provided between the source/drain and contact metals to significantly reduce contact resistance. Numerous transistor configurations and suitable fabrication processes will be apparent in light of this disclosure, including both planar and non-planar transistor structures (e.g., FinFETs and nanowire transistors). The techniques are particularly well-suited for implementing p-type devices, but can be used for n-type devices if so desired.

Abstract: An apparatus including a transistor device on a substrate including an intrinsic layer including a channel; a source and a drain on opposite sides of the channel; and a diffusion barrier between the intrinsic layer and each of the source and the drain, the diffusion barrier including a conduction band energy that is less than a conduction band energy of the channel and greater than a material of the source and drain. A method including defining an area of an intrinsic layer on a substrate for a channel of a transistor device; forming a diffusion barrier layer in an area defined for a source and a drain; and forming a source on the diffusion barrier layer in the area defined for the source and forming a drain in the area defined for the drain.

Abstract: A field effect transistor having a reduced sheet resistance is provided. A channel layer, a first spacer layer, a second spacer layer, a first electronic barrier layer, and a second electronic barrier layer are sequentially grown on the main surface of a substrate. A gate recess is created, and then an ion implanted section is formed. A third electronic barrier layer and a p-type layer are formed by a metalorganic chemical vapor deposition (MOCVD) method. The p-type layer except a portion at the gate recess is removed. B ions are implanted in the regrown third electronic barrier layer to reform the ion implanted section. A source electrode and a drain electrode are formed on the third electronic barrier layer. Then a gate electrode is formed on the p-type layer.

Abstract: A semiconductor device with one or more fin structures formed from a first material, gate, source, and drain regions formed from a second material, and a contact insulator layer deposited over the substrate, where an etching process applied to the substrate removes the insulator to create a trench over the source region. The device also includes a lower band gap source material that is deposited into the trench, a second contact insulator layer, and a metalizing material that is deposited over the substrate. In some embodiments, the device also includes a higher band gap source material that is deposited into the trench, a second contact insulator layer, and a metalizing material that is deposited over the substrate.

Abstract: A method and structure for mitigating strain loss (e.g., in a FinFET channel) includes providing a semiconductor device having a substrate having a substrate fin portion, an active fin region formed over a first part of the substrate fin portion, a pickup region formed over a second part of the substrate fin portion, and an anchor formed over a third part of the substrate fin portion. In some embodiments, the substrate fin portion includes a first material, and the active fin region includes a second material different than the first material. In various examples, the anchor is disposed between and adjacent to each of the active fin region and the pickup region.

Abstract: An III group nitride semiconductor device comprises: a substrate; a nitride semiconductor layer located on the substrate; a passivation layer located on the nitride semiconductor layer, a portion of the passivation layer in a gate region being etched to expose the nitride semiconductor layer so as to form a gate groove; a composite dielectric layer located on the passivation layer and the gate groove, the composite dielectric layer comprising one or more combination structures of two or more of a nitride dielectric layer, an oxynitride dielectric layer and an oxide dielectric layer which are formed sequentially in the direction away from the substrate; and a source electrode and a drain electrode respectively located in a source region and a drain region on the nitride semiconductor layer, and a gate electrode located in a gate region between the source region and the drain region on the composite dielectric layer.

Abstract: A multilayer semiconductor device structure having different circuit functions on different semiconductor device layers is provided. The semiconductor structure comprises a first semiconductor device layer fabricated on a bulk substrate. The first semiconductor device layer comprises a first semiconductor device for performing a first circuit function. The first semiconductor device layer includes a patterned top surface of different materials. The semiconductor structure further comprises a second semiconductor device layer fabricated on a semiconductor-on-insulator (“SOI”) substrate. The second semiconductor device layer comprises a second semiconductor device for performing a second circuit function. The second circuit function is different from the first circuit function. A bonding surface coupled between the patterned top surface of the first semiconductor device layer and a bottom surface of the SOI substrate is included.

Abstract: An HEMT includes a buffer layer, a hole-supply layer on the buffer layer, a heterostructure on the hole-supply layer, and a source electrode. The hole-supply layer is made of P-type doped semiconductor material, the buffer layer is doped with carbon, and the source electrode is in direct electrical contact with the hole-supply layer, such that the hole-supply layer can be biased to facilitate the transport of holes from the hole-supply layer to the buffer layer.

Abstract: A method for forming a semiconductor structure is disclosed. The method provides a substrate with an insulator pad overlying at least a top portion of the substrate. The method further includes forming a plurality of dielectric columns overlying the substrate and the dielectric pad. Each dielectric column is separated from another dielectric column to form a corresponding plurality of aspect-ration trapping (ART) trenches. The insulator pad spans a bottom portion of a first ART trench of the plurality of ART trenches. A portion of the substrate spans a bottom portion of a second ART trench of the plurality of ART trenches. The method further includes forming a III-V semiconductor material stack in the second ART trench. The method further includes forming a first resistive region in the first ART trench, wherein the first resistive region is in contact with the insulator pad.

Abstract: In certain embodiments, a semiconductor device includes a substrate having an n-doped well feature and an epitaxial silicon germanium fin formed over the n-doped well feature. The epitaxial silicon germanium fin has a lower part and an upper part. The lower part has a lower germanium content than the upper part. A channel is formed from the epitaxial silicon germanium fin. A gate is formed over the epitaxial silicon germanium fin. A doped source-drain is formed proximate the channel.

Abstract: An electronic device can include a transistor structure. In an embodiment, the transistor structure can include a channel region and a drift structure including different semiconductor base materials. In another embodiment, the transistor structure can include a source region and a drain structure including a first region, wherein the source region and the first region include different semiconductor base materials and have the same conductivity type. In another aspect, a process of forming an electronic device can include forming a semiconductor layer; forming a body region; patterning the body region and the semiconductor layer to define a trench having a sidewall; forming a first region of a drain structure along the sidewall of the trench, wherein the first region and body region include different semiconductor base materials and different conductivity types.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to fully depleted silicon on insulator (SOI) semiconductor structures and methods of manufacture. The structure includes: a gate structure formed over a semiconductor material; a source region adjacent to the gate structure; a drain region remote from the gate structure; and a drift region separating the gate structure from the drain region. The drift region includes an epitaxial material grown on the semiconductor material which increases the thickness of the semiconductor material in the drift region.

Abstract: A crossbar switch comprising: a first interconnect, a second interconnect, and a resistance change element. The resistance change element includes: a first electrode connected to the first interconnect and a second electrode connected to the second interconnect which are embedded in a first insulating film on a substrate having a transistor; a second insulating film covering the first insulating film and the first and second electrodes; first and second opening portions exposing parts of an upper surface including end portions of the first and second electrodes from the second insulating film with translational symmetry; first and second resistance change films covering the first and second opening portions and connecting to the first and second electrodes at the opening portions; third and fourth electrodes connecting to the first and second resistance change films; a fifth electrode connecting to the third and fourth electrodes and to a diffusion layer of the transistor.

Abstract: A semiconductor device includes: a substrate including a field region that defines an active region; source/drain regions in the active region; a channel region between the source/drain regions; a lightly doped drain (LDD) region between one of the source/drain regions and the channel region; and a gate structure disposed on the channel region. An upper portion of the active region may include an epitaxial growth layer having a larger lattice constant than silicon (Si), and the source/drain regions and the LDD region may be doped with gallium (Ga).

Abstract: A semiconductor on insulator multilayer structure is provided. The multilayer comprises a high resistivity single crystal semiconductor handle substrate, an optionally relaxed semiconductor layer comprising silicon, germanium, or silicon germanium, an optional polycrystalline silicon layer, a dielectric layer, and a single crystal semiconductor device layer.

Abstract: A device includes a substrate having an N-active region and a P-active region, a layer of silicon-carbon positioned on an upper surface of the N-active region, a first layer of a first semiconductor material positioned on the layer of silicon-carbon, a second layer of the first semiconductor material positioned on an upper surface of the P-active region, and a layer of a second semiconductor material positioned on the second layer of the first semiconductor material. An N-type transistor is positioned in and above the N-active region and a P-type transistor is positioned in and above the P-active region.

Abstract: In a semiconductor device, a width of a second epitaxial layer is greater than a width of a first epitaxial layer, and a thickness of an end portion of the second epitaxial layer, which is in contact with an element isolation portion, is smaller than a thickness of an end portion of the first epitaxial layer, which is in contact with the element isolation portion, and a second shortest distance between the element isolation portion and a second plug is greater than a first shortest distance between the element isolation portion and a first plug.

Abstract: A method of forming a GAA FinFET, including: forming a fin on a substrate, the substrate having a STI layer formed thereon and around a portion of a FIN-bottom portion of the fin, the fin having a dummy gate formed thereover, the dummy gate having a gate sidewall spacer on sidewalls thereof; forming a FIN-void and an under-FIN cavity in the STI layer; forming first spacers by filling the under-FIN cavity and FIN-void with a first fill; removing the dummy gate, thereby exposing both FIN-bottom and FIN-top portions of the fin underneath the gate; creating an open area underneath the exposed FIN-top by removing the exposed FIN-bottom; and forming a second spacer by filling the open area with a second fill; wherein a distance separates a top-most surface of the second spacer from a bottom-most surface of the FIN-top portion. A GAA FinFET formed by the method is also disclosed.

Abstract: The disclosed technology generally relates to semiconductor fabrication, and more particularly to a method of defining routing tracks for a standard cell semiconductor device, and to the standard cell semiconductor device fabricated using the method. In one aspect, a method of defining routing tracks in a target layer over a standard cell semiconductor device includes forming mandrels and forming a first set and a second set of spacers for defining the routing tracks. The standard cell semiconductor device includes a device layer and the routing tracks for contacting a device layer. The routing tracks include at least two pairs of off-center routing tracks, a central routing track arranged between the pairs of off-center routing tracks, and at least two edge tracks arranged on opposing sides of the at least two pairs of off-center routing tracks.

Abstract: A lateral transistor includes a source a gate and a drain connection to a transition layer within a semiconductor substrate. One or more capacitively coupled floating field plates are connected to the source connection such that the source voltage is uniformly distributed across the field plates.

Abstract: A bipolar transistor is supported by a single-crystal silicon substrate including a collector connection region. A first epitaxial region forms a collector region doped with a first conductivity type on the collector connection region. The collector region includes a counter-doped region of a second conductivity type. A second epitaxial region forms a base region of a second conductivity type on the first epitaxial region. Deposited semiconductor material forms an emitter region of the first conductivity type on the second epitaxial region. The collector region, base region and emitter region are located within an opening formed in a stack of insulating layers that includes a sacrificial layer. The sacrificial layer is selectively removed to expose a side wall of the base region. Epitaxial growth from the exposed sidewall forms a base contact region.

Abstract: A semiconductor structure and a method for fabricating the semiconductor structure are provided. The method includes forming an epitaxial layer in a substrate. The epitaxial layer includes a first region having a first crystal plane and a second region having a second crystal plane, and indices of lattice planes of the first crystal plane and the second crystal plane are different. The method also includes forming a capping structure including one or more capping layers on the first region and the second region. Forming the capping layer includes forming an initial capping layer having different thicknesses on the first region and the second region; and etching the initial capping layer to reduce a thickness difference between the initial capping layer on the first region and the initial capping layer on the second region. Further, the method includes forming an electrode electrically connected to the capping structure.

Abstract: A method of manufacturing a semiconductor die includes: forming a power HEMT (high-electron-mobility transistor) in a III-nitride semiconductor substrate, the power HEMT having a gate, a source and a drain; monolithically integrating a first gate driver HEMT with the power HEMT in the III-nitride semiconductor substrate, the first gate driver HEMT having a gate, a source and a drain and logically forming part of a driver; and electrically connecting the first gate driver HEMT to the gate of the power HEMT so that the first gate driver HEMT is operable to turn the power HEMT off or on responsive to an externally-generated control signal received from the driver or other device.

Abstract: A transistor comprises a pair of source/drain regions having a channel region there-between. A transistor gate construction is operatively proximate the channel region. The channel region comprises a direction of current flow there-through between the pair of source/drain regions. The channel region comprises at least one of GaP, GaN, and GaAs extending all along the current-flow direction. Each of the source/drain regions comprises at least one of GaP, GaN, and GaAs extending completely through the respective source/drain region orthogonal to the current-flow direction. The at least one of the GaP, the GaN, and the GaAs of the respective source/drain region is directly against the at least one of the GaP, the GaN, and the GaAs of the channel region. Each of the source/drain regions comprises at least one of elemental silicon and metal material extending completely through the respective source/drain region orthogonal to the current-flow direction. Other embodiments are disclosed.

Abstract: A semiconductor crystal substrate includes a first buffer layer formed of a nitride semiconductor over a substrate, a second buffer layer formed of a nitride semiconductor on the first buffer layer, a first semiconductor layer formed of a nitride semiconductor on or over the second buffer layer, and a second semiconductor layer formed of a nitride semiconductor on the first semiconductor layer. The Fe concentration of the first buffer layer is higher than the C concentration of the first buffer layer. The C concentration of the second buffer layer is higher than the Fe concentration of the second buffer layer.

Abstract: A semiconductor device includes a substrate including a first fin element, a second fin element, and a third fin element. A first source/drain epitaxial feature is disposed over the first and second fin elements. A first portion of the first source/drain epitaxial feature disposed on the first fin element and a second portion of the first source/drain epitaxial feature disposed on the second fin element merge at a merge point. A second source/drain epitaxial feature is disposed over the third fin element. A first sidewall of the second source/drain epitaxial feature interfaces a first third-fin spacer disposed along a first sidewall of the third fin element. A second sidewall of the second source/drain epitaxial feature interfaces a second third-fin spacer disposed along a second sidewall of the third fin element. The merge point has a first height less than a second height of the first third-fin spacer.

Abstract: Provided herein is a method of manufacturing a semiconductor device. The method may include forming an amorphous channel layer. The method may include forming a diffusion barrier on the amorphous channel layer. The method may include forming an amorphous seed layer on the diffusion barrier. The method may include forming a seed layer by crystallizing the amorphous seed layer. The method may include forming a channel layer by crystallizing the amorphous channel layer.

Abstract: A high electron mobility transistor includes a buffer layer, a threshold voltage adjustment layer, a band adjustment layer, a first enhancement layer, a gate electrode, and source/drain electrodes. The threshold voltage adjustment layer is disposed on the buffer layer. A channel region is disposed in the buffer layer adjacent to an interface between the buffer layer and the threshold voltage adjustment layer. The band adjustment layer is disposed on the threshold voltage adjustment layer. The first enhancement layer is conformally covering the threshold voltage adjustment layer and the band adjustment layer. The gate electrode is disposed on the first enhancement layer. The source/drain electrodes are disposed on the buffer layer through the threshold voltage adjustment layer and the first enhancement layer on opposite sides of the gate electrode respectively. The threshold voltage adjustment layer and the first enhancement layer are III-V semiconductors.

Abstract: Techniques are disclosed for forming transistors on the same substrate with varied channel materials. The techniques include forming a replacement material region in the substrate, such region used to form a plurality of fins therefrom, the fins used to form transistor channel regions. In an example case, the substrate may comprise Si and the replacement materials may include Ge, SiGe, and/or at least one III-V material. The replacement material regions can have a width sufficient to ensure a substantially planar interface between the replacement material and the substrate material. Therefore, the fins formed from the replacement material regions can also have a substantially planar interface between the replacement material and the substrate material. One example benefit from being able to form replacement material channel regions with such substantially planar interfaces can include at least a 30 percent improvement in current flow at a fixed voltage.

Abstract: A silicon carbide semiconductor device, including a silicon carbide substrate, a drift layer provided on a front surface of the silicon carbide substrate, an embedded layer selectively provided in a surface layer of the drift layer, an epitaxial layer provided on the drift layer, a channel layer provided on the epitaxial layer, a source region selectively provided in a surface layer of the channel layer, a trench penetrating the source region and the channel layer and reaching the epitaxial layer, a gate electrode provided in the trench via a gate insulating film, a source electrode in contact with the channel layer and the source region, and a drain electrode provided on a rear surface of the silicon carbide substrate. The embedded layer is arranged underneath the trench in a depth direction. A longitudinal direction of the trench, which is perpendicular to the depth direction, is parallel to the off-direction of the silicon carbide substrate.

Abstract: Semiconductor devices having group III-V material active regions and graded gate dielectrics and methods of fabricating such devices are described. In an example, a semiconductor device includes a group III-V material channel region disposed above a substrate. A gate stack is disposed on the group III-V material channel region. The gate stack includes a graded high-k gate dielectric layer disposed directly between the III-V material channel region and a gate electrode. The graded high-k gate dielectric layer has a lower dielectric constant proximate the III-V material channel region and has a higher dielectric constant proximate the gate electrode. Source/drain regions are disposed on either side of the gate stack.

Abstract: A semiconductor device includes first and second active patterns protruding upward from a substrate, a gate electrode crossing the first and second active patterns and extending in a first direction, a first source/drain region on the first active pattern and on at least one side of the gate electrode, and a second source/drain region on the second active pattern and on at least one side of the gate electrode. The first and second source/drain regions have a conductivity type different from each other, and the second source/drain region has a bottom surface in contact with a top surface of the second active pattern and at a lower level than that of a bottom surface of the first source/drain region in contact with a top surface of the first active pattern. The first active pattern has a first width smaller than a second width of the second active pattern.

Abstract: A semiconductor device includes a layered body, a gate electrode, a source electrode, a drain electrode, and a cap layer. The layered body includes a channel layer and a first low resistance region. The channel layer is made of a compound semiconductor. The first low resistance region is provided in a portion on surface side of the layered body. The gate electrode, the source electrode, and the drain electrode are each provided on top surface side of the layered body. The cap layer is provided between the first low resistance region and one or both of the source electrode and the drain electrode.

Abstract: An epitaxial substrate for an electronic device, in which a lateral direction of the substrate is defined as a main current conducting direction and a warp configuration of the epitaxial substrate is adequately controlled, as well as a method of producing the epitaxial substrate. Specifically, the epitaxial substrate for an electron device, including: a Si single crystal substrate; and a Group III nitride laminated body formed by epitaxially growing plural Group III nitride layers on the Si single crystal substrate, wherein a lateral direction of the epitaxial substrate is defined as a main current conducting direction, is characterized in that the Si single crystal substrate is a p-type substrate having a specific resistance value of not larger than 0.01 ?·cm.

Abstract: A FET with a buried gate structure. The FET's gate electrode comprises a plurality of buried gate structures, the tops of which extend above the substrate's top surface and the bottoms of which are buried to a depth at least equal to that of the bottom of the channel layer, or the 2DEG plane within a channel layer for a HEMT, such that the buried gate structures contact the channel layer only from its sides. A head portion above and not in contact with the substrate's top surface contacts the tops of and interconnects all of the buried gate structures. Drain current is controlled by channel width modulation by lateral gating of the channel layer by the buried gates structures. The FET may include at least one field plate which comprises a slit structure in which the field plate is divided into segments.

Abstract: A nitride semiconductor device includes a silicon substrate. A nitride semiconductor layer is formed over the silicon substrate. A gate electrode is formed over the nitride semiconductor layer so as to have a first ring-shaped portion and a second ring-shaped portion connected to the first ring-shaped portion. A first finger electrode is surrounded by the first ring-shaped portion. A second finger electrode is surrounded by the second ring-shaped portion. A third finger electrode is interposed between the first ring-shaped portion and the second ring-shaped portion.

Abstract: A method for manufacturing an electrofluidic device comprising the steps of providing a first plate with features for holding a first fluid, filling a first fluid into features on a first plate; providing a second plate and sealing a second plate onto the first plate forming stacked plates with at least one cavity between the plates, and leaving at least one fill port for a second fluid. Thereafter, the stacked plates are cooled to increase the viscosity of the first fluid so that the first fluid maintains a fixed position as a second fluid is filled into the cavity. Methods are disclosed.

Abstract: A tunneling field effect transistor is formed from a fin of semiconductor material on a support substrate. The fin of semiconductor material includes a source region, a drain region and a channel region between the source region and drain region. A gate electrode straddles over the fin at the channel region. Sidewall spacers are provided on each side of the gate electrode. The source of the transistor is made from an epitaxial germanium content source region grown from the source region of the fin and doped with a first conductivity type. The drain of the transistor is made from an epitaxial silicon content drain region grown from the drain region of the fin and doped with a second conductivity type.

Abstract: A semiconductor device includes a substrate having a working surface, and a plurality of field effect transistor (FET) devices provided on the substrate in a common plane along the working surface. Each FET device includes an active nanochannel structure having opposing end surfaces and a sidewall surface extending between the opposing end surfaces, and an active gate structure surrounding an intermediate portion of the nanochannel structure in contact with the sidewall surface. First and second gate spacers each surrounding a respective end portion of the nanochannel structure in contact with the side wall surface, and first and second source/drain (S/D) structures are in contact with the opposing end surfaces of the nanochannel structure respectively. A single diffusion break provided between first and second FET devices, the single diffusion break including a dummy nanochannel structure connected to an S/D structure of the first FET device and an S/D structure of the second FET device.

Abstract: A PNP transistor is manufactured in parallel with the manufacture of NPN, NMOS, and PMOS transistors. A first semiconductor layer is deposited on a P-type doped semiconductor substrate and divided into first, second, and third regions, with the third region forming the base. An insulating well is deeply implanted into the substrate. First and second third wells, respectively of N-type and P-type are formed to extend between the second region and third region and the insulating well. A third well of P-type is formed below the third region to provide the collector. Insulating layers are deposited over the third region and patterned to form an opening. Epitaxial growth of a second P-type doped semiconductor layer is performed in the opening to provide the emitter.

Abstract: A high-electron-mobility transistor (HEMT) includes a substrate layer of silicon, a first contact disposed on a first surface of the substrate layer, and a number of layers disposed on a second surface of the substrate layer opposite the first surface. A second contact and a gate contact are disposed on those layers. A trench containing conducting material extends completely through the layers and into the substrate layer. In an embodiment of the HEMT, the first contact is a drain contact and the second contact is a source contact. In another embodiment of the HEMT, the first contact is a source contact and the second contact is a drain contact.

Abstract: A semiconductor device includes a single electron transistor (SET) having an island region, a bottom source/drain region under the island region, and a top source/drain region over the island region, a first gap between the bottom source/drain region and the island region, a second gap between the top source/drain region and the island region, and a gate structure on a side of the island region.

Abstract: A semiconductor device includes a switching device having: a substrate configured by a semi-insulating material or a semiconductor; a channel forming layer on the substrate that is configured by a compound semiconductor mainly having a group III nitride; a gate structure configured by a gate electrode on the channel forming layer with a gate insulating film interposed therebetween; and a source electrode and a drain electrode on the channel forming layer at both sides of the gate structure respectively, a collapse inhibiting layer on the channel forming layer in an element region of the channel forming layer where the switching device is arranged that is configured by an insulating material; and a leakage inhibiting layer on the channel forming layer in an element isolation region of the channel forming layer surrounding the element region that is configured by an insulating material different from that of the collapse inhibiting layer.

Abstract: A semiconductor structure includes a substrate having a plurality of fin structures thereon, an isolation oxide structure in the substrate between adjacent two of the plurality of fin structures, a gate disposed on the plurality of fin structures, a gate dielectric layer disposed between the plurality of fin structures and the gate, and a source/drain doped region in each of the plurality of fin structures. The isolation oxide structure has a concave, curved top surface.

Abstract: Methods and structures formed thereby are described, of forming self-aligned contact structures for microelectronic devices. An embodiment includes forming a trench in a source/drain region of a transistor device disposed in a device layer, wherein the device layer is on a substrate, forming a fill material in the trench, forming a source/drain material on the fill material, forming a first source/drain contact on a first side of the source/drain material, and then forming a second source drain contact on a second side of the source/drain material.

Abstract: FinFET devices including III-V fin structures and silicon-based source/drain regions are formed on a semiconductor substrate. Silicon is diffused into the III-V fin structures to form n-type junctions. Leakage through the substrate is addressed by forming p-n junctions adjoining the source/drain regions and isolating the III-V fin structures under the channel regions.

Abstract: Semiconductor structures and fabrication methods are provided. An exemplary fabrication method includes providing a base substrate having a semiconductor substrate and a plurality of fins on the semiconductor substrate; forming an isolation structure on the semiconductor substrate, between adjacent fins and with a top surface lower than the top surfaces of the fins; forming a gate structure across of the fins by covering portions of top and side surfaces of the fins; forming a sidewall material layer to cover the gate structure and the fins; etching the sidewall material layer to form gate sidewall spacers on side surfaces of the gate structure and shadowing sidewall spacers on portions of side surfaces of the fins adjacent to the isolation structure; and performing an ion implantation process on the fins using the gate sidewall spacers and the shadowing sidewall spacers as a mask to form lightly doped regions in the fins.

Abstract: An embodiment of a semiconductor device includes a semiconductor substrate that includes an upper surface and a semiconductor layer, a first dielectric layer disposed over the semiconductor substrate, and a regrown contact formed through a first opening in the first dielectric layer. The regrown contact includes a regrown region formed over the semiconductor substrate, an overhang region coupled to the regrown region and formed over the first dielectric layer, adjacent the first opening, and a conductive cap formed over the regrown region and the overhang region. A method for fabricating the semiconductor device includes forming the first dielectric layer over the semiconductor substrate, forming the first opening in the first dielectric layer, forming a regrown semiconductor layer within the first opening and over the first dielectric layer, forming a conductive cap over the regrown semiconductor layer, and etching the regrown semiconductor layer outside the conductive cap.

Abstract: A semiconductor device and method includes: forming a first fin and a second fin on a substrate; forming a dummy gate material over the first fin and the second fin; forming a recess in the dummy gate material between the first fin and the second fin; forming a sacrificial oxide on sidewalls of the dummy gate material in the recess; filling an insulation material between the sacrificial oxide on the sidewalls of the dummy gate material in the recess; removing the dummy gate material and the sacrificial oxide; and forming a first replacement gate over the first fin and a second replacement gate over the second fin.

Abstract: The present application discloses a method for fabricating a TFT backplane and a TFT backplane. The method includes: providing a substrate; subsequently forming a first active region, a first oxide layer, a nitride layer and a first and a second gate independently of each other on the substrate; removing the nitride layer not covered by the first and second gate electrodes; depositing a second insulating layer; forming a second active region with different material from the first active region on the on the second insulating layer above the second gate electrode; forming a first and a second source electrodes, a first and a second drain electrodes respectively. This method can improve the performance of the TFT backplane.