Abstract: An aspect of the present invention provides a semiconductor device that includes a first transistor including a source region, a drain region provided in the same device region as the source region, and a loop-shaped gate electrode region, and a second transistor sharing, with the first transistor, the loop-shaped gate electrode region and the source region or the drain region.

Abstract: The invention provides a thin film semiconductor element and a method of manufacturing the same to achieve lowering the resistance of gate electrodes, lowering the capacitance of source electrodes, and enhancing etching characteristics. The thin film semiconductor element can include a semiconductor film provided on a substrate, source and drain electrodes connected to the semiconductor film, and a gate electrode provided on the semiconductor film with an insulating film interposed therebetween. The film thickness of the source and drain electrodes can be smaller than the film thickness of the gate electrode.

Abstract: A CMOS output stage is disclosed. The CMOS output stage comprises a substrate and at least one well coupled to the substrate. The CMOS output stage also includes a plurality of slots provided through the one well into the substrate. Each of the slots are oxidized. Each of the plurality of slots are filled with metal to provide a plurality of power busses. One of the power busses provides a ground. One of the power busses provides an output. One of the power busses provides a power connector. This results in the buried power buss metal always having oxide isolated surroundings. This feature allows all of these power busses to be established wherever necessary without causing any circuit issues since they are always insulated from other areas of the device. One of the power busses provides a ground. One of the power busses provides an output. One of the power busses provides a power connector.

Abstract: The gate tunnel leakage current is increased in the up-to-date process, so that it is necessary to reduce the gate tunnel leakage current in the LSI which is driven by a battery for use in a cellular phone and which needs to be in a standby mode at a low leakage current. In a semiconductor integrated circuit device, the ground source electrode lines of logic and memory circuuits are kept at a ground potential in an active mode, and are kept at a voltage higher than the ground potential in an unselected standby mode. The gate tunnel leakage current can be reduced without destroying data.

Abstract: In order for circuit blocks 1 to 3 composed by the CMOS process, and analog lines 5-1, 5-2, and 5-3 connected thereto not to overlap on the layout, the analog lines 5-1 and 5-2 are wired so that such lines roundabout the layout of the AM/FM common circuit block 3. Through this, the distance of the signal line within the AM/FM common circuit block 3 and the analog lines 5-1 and 5-2 can become as long as possible, the signal line within the AM/FM common circuit block 3 and the analog lines 5-1 and 5-2 would not be coupled via parasitic capacity, and mutual interference occurring between the signal line and the analog lines 5-1 and 5-2 can be suppressed.

Abstract: A configuration is provided to reduce variations in the width of the gate of a read-out transistor without increasing the surface area of a memory cell. To do this, a recess is provided in an inner corner of a gate electrode that is bent into an L-shape. The recess is located so as to face a rectangular portion of an active region of the memory cell.

Abstract: A semiconductor integrated circuit device has: a semiconductor substrate defining a plurality of rows, each row including areas for a sequence of cells; a plurality of active regions disposed in each of the rows constituting semiconductor elements of associated cells; and a wiring region of stripe shape elongated along a direction of row, defined on the semiconductor substrate outside of the active regions in each row, and including wirings belonging to the associated cells, each wiring region having height in a direction crossing the row direction, the wiring region having locally different height.

Abstract: This invention provides a printhead capable of decreasing the ON resistance value without increasing the heater board size in order to downsize the heater board, an image printing apparatus using the printhead, and a control method therefor. In the printhead, heater resistors are series-connected to normal MOS transistors in each group on a heat board. The pitch of the heater resistors and the pitch of the normal MOS transistors are designed equal to each other in order to shorten the connection line. One high-breakdown-voltage MOS transistor is arranged in each group, and the pitch is designed to a length corresponding to the product of the pitch of the heater resistors and the number x of heater resistors. The high-breakdown-voltage MOS transistor has a higher ON resistance value per unit area than that of the normal MOS transistor. However, the area of the high-breakdown-voltage MOS transistor is larger by x times than that of the normal MOS transistor.

Abstract: The invention includes BIFETRAM devices. Such devices comprise a bipolar transistor in combination with a field effect transistor (FET) in a three-dimensional stacked configuration. The memory devices can be incorporated within semiconductor-on-insulator (SOI) constructions. The base region of the bipolar device can be physically and electrically connected to one of the source/drain regions of the FET to act as a storage node for the memory cell. The semiconductor material of the SOI constructions can comprise Si/Ge, and the active region of the FET can extend into the Si/Ge. The SOI constructions can be formed over any of a number of substrates, including, for example, semiconductive materials, glass, aluminum oxide, silicon dioxide, metals and/or plastics.

Abstract: A memory cell has a trench capacitor, in which the area required over a terminal area of the trench capacitor is advantageously reduced by the formation of a particularly thin insulation collar. The insulation collar is reduced to such an extent that although a lateral current is prevented, the formation of a parasitic field-effect transistor is permitted. In order that, however, overall no current flows via the parasitic field-effect transistor, a second parasitic field-effect transistor is disposed in a manner connected in series, but is not turned on. This is achieved by the formation of a thicker second insulation collar that isolates the filling of the trench capacitor from the surrounding substrate.

Abstract: To reduce the width of isolation between the first and second p channel MIS•FETs driven by different voltages, a first p channel MIS•FET driven by a first supply voltage and a second p channel MIS•FET driven by a second supply voltage higher than the first supply voltage are arranged in the same n well of the same semiconductor substrate, and the second supply voltage is supplied as a common well bias voltage to the n well.

Abstract: An integrated semiconductor circuit, having active components lying in mutually adjoining wells of a respective first and second conduction type, wherein the active components respectively are associated with substrate contacts lying in direct proximity to an edge bounding the mutually adjoining wells, is disclosed. Preferably, structures of the active components other than the contacts are arranged to lie further away from the edge and the circuit/layout structures are not mirror-symmetrical with respect to a center line of the circuit chip.

Abstract: A cellular MOS array becomes denser by employing an asymmetric structure, in which the areas of the sources are reduced without changing the length and the width of the channel thereof, and thereby the chip size is reduced and the cost is lowered.

Abstract: In a memory cell, the substrate contact region of an NMOS transistor and the well contact region of a PMOS transistor are arranged perpendicularly to a floating gate. In a cell array, the memory cell and another memory cell arranged axisymmetrically with respect to the memory cell are alternately arranged in the column direction to constitute a sub array, and the sub arrays arranged in the column direction are arranged in parallel or axisymmetically in the row direction. With this arrangement, the substrate contact region, the well contact region, and the diffusion region of the PMOS transistor can be shared between the adjacent memory cells, thereby reducing the area of the cell array.

Abstract: A MIS type semiconductor device and a method for fabricating the same characterized in that impurity regions are selectively formed on a semiconductor substrate or semiconductor thin film and are activated by radiating laser beams or a strong light equivalent thereto from above so that the laser beams or the equivalent strong light are radiated onto the impurity regions and on an boundary between the impurity region and an active region adjoining the impurity region.

Abstract: First standard cells with no contact pattern and second standard cells having first contact patterns are placed on an area where a cell array is to be formed. Second contact patterns are additionally placed between the first standard cells. The second contact patterns are placed in an area that lacks a power supply capability.

Abstract: The present invention is a level of an integrated circuit. The level of integrated circuit has a first area having a plurality of features having a first density and the level of the integrated circuit has a second area adjacent to the first area wherein the second area has a plurality of dummy features having a density substantially similar to the first density.

Abstract: A semiconductor device comprises a support layer made of semiconductor, a diffusion layer formed by implanting impurities in a surface layer of the support layer, a buried insulating layer provided on the diffusion layer, an island-like active layer provided on the buried insulating layer, a channel region formed in the active layer, source and drain regions formed in the active layer, sandwiching the channel region, a gate insulating film formed on the channel region, a gate electrode formed on the gate insulating film and on side surfaces of the island-like active layer, and insulated and isolated from the channel, source, and drain regions, and an electrode connected to the active layer.

Abstract: Briefly, in accordance with one embodiment of the invention, an integrated circuit includes: a gate array architecture. The gate array architecture includes a semiconductor substrate having a plurality of N-type diffusion regions and P-type diffusion regions. The diffusion regions have partially overlying polysilicon landing sites to form N-type and P-type transistors. The regions are relatively sized to form two distinct transistor sizes, smaller N- and P-type transistors and larger N- and P-type transistors.

Abstract: A composite barrier layer formed between a glass film and active regions of a memory device is disclosed. The composite barrier layer comprises an oxide layer formed by atomic deposition process and an insulating layer, for example a nitride barrier layer, formed over the oxide layer. The composite barrier layer eliminates the diffusion of impurity atoms from the glass film into the active regions of the device.

Abstract: A new method to form a SRAM memory cell in an integrated circuit device is achieved. The method comprises providing a bi-stable flip-flop cell having a data storage node and a data bar storage node. A first capacitor is formed coupled to the data bar storage node, and a second capacitor is formed coupled to the data storage node. The first and second capacitors comprise a first conductor layer overlying a second conductor layer with a dielectric layer therebetween. One of the first and second conductor layers is coupled to ground. A new SRAM device is disclosed.

Abstract: A semiconductor device comprises a semiconductor substrate, an N-channel MISFET and a P-channel MISFET provided on the semiconductor substrate, each of the N- and P-channel MISFETs being isolated by an isolation region and having a gate insulating film, a first gate electrode film provided on the gate insulating film of the N-channel MISFET and composed of a first metal silicide, a second gate electrode film provided on the gate insulating film of the P-channel MISFET and composed of a second metal silicide made of a second metal material different from a first metal material composing the first metal silicide, and a work function of the first gate electrode film being lower than that of the second gate electrode film.

Abstract: Provided is a field emission device having a mesh gate. The object of this research is to provide a field emission display (FED) using a triode field emission device for preventing increase of operation voltage, and securing high concentration of electron beams. The operation properties of the FED is different based on a structure of an extraction electrode. In this research, the extraction electrode is formed on the electron emitting source and it has a plurality of openings corresponding to the locations of carbon nanotube mixture. The concentration of the electron beams is raised and leakage current is suppressed by using an insulating mesh gate plate. The upper part of the openings has a smaller diagram than the lower part. The high concentration of electron beams and little leakage current can be generated by adding auxiliary electrodes or optimizing the shape of electrodes.

Abstract: There is provided a semiconductor device which includes a first interlayer insulating film (first insulating film) formed over a silicon (semiconductor) substrate, a capacitor formed on the first interlayer insulating film and having a lower electrode, a dielectric film, and an upper electrode, a fourth interlayer insulating film (second insulating film) formed over the capacitor and the first interlayer insulating film, and a metal pattern formed on the fourth interlayer insulating film over the capacitor and its periphery to have a stress in an opposite direction to the fourth interlayer insulating film. As a result, characteristics of the capacitor covered with the interlayer insulating film can be improved.

Abstract: Well bias circuitry for selectively biasing the voltages of the well areas of an integrated circuit. In one embodiment, the well bias circuitry includes a switching cell located in a row of cells of the integrated circuit for selectively coupling a voltage supply line to a well bias line. The switching cell may include two level shifters, each for providing a voltage to a gate of a coupling transistor to make the coupling transistor non conductive in response to an enable signal. The switching cells may be sequentially coupled such that the coupling transistors of each of the switching cells are not made conductive at the same time so as to reduce inrush current due to changing the well bias from a well bias voltage to a supply voltage. In one example, the switching cells may include delay circuitry for delaying the change in state of the enable signal before being provided to the next switching cell.

Abstract: A semiconductor display device which includes the polycrystalline silicon TFTs is constructed by a pixel region and a peripheral circuit and TFT characteristics required for each circuit are different. For example, an LDD structure TFT having a large off-current suppressing effect is suitable for the pixel region. Also, a GOLD structure TFT having a large hot carrier resistance is suitable for the peripheral circuit. When the performance of the semiconductor display device is improved, it is suitable that difference TFT structures are used for each circuit. In the case where the GOLD structure TFT having both Lov regions and Loff regions is formed, ion implantation into the Lov regions is independently performed using a negative resist pattern formed in a self alignment by a rear surface exposure method as a mask, and thus impurity concentrations of the Lov regions and the Loff regions can be independently controlled.

Abstract: A standardized silicon platform chip has a substrate surface with an array of unconnected transistors that surround islands. The islands have circuit elements that are interconnectable within each island to form a plurality of varied circuit functions for each of the islands. The varied circuit functions include both application functions and clock functions. Interconnect layers are deposited over the substrate surface to interconnect the circuit elements within each island to complete the varied circuit functions. The varied circuit functions include varied levels of integration including at least gates, flip-flops, clock trees, and oscillators. The varied circuit functions are custom connectable to the array of unconnected transistors to form standard clock resources for the standardized silicon platform chip.

Abstract: A structure and method are provided in which an n-type field effect transistor (NFET) and a p-type field effect transistor (PFET) each have a channel region disposed in a single-crystal layer of a first semiconductor and a stress is applied at a first magnitude to a channel region of the PFET but not at that magnitude to the channel region of the NFET. The stress is applied by a layer of a second semiconductor which is lattice-mismatched to the first semiconductor. The layer of second semiconductor is formed over the source and drain regions and extensions of the PFET at a first distance from the channel region of the PFET and is formed over the source and drain regions of the NFET at a second, greater distance from the channel region of the NFET, or not formed at all in the NFET.

Abstract: A method for controlling electric conduction on nanoscale wires is disclosed. The nanoscale wires are provided with controllable regions axially and/or radially distributed. Controlling those regions by means of microscale wires or additional nanoscale wires allows or prevents electric conduction on the controlled nanoscale wires. The controllable regions are of two different types. For example, a first type of controllable region can exhibit a different doping from a second type of controllable region. The method allows one or more of a set of nanoscale wires, packed at sublithographic pitch, to be independently selected.

Abstract: Plurality of pixels (102) are arranged on the substrate. Each of the pixels (102) is provided with an EL element which utilizes as a cathode a pixel electrode (105) connected to a current control TFT (104). On a counter substrate (110), a light shielding film (112) is disposed at the position corresponding to periphery of each pixel (102), while a color filter (113) is disposed at the position corresponding to each of the pixels (102). This light shielding film makes the contour of the pixels clear, resulting in an image display with high definition. In addition, it is possible to fabricate the EL display device of the present invention with most of an existing manufacturing line for liquid crystal display devices. Thus, an amount of equipment investment can be significantly reduced, thereby resulting in a reduction in the total manufacturing cost.

Abstract: This invention provides a printhead capable of decreasing the ON resistance value without increasing the heater board size in order to downsize the heater board, an image printing apparatus using the printhead, and a control method therefor. In the printhead, heater resistors are series-connected to normal MOS transistors in each group on a heat board. The pitch of the heater resistors and the pitch of the normal MOS transistors are designed equal to each other in order to shorten the connection line. One high-breakdown-voltage MOS transistor is arranged in each group, and the pitch is designed to a length corresponding to the product of the pitch of the heater resistors and the number x of heater resistors. The high-breakdown-voltage MOS transistor has a higher ON resistance value per unit area than that of the normal MOS transistor. However, the area of the high-breakdown-voltage MOS transistor is larger by x times than that of the normal MOS transistor.

Abstract: In a nonvolatile memory array in which each cell (110) has two floating gates (160), for any two consecutive memory cells, one source/drain region (174) of one of the cells and one source/drain region of the other one of the cells are provided by a contiguous region of the appropriate conductivity type (e.g. N type) formed in a semiconductor substrate (120). Each such contiguous region provides source/drain regions to only two of the memory cells in that column. The bitlines (180) overlie the semiconductor substrate in which the source/drain regions are formed. The bitlines are connected to the source/drain regions.

Abstract: A base cell is configured such that P-type regions 11 to 13 are arrayed in a column direction in an N-type well 10, N-type regions 21 to 23 are arrayed in a column direction in a P-type well 20 next to the N-type well, gate lines 34A and 35B passing above a channel between the P-type regions and further between the N-type regions are formed in a row direction, and well contact regions 16C and 26C are formed in the wells 10 and 20 at outer ends thereof, respectively, while no gate contacts are formed at the outer ends. Power supply lines VDD and VSS connected to the well contact regions are formed in the column direction in a second wiring layer above a first wiring layer.

Abstract: A BiCMOS semiconductor, and manufacturing method therefore, is provided. A semiconductor substrate having a collector region is provided. A pseudo-gate is formed over the collector region. An emitter window is formed in the pseudo-gate to form an extrinsic base structure. An undercut region beneath a portion of the pseudo-gate is formed to provide an intrinsic base structure in the undercut region. An emitter structure is formed in the emitter window over the intrinsic base structure. An interlevel dielectric layer is formed over the semiconductor substrate, and connections are formed through the interlevel dielectric layer to the collector region, the extrinsic base structure, and the emitter structure. The intrinsic base structure comprises a compound semiconductive material such as silicon and silicon-germanium, or silicon-germanium-carbon, or combinations thereof.

Abstract: A physical properties calculating apparatus accepts inputs of material and thickness of an intermediate layer, accepts inputs of material and thickness of an outer layer, accepts inputs of material and thickness of an inner layer, accepts an input of outside air humidity, accepts an input of inside humidity, accepts an input of outside air temperature, calculates the moisture content of the intermediate layer by activating a sub-routine for calculating the moisture content of the intermediate layer based on the accepted various information and preset information, and calculates physical properties such as oxygen transmission rate of the intermediate layer based on the calculated moisture content of the intermediate layer and the accepted outside air temperature. It is possible to know the physical properties of the intermediate layer that forms a packaging material for packaging products to be packaged, such as foods, without actually measuring the physical properties.

Abstract: The speed of CMOS circuits is improved by imposing a longitudinal tensile stress on the NFETs and a longitudinal compressive stress on the PFETS, by implanting in the sources and drains of the NFETs ions from the eighth column of the periodic table and hydrogen and implanting in the sources and drains of the PFETs ions from the fourth and sixth columns of the periodic table.

Abstract: A semiconductor device layout involving the following: arranging active regions of a plurality of transistors having at least more than one first and second electrodes disposed on a substrate; arranging a plurality of gates of transistors between more than one first and second electrodes of those active regions respectively by positioning at least more than one gates having predetermined width and length at a constant gap on the substrate; and arranging a plurality of dummy gates having predetermined width and length between a plurality of transistors (or between and outside transistors) at the same gap as that of the gates of transistors on the substrate, so that all the gates of transistors are arranged at a constant gap to minimize the variance of process deviations and accordingly reduce the difference of threshold voltage of transistors, thereby increasing reliability of the semiconductor device.

Abstract: According to one exemplary embodiment, a semiconductor data array comprises an active segment situated on a substrate. The semiconductor data array can be, for example, a ROM array. The semiconductor data array further comprises a first word line situated over the active segment and a second word line situated substantially parallel to the first word line, where the second word line is not situated over the active segment. The semiconductor data array further comprises a column situated over the active segment, the first word line, and the second word line. The semiconductor data array further comprises a contact situated on the active segment, where the contact couples the active segment to the column, where the contact is separated from the first word line by a first distance and from the second word line by a second distance, and where the first distance is less than the second distance.

Abstract: The semiconductor device of the invention includes transistors for a driver and dummy patterns formed to be adjacent to the end portion of each output bit group constituting a cathode driver, anode drivers and anode drivers.

Abstract: Formation of elements of a vertical transistor is described, particularly, a gate-source-drain arrangement of a CMOS transistor. Vertical transistors are used frequently in the integrated circuit art. Accordingly, improved methods for their formation, which are not limited by constraints of photolithography, have great utility and importance. Those of skill in the art will appreciate that the techniques described may be used to fabricate other types of devices as well. For example, junctions of a bipolar transistor (as well as other device junction types) may be fabricated using the methods described herein.

Abstract: Accurate determination of gate dielectric thickness is required to produce high-reliability and high-performance ultra-thin gate dielectric semiconductor devices. Large area gate dielectric capacitors with ultra-thin gate dielectric layers suffer from high gate leakage, which prevents the accurate measurement of gate dielectric thickness. Accurate measurement of gate dielectric thickness of smaller area gate dielectric capacitors is hindered by the relatively large parasitic capacitance of the smaller area capacitors. The formation of first and second dummy structures on a wafer allow the accurate determination of gate dielectric thickness. First and second dummy structures are formed that are substantially similar to the gate dielectric capacitors except that the first dummy structures are formed without the second electrode of the capacitor and the second dummy structures are formed without the first electrode of the capacitor structure.

Abstract: A synchronous double-data-rate semiconductor memory device is adapted to receive write data on both the rising and falling edges of a data strobe signal derived from an externally-applied system clock. In the write path circuitry for each data pin of the device, adjustable delay elements are provided to enable the adjustment of the setup and hold times of write data applied to the data pin relative to the data strobe signal. The delays are separately adjustable for data present during the rising edge of the data strobe signal and for data present during the falling edge of the data strobe signal. The setup and hold window for write data is thus optimizable on a per-bit basis rather than a per-cycle basis. In one embodiment, a delay circuit is provided for generating delaying the rising edge data and the falling edge data by different delay intervals.

Abstract: In a MOS array, current loss at distances further away from the drain and source contacts is compensated for by adjusting the length of the polygate. In an array with drain and source contacts near the middle of the structure, the length of the polygate tapers off along the width of the polygate towards both ends of the polygate.

Abstract: An array of non-volatile memory cells is arranged in a plurality of rows and columns where each cell has a first region and a second region spaced apart from one another with a channel region therebetween for the conduction of charges between the first region and the second region. A first plurality of row lines electrically connect the second region of cells in the same row. A plurality of column lines electrically connect the first region of cells in the same column. A plurality of strap lines connect certain of the row lines with each strap line electrically connecting a second plurality of row lines not immediately adjacent to one another, wherein row lines connected to a first strap line are interleaved with row lines connected to a second strap line.

Abstract: A power semiconductor device 10 has increased breakdown voltage due to an oxide termination structure. A peripheral trench 58 is filled with a dielectric material, such as silicon dioxide. The trench extends below the P well 22 that includes the source 32. The electric field at the border to P well 22 and trench 60 turns upward toward the surface and passes through dielectric 60. A field plate 64 coves portions of the P well 22 and the dielectric 60.

Abstract: A semiconductor device includes: a semiconductor substrate having two types of active regions that are a PMOS region and an NMOS region separated from each other in plan view by a PN separation film; and a dual-gate electrode extending linearly across the PMOS region, the PN separation film and the NMOS region collectively on an upper side of the semiconductor substrate. The dual-gate electrode includes a P-type portion, an N-type portion and a PN junction positioned therebetween. The PN junction includes a silicide region. The silicide region is apart from both the PMOS region and the NMOS region and formed within the area of the PN separation film in plan view.

Abstract: A standard cell for a plurality of power supplies comprises a first power line and a second power line electrically isolated from the first power line. An N well is arranged in spaced relation with the whole peripheral boundaries of the standard cell. In the case where the standard cells are arranged adjacently to each other in the direction along the power lines or in the direction orthogonal thereto, the N well in the standard cell for a plurality of power supplies is isolated from the N wells of the adjacent standard cells in the direction along the power lines or in the direction orthogonal thereto, as the case may be.

Abstract: The present invention pertains to formation of a PMOS transistor wherein a layer of silicon or SiGe inhibits p-type dopant from entering into an underlying gate dielectric layer. The p-type dopant can be added to a gate electrode material that overlies the silicon or SiGe layer and can diffuse down toward the silicon or SiGe layer. The layer of silicon or SiGe may be formed to a thickness of about 5 to 120 nanometers and doped with a dopant, such as indium (In), for example, to deter the p-type dopant from passing through the silicon or SiGe layer. The dopant may have a peak concentration within the layer of silicon or SiGe near the interface of the silicon or SiGe layer with the underlying layer of gate dielectric material. Allowing the gate electrode to be doped with the p-type dopant (e.g., boron) facilitates forming the transistor with an associated work function having a desired value (e.g., coincident with a Fermi level of about 4.8 to about 5.6 electron volts).

Abstract: The invention provides integrated semiconductor devices that are formed upon an SOI substrate having different crystal orientations that provide optimal performance for a specific device. Specifically, an integrated semiconductor structure including at least an SOI substrate having a top semiconductor layer of a first crystallographic orientation and a semiconductor material of a second crystallographic orientation, wherein the semiconductor material is substantially coplanar and of substantially the same thickness as that of the top semiconductor layer and the first crystallographic orientation is different from the second crystallographic orientation is provided. The SOI substrate is formed by forming an opening into a structure that includes at least a first semiconductor layer and a second semiconductor layer that have different crystal orientations. The opening extends to the first semiconductor layer.

Abstract: A method for forming a trimmed gate in a transistor comprises the steps of forming a polysilicon gate conductor on a semiconductor substrate and trimming the polysilicon portion by a film growth method chosen from among selective surface oxidation and selective surface nitridation. The trimming step may selectively compensate n-channel and p-channel devices. Also, the trimming film may optionally be removed by a method chosen from among anisotropic and isotropic etching. Further, gate conductor spacers may be formed by anisotropic etching of the grown film. The resulting transistor may comprise a trimmed polysilicon portion of a gate conductor, wherein the trimming occurred by a film growth method chosen from among selective surface oxidation and selective surface nitridation.