Abstract: Forming a back-illuminated type CMOS image sensor, includes process for formation of a registration mark on the wiring side of a silicon substrate during formation of an active region or a gate electrode. A silicide film using an active region may also be used for the registration mark. Thereafter, the registration mark is read from the back side by use of red light or near infrared rays, and registration of the stepper is accomplished. It is also possible to form a registration mark in a silicon oxide film on the back side (illuminated side) in registry with the registration mark on the wiring side, and to achieve the desired registration by use of the registration mark thus formed.

Abstract: An electronic device includes an n-channel transistor and a p-channel transistor. The p-channel transistor has a first gate electrode with a first work function and a first channel region including a semiconductor layer immediately adjacent to a semiconductor substrate. In one embodiment, the first work function is less than the valence band of the semiconductor layer. In another embodiment, the n-channel transistor has a second gate electrode with a second work function different from the first work function and closer to a conduction band than a valence band of a second channel region. A process of forming the electronic device includes forming first and second gate electrodes having first and second work functions, respectively. First and second channel regions having a same minority carrier type are associated with the first and second gate electrodes, respectively.

Abstract: A low cost IC solution is disclosed in accordance with an embodiment to provide Super CMOS microelectronics macros. Hereinafter, the Super CMOS or Schottky CMOS all refer to SCMOS. The SCMOS device solutions with a niche circuit element, the complementary low threshold Schottky barrier diode pairs (SBD) made by selected metal barrier contacts (Co/Ti) to P- and N- Si beds of the CMOS transistors. A DTL like new circuit topology and designed wide contents of broad product libraries, which used the integrated SBD and transistors (BJT, CMOS, and Flash versions) as basic components. The macros are composed of diodes that are selectively attached to the diffusion bed of the transistors, configuring them to form generic logic gates, memory cores, and analog functional blocks from simple to the complicated, from discrete components to all grades of VLSI chips. Solar photon voltaic electricity conversion and bio-lab-on-a-chip are two newly extended fields of the SCMOS IC applications.

Abstract: A semiconductor device is provided. An isolation structure is formed in a substrate to define a first and a second active region, and a channel active region therebetween. A field implant region is formed below a portion of the isolation structure around the first, second, and channel active regions. A channel active region includes two first sides defining a channel width. The distance from each first side to a second side of a neighboring field implant region is d1. The shortest distance from a third side of each first or second active region to an extension line of each second side of the field implant region is d2. R=d1/d2, where 0.15?R?0.85. A gate structure covers the channel active region and extends over a portion of the isolation structure. Source/drain doped regions are formed in the first and the second active regions.

Abstract: A semiconductor integrated circuit device capable of suppressing variations in transistor characteristics due to the well proximity effect is provided. Standard cell rows are arranged in a vertical direction, each standard cell row including standard cells arranged in a horizontal direction. In the standard cell rows, positions of the N well and the P region in the vertical direction are switched every other row. Adjacent standard cell rows share the P region or the N well. A distance from a PMOS transistor located at an end of a standard cell row to an end of an N well is greater than or equal to a width of an N well shared by standard cell rows.

Abstract: Receiver circuits using nanotube-based switches and transistors. A receiver circuit includes a differential input having a first and second input link, a differential output having a first and second output link, and first and second switching elements in electrical communication with the input links and the output links. Each switching element has an input node, an output node, a nanotube channel element, and a control structure disposed in relation to the nanotube channel element to controllably form and unform an electrically conductive channel between said input node and said output node. First and second MOS transistors are each in electrical communication with a reference signal and with the output node of a corresponding one of the first and second switching elements.

Abstract: Gallium nitride material devices and methods associated with the devices are described. The devices may be designed to provide enhanced thermal conduction and reduced thermal resistance. The increased thermal conduction through and out of the gallium nitride devices enhances operability of the devices, including providing excellent RF operation, reliability, and lifetime.

Abstract: A hybrid CMOL stack enables more efficient design of CMOS logical circuits. The hybrid CMOL structure includes a first substrate having a CMOS device layer on the substrate, a first interconnect layer with interface pins over the CMOS device layer of the first substrate, a first array of nanowires connected to the interface pins of the first interconnect layer, a layer of nanowire junction material over the first array of nanowires, a second array of nanowires over the nanowire junction material, a second interconnect layer having interface pins disposed over the second array of nanowires, the interface pins being connected to the second array of nanowires, and a second substrate, the second substrate including a second CMOS device layer disposed over the second interconnect layer.

Abstract: A semiconductor device includes a plurality of circuit blocks respectively arranged both in a first direction and in a second direction that intersects the first direction. A plurality of signal lines extend in one direction of the first direction and the second direction to correspond to and extend over the circuit blocks arranged in the one direction among the plurality of circuit blocks, the signal lines being spaced apart in the other direction of the first direction and the second direction. A plurality of power lines are arranged over the circuit blocks, each power line extending along at least one of the signal lines in the one direction. A dummy power line is arranged between one of the power lines and a signal line adjacent to the one of the power lines in the other direction.

Abstract: A memory device, and method of making the same, in which a trench is formed into a substrate of semiconductor material. The source region is formed under the trench, and the channel region between the source and drain regions includes a first portion that extends substantially along a sidewall of the trench and a second portion that extends substantially along the surface of the substrate. The floating gate is disposed in the trench, and is insulated from the channel region first portion for controlling its conductivity. The control gate is disposed over and insulated from the channel region second portion, for controlling its conductivity. The erase gate is disposed at least partially over and insulated from the floating gate. The erase gate includes a notch, and the floating gate includes an edge that directly faces and is insulated from the notch.

Abstract: A lower electrode projects outward from a common end face of an upper electrode and a capacitor film. A protective film, which is made of a different material from the capacitor film, is deposited on top of a part of the lower electrode outside the end face. The protective film also extends to the position at a certain distance inward from the end face, so that it is placed between the capacitor film and the lower electrode. The capacitor film thereby has a stepped surface near the end face due to the presence of the protective film, which suppresses the progress of damage during etching of the upper electrode and the capacitor film. Further, the protective film prevents the occurrence of damage in the lower electrode.

Abstract: A number of modified lateral DMOS (LDMOS) transistor arrays are formed and tested to determine if a measured value, such as a series on-resistance, substrate current, breakdown voltage, and reliability, satisfies process alignment requirements. The modified LDMOS transistor arrays are similar to standard LDMOS transistor arrays such that the results of the modified LDMOS transistor arrays can be used to predict the results of the standard LDMOS transistor arrays.

Abstract: A vertical transistor including a substrate, a gate, a base line and a gate dielectric layer is provided. The substrate includes a pillar protruding out of a surface of the substrate. The pillar includes a first doped region, a channel region and a second doped region from bottom to top. The gate is disposed on a sidewall at one side of the channel region. The base line is disposed on a sidewall at the other side of the channel region and not contacted with the gate. The gate dielectric layer is disposed between the gate and the channel region.

Abstract: A memory cell that includes a first electrode layer; a spin filter layer that includes a material that has exchange splitting in the conduction band; and a magnetic layer, wherein the magnetization of the second magnetic layer can be effected by the torque of electrons tunneling through, wherein the spin filter layer is between the first electrode layer and the magnetic layer.

Abstract: An exemplary embodiment relates to a method for forming a metal oxide semiconductor field effect transistor (MOSFET). The method includes providing a substrate having a gate formed above the substrate and performing at least one of the following depositing steps: depositing a spacer layer and forming a spacer around a gate and gate insulator located above a layer of silicon above the substrate; depositing an etch stop layer above the spacer, the gate, and the layer of silicon; and depositing a dielectric layer above the etch stop layer. At least one of the depositing a spacer layer, depositing an etch stop layer, and depositing a dielectric layer comprises high compression deposition which increases in tensile strain in the layer of silicon.

Abstract: Embodiments of an apparatus and methods for providing a workfunction metal gate electrode on a substrate with doped metal oxide semiconductor structures are generally described herein. Other embodiments may be described and claimed.

Abstract: To provide a semiconductor integrated circuit device advantageous against EM and ESD. A plurality of I/O cells; a power wire formed of a plurality of interconnect layers over the above-described I/O cells; a bonding pad formed in an upper layer of the power wire and in a position corresponding to the I/O cell; and lead-out areas capable of electrically coupling the I/O cell to the bonding pad are provided. The above-described power wire includes a first power wire and a second power wire, and the above-described I/O cell includes first elements coupled to the first power wire and second elements coupled to the second power wire. The first element is placed on the first power wire side, and the second element is placed on the second power wire side. The first power wire and the second power wire can allow for a high current due to the interconnect layers over the I/O cells, thus having robustness against EM and ESD.

Abstract: There is provided an engineering change order (ECO) cell, which includes: a function circuit including at least one PMOS transistor with a P-diffusion layer and a first poly gate, at least one NMOS transistor with an N-diffusion layer and a second poly gate; a first power layer supplying the at least one PMOS transistor with a first power voltage; and a second power layer supplying the at least one NMOS transistor with a second power voltage. The first poly gate of the PMOS transistor is isolated from the second poly gate of the NMOS transistor.

Abstract: A structure, method and a design structure for preventing latchup in a gate array. The design structure including: a NFET gate array and a PFET gate array in a substrate; an electrically conductive through via extending from a bottom surface of the substrate toward a top surface of the substrate the NFET gate array and PFET gate array, the through via electrically contacting the P-well.

Abstract: Transistors having a Hafnium-Silicon gate electrode and high-k dielectric are disclosed. A workpiece is provided having a gate dielectric formed over the workpiece, and a gate formed over the gate dielectric. The gate may comprise a layer of a combination of Hf and Si. The layer of the combination of Hf and Si of the gate establishes the threshold voltage Vt of the transistor. The transistor may comprise a single NMOS transistor or an NMOS transistor of a CMOS device.

Abstract: A CMOS image sensor includes a photodiode, and a plurality of transistors for transferring charges accumulated at the photodiode to one column line, wherein at least one transistor among the plurality of transistors has a source region wider than a drain region, for increasing a driving current.

Abstract: A semiconductor device includes: a P-type semiconductor layer formed in a surface region of a semiconductor substrate; a first gate insulating film formed on the P-type semiconductor layer; a first gate electrode; and a first source region and a first drain region formed in the P-type semiconductor layer to interpose a region under the first gate electrode in a direction of gate length. The first gate electrode includes: a first silicide film formed on the first gate insulating film and containing nickel silicide having a first composition ratio of nickel to silicon as a main component; a conductive film formed on the first silicide film; and a second silicide film formed on the conductive film and containing nickel silicide having a second composition ratio of nickel to silicon as a main component. The second composition ratio is larger than the first composition ratio.

Abstract: A semiconductor structure having improved carrier mobility is provided. The semiconductor structures includes a hybrid oriented semiconductor substrate having at least two planar surfaces of different crystallographic orientation, and at least one CMOS device located on each of the planar surfaces of different crystallographic orientation, wherein each CMOS device has a stressed channel. The present invention also provides methods of fabricating the same. In general terms, the inventive method includes providing a hybrid oriented substrate having at least two planar surfaces of different crystallographic orientation, and forming at least one CMOS device on each of the planar surfaces of different crystallographic orientation, wherein each CMOS device has a stressed channel.

Abstract: Disclosed are a design method and apparatus in which information regarding a cell is input, the cell having taps in a substrate surface, for supplying the potentials of respective ones of wells in which active elements are formed, and source diffusion regions in the substrate surface, conductivity types thereof being opposite those of the wells. The taps are converted to conductivity types identical with those of the source diffusion regions to obtain source regions and freely set the well potentials of the cell to any potentials. If the cell is one having shorting portions electrically connecting taps and sources and the shorting portions are diffusion regions of the same conductivity type as that of the taps, then the shorting portions are converted to conductivity types identical with those of the source diffusion regions to obtain source regions.

Abstract: According to an embodiment, there is provided a thin film transistor substrate divided into a display area displaying the image and a non-display besides the display area, the thin film transistor substrate comprising: a common voltage line for MPS (mass production system) test and a grounding line for MPS (mass production system) test formed at the edge of the non-display area in parallel; an insulating layer covering the common voltage line for MPS (mass production system) test and the grounding line for MPS (mass production system) test; and an electrode layer formed on the insulating layer corresponded to the common voltage line for MPS (mass production system) test and the grounding line for MPS (mass production system) test. Thus, the present invention provides a thin film transistor substrate and a fabricating method thereof for minimizing defects due to static electricity.

Abstract: A semiconductor integrated circuit having a substantially rectangular standard cell divided by first borderlines opposed to other standard cells longitudinally adjacent to the standard cell and second borderlines opposed to other standard cells laterally adjacent to the standard cell, the standard cell has: a p-type MOS transistor having first diffused regions and a first gate electrode; an n-type MOS transistor having second diffused regions and a second gate electrode with STI disposed for device isolation between the n-type MOS transistor and the p-type MOS transistor substantially in parallel with the first borderlines; dummy p-type MOS transistors having third gate electrodes disposed on the second borderlines so as to be adjacent to the first diffused regions of the p-type MOS transistor, the third gate electrodes being connected to power supply wiring so as to turn off the dummy p-type MOS transistors; and dummy n-type MOS transistors having fourth gate electrodes disposed on the second borderlines so

Abstract: Disclosed is a semiconductor wafer and method of fabricating the same. The semiconductor wafer is comprised of a semiconductor layer formed on an insulation layer on a base substrate. The semiconductor layer includes a surface region organized in a first crystallographic orientation, and another surface region organized in a second crystallographic orientation. The performance of a semiconductor device with unit elements that use charges, which are activated in high mobility to the crystallographic orientation, as carriers is enhanced. The semiconductor wafer is completed by forming the semiconductor layer with the second crystallographic orientation on the plane of the first crystallographic orientation, growing an epitaxial layer, forming the insulation layer on the epitaxial layer, and then bonding the insulation layer to the base substrate.

Abstract: Field programmable device (FPD) chips with large logic capacity and field programmability that are in-circuit programmable are described. FPDs use small versatile nonvolatile nanotube switches that enable efficient architectures for dense low power and high performance chip implementations and are compatible with low cost CMOS technologies and simple to integrate.

Abstract: An integrated circuit (IC) includes at least a first complementary MOS (CMOS) circuit, the first CMOS circuit comprising one or more first n-channel MOS (NMOS) transistors and one or more first p-channel MOS (PMOS) transistors, where the first NMOS transistors and the first PMOS transistors are arranged in the first CMOS circuit to drive at least a first common node of the first CMOS circuit. An average of the effective gate channel lengths of the first NMOS transistors (first NMOS average length) is at least 2% greater than an average of the effective gate channel lengths of the first PMOS transistors (first PMOS average length).

Abstract: A protection diode is used in a CMOS integrated circuit device to direct charged particles to benign locations and prevent damage to the device. The protection diode includes a well region of a first conductivity type formed in a surface of a semiconductor substrate, a heavily doped P-type impurity region disposed within the well region, a heavily doped N-type impurity region disposed within the well region and an STI structure interposed therebetween. A top surface of the STI structure extends above the surface. A silicide resistant block-out layer is formed over the STI structure and extends laterally beyond the STI structure, covering any counterdoped sections that may undesirably be formed in the substrate adjacent the STI structure during implantation operations. The method for forming the structure utilizes processing operations and materials used in the formation of the CMOS integrated circuit device.

Abstract: A flash memory device can include a semiconductor fin protruding from a semiconductor substrate of a first conductive type to extend in one direction, a first doped layer and a second doped layer provided to an upper portion and a lower portion of the semiconductor fin, respectively, to be vertically spaced apart from each other, the first and second doped layers having a second conductive type, and a plurality of word lines extending over a top and a sidewall of the semiconductor fin to intersect the direction. The word lines overlap the first doped layer and the second doped layer to have vertical channels.

Abstract: A transistor circuit for an array device comprises a plurality of thin film transistors electrically connected in parallel and provided on a common substrate. The transistors are arranged on the substrate as at least two rows (20i, 2O2, 2O3) of transistors, and the source lines (30) of the transistors in the first and second rows have different widths and the drain lines (32) of the transistors in the first and second rows have different widths. All sources (30) are connected together and all drains (32) are connected together, and a source connection is provided to an end portion of the wider source lines and a drain connection is provided to an end portion of the wider drain lines. This provide a source and drain layout that reduces layout area and pitch of wide channel TFTs, whilst preventing degradation in the source and drain terminals/lines due to high current densities. The layout essentially comprises groups of small parallel TFTs, which are in turn connected in parallel.

Abstract: A semiconductor device includes an anti-fuse portion and a memory cell portion each including a MOSFET structure having a gate insulating film formed on a semiconductor substrate and a gate electrode formed on the gate insulating film; wherein a depletion ratio in the gate electrode of the anti-fuse portion is different from the depletion ratio in the gate electrode of the memory cell portion, and the depletion ratio in the gate electrode of the anti-fuse portion is lower than the depletion ratio in the gate electrode of the memory cell portion.

Abstract: A semiconductor device is composed of: an array of CMOS primitive cells provided in a circuit region; a power supply line extended along the array of the CMOS primitive cells and connected to the CMOS primitive cells; a ground line extended along the array of the CMOS primitive cells and connected to the CMOS primitive cells; a first decoupling capacitor provided under the power supply line; a second decoupling capacitor provided under the ground line. The first decoupling capacitor is formed of a PMOS transistor having a gate connected to the ground line. At least one of the source and drain of the PMOS transistor is connected to the power supply line. The second decoupling capacitor is formed of an NMOS transistor having a gate connected to the power supply line. At least one of the source and drain of the NMOS transistor is connected to the ground line.

Abstract: A semiconductor device and a method of fabricating a semiconductor device, wherein the method comprises forming, on a substrate, a plurality of planarized fin bodies to be used for customized fin field effect transistor (FinFET) device formation; forming a nitride spacer around each of the plurality of fin bodies; forming an isolation region in between each of the fin bodies; and coating the plurality of fin bodies, the nitride spacers, and the isolation regions with a protective film. The fabricated semiconductor device is adapted to be used in customized applications as a customized semiconductor device.

Abstract: Systems and methods are disclosed to process a semiconductor substrate by fabricating a first layer on the substrate using semiconductor fabrication techniques; fabricating a second layer above the first layer having one or more NANO-bonding areas; self-assembling one or more NANO-elements; and bonding the NANO-elements to the NANO-bonding areas.

Abstract: A CMOS image sensor and a method of fabricating the same are provided. The CMOS image sensor includes: an epitaxial layer of a first conductivity type, formed in a semiconductor substrate of the first conductivity type; a blue photodiode region of a second conductivity type, formed in the epitaxial layer at a first depth; a green photodiode region of the second conductivity type, spaced apart from the blue photodiode region and formed in the epitaxial layer at a second depth larger than the first depth; and a red photodiode region of the second conductivity type, spaced apart from the green photodiode region and formed in the epitaxial layer at a third depth larger than the second depth.

Abstract: A method of forming crystalline Si:C in source and drain regions is provided. After formation of shallow trench isolation and gate electrodes of field effect transistors, gate spacers are formed on gate electrodes. Preamorphization implantation is performed in the source and drain regions, followed by carbon implantation. The upper portion of the source and drain regions comprises an amorphous mixture of silicon, germanium, and/or carbon. An anti-reflective layer is deposited to enhance the absorption of a laser beam into the silicon substrate. The laser beam is scanned over the silicon substrate including the upper source and drain region with the amorphous mixture. The energy of the laser beam is controlled so that the temperature of the semiconductor substrate is above the melting temperature of the amorphous mixture but below the glass transition temperature of silicon oxide so that structural integrity of the semiconductor structure is preserved.

Abstract: A bond pad structure of an integrated circuit is provided. The bond pad structure includes a conductive bond pad, a first dielectric layer underlying the bond pad, and an Mtop plate located in the first dielectric layer and underlying the bond pad. The Mtop plate is a solid conductive plate and is electrically coupled to the bond pad. The bond pad structure further includes a first passivation layer over the first dielectric layer wherein the first passivation layer has at least a portion under a middle portion of the bond pad. At least part of an active circuit is located under the bond pad.

Abstract: Provided is a CMOS image sensor with an asymmetric well structure of a source follower. The CMOS image sensor includes: a well disposed in an active region of a substrate; a drive transistor having one terminal connected to a power voltage and a first gate electrode disposed to cross the well; and a select transistor having a drain-source junction between another terminal of the drive transistor and an output node, and a second gate electrode disposed in parallel to the drive transistor. A drain region of the drive transistor and a source region of the select transistor are asymmetrically arranged.

Abstract: A semiconductor device includes first and second transistor devices. The first device includes a first substrate region, a first gate electrode, and a first gate dielectric. The first gate dielectric is located between the first substrate region and the first gate electrode. The second device includes a second substrate region, a second gate electrode, and a second gate dielectric. The second gate dielectric is located between the second substrate region and the second gate electrode. The first gate dielectric includes a first high-k layer having a dielectric constant of 8 or more. Likewise, the second gate dielectric includes a second high-k layer having a dielectric constant of 8 or more. The second high-k layer has a different material composition than the first high-k layer.

Abstract: This invention relates to a printhead substrate capable of suppressing an increase in wiring width and an increase in the size of a substrate formed by a film forming process while increasing the number of simultaneously driven printing elements in order to improve the printing performance, a printhead using the substrate, and a printing apparatus using the printhead. The wiring lines of the substrate are formed into a common wiring line, and energy applied to a heating resistance element is prevented from deviating from a stable ink discharge range owing to the difference in the number of simultaneously driven heating resistance elements. For this purpose, a driving element is greatly downsized in comparison with a conventional one, and the operation region of a MOS transistor is shifted from the non-saturation region to the saturation region.

Abstract: Forming a semiconductor structure includes providing a substrate having a strained semiconductor layer overlying an insulating layer, providing a first device region for forming a first plurality of devices having a first conductivity type, providing a second device region for forming a second plurality of devices having a second conductivity type, and thickening the strained semiconductor layer in the second device region so that the strained semiconductor layer in the second device region has less strain that the strained semiconductor layer in the first device region. Alternatively, forming a semiconductor structure includes providing a first region having a first conductivity type, forming an insulating layer overlying at least an active area of the first region, anisotropically etching the insulating layer, and after anisotropically etching the insulating layer, deposing a gate electrode material overlying at least a portion of the insulating layer.

Abstract: A complementary metal oxide semiconductor integrated circuit may be formed with a PMOS device formed using a replacement metal gate and a raised source drain. The raised source drain may be formed of epitaxially deposited silicon germanium material that is doped p-type. The replacement metal gate process results in a metal gate electrode and may involve the-removal of a nitride etch stop layer.

Abstract: A platform application specific integrated circuit (ASIC) including a base layer. The base layer generally comprises a predefined input/output (I/O) region and a predefined core region. The predefined input/output (I/O) region may comprise a plurality of pre-diffused regions disposed in the platform ASIC. The predefined core region may comprise one or more metal layers defining a plurality of power regions formed according to a custom design created after the base layer is fabricated. The base layer can be customized by depositing one or more metal layers.

Abstract: An integrated circuit. The integrated circuit comprises an area having a layout aligned in rows. Each row is definable by a pair of row boundaries. The integrated circuit also comprises a plurality of cells, comprising a first set of cells. Each cell in the first set of cells spans at least two rows and comprises a PMOS transistor having a source/drain region that spans across one of the row boundaries and an NMOS transistor having a source/drain region that spans across one of the row boundaries.

Abstract: An integrated circuit (IC) includes a memory cell having source/drain regions for defining source/drains of a first pull-up or pull-down (PU/PD) transistor for a first storage node, a second PU/PD transistor for a second storage node, and driver, cell pass, and buffer pass transistors. The memory cell includes a first gate electrode region for the first PU/PD and driver transistors, a second gate electrode region for the cell pass and buffer pass transistors, and a third gate electrode region for the second PU/PD transistor. The third gate electrode region and the cell pass transistor are coupled to the first storage node and the first gate electrode region is coupled to the second storage node. The buffer pass and driver transistors are coupled to a source/drain path of the cell pass transistor and the buffer pass transistor is coupled between a bitline (BL) node and the driver transistor.

Abstract: In general, in one aspect, a method includes forming N-diffusion and P-diffusion fins in a semiconductor substrate. A P-diffusion gate layer is formed over the semiconductor substrate and removed from the N-diffusion fins. A pass-gate N-diffusion gate layer is formed over the semiconductor substrate and removed from the P-diffusion fins and pull-down N-diffusion fins. A pull-down N-diffusion layer is formed over the semiconductor substrate.

Abstract: A structure, method and a design structure for preventing latchup in a gate array. The design structure including: a NFET gate array and a PFET gate array in a substrate; an electrically conductive through via extending from a bottom surface of the substrate toward a top surface of the substrate the NFET gate array and PFET gate array, the through via electrically contacting the P-well.

Abstract: According to an aspect of the present invention, there is provided a nonvolatile semiconductor memory device, comprising a plurality of memory strings, each of the memory strings being constituted with a plurality of electrically erasable memory cells being serially connected each other, the memory strings comprising: a columnar semiconductor layer perpendicularly extending toward a substrate; a plurality of conductive layers being formed in parallel to the substrate and including a first space between a sidewall of the columnar semiconductor layers; and characteristic change layer being formed on the sidewall of the columnar semiconductor layer faced to the first space or a sidewall of the conductive layer faced to the first space and changing characteristics accompanying with applied voltage; wherein the plurality of the conductive layers have a function of a relative movement to a prescribed direction for the columnar semiconductor layer.