Abstract: The package includes a substrate, a first chip, a second chip, multiple first bumps and multiple second bumps. The substrate has a first region and a second region. The first region is substantially coplanar with the second region. The first bumps connect the first chip and the second chip. The second bumps connect the first chip and the second region of the substrate, wherein the second chip is over the first region of the substrate. The second bumps have a height greater than that of the first bumps plus the second chip. The substrate does not have an opening accommodating the second chip. The first bumps may be gold bumps or solder bumps. The second bumps may be solder bumps.

Abstract: A memory array includes a base circuitry layer and a plurality of memory array layers stacked sequentially to form the memory array. Each memory array layer is electrically coupled to the base circuitry layer. Each memory array layer includes a plurality of memory units. Each memory unit includes a vertical pillar transistor electrically coupled to a memory cell.

Abstract: A processing layer, such as silicon, is formed on a metal silicide contact followed by a metal layer. The silicon and metal layers are annealed to increase the thickness of the metal silicide contact. By selectively increasing the thickness of silicide contacts, Rs of transistors in iso and nested regions can be matched.

Abstract: A nonvolatile programmable logic switch according to an embodiment includes: a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type; a memory cell transistor including a first insulating film formed on the first semiconductor region, a charge storage film formed on the first insulating film, a second insulating film formed on the charge storage film, and a control gate formed on the second insulating film; a pass transistor including a third insulating film formed on the second semiconductor region, and a gate electrode formed on the third insulating film and electrically connected to the first drain region; a first electrode applying a substrate bias to the first semiconductor region, the first electrode being formed in the first semiconductor region; and a second electrode applying a substrate bias to the second semiconductor region, the second electrode being formed in the second semiconductor region.

Abstract: A method of forming an apparatus includes forming a plurality of deep trenches and a plurality of shallow trenches in a first region of a substrate. At least one of the shallow trenches is positioned between two deep trenches. The shallow trenches and the deep trenches are parallel to each other. A layer of conductive material is deposited over the first region and a second region of the substrate. The layer of conductive material is etched to define lines separated by gaps over the first region of the substrate, and active device elements over the second region of the substrate. The second region of the substrate is masked and the lines are removed from the first region of the substrate. Elongate trenches are etched where the lines were removed while the second region of the substrate is masked.

Abstract: A shared contact structure, semiconductor device and method of fabricating the semiconductor device, in which the shared contact structure may include a gate electrode disposed on an active region of a substrate and including facing first and second sidewalls. The first sidewall may be covered with an insulating spacer. The source/drain regions may be formed within the active region adjacent the first sidewall, and provided on the opposite side of the second sidewall. A corner protection pattern may be formed adjacent the source/drain regions and the insulating spacer, and covered by an inter-layer dielectric. A shared contact plug may be formed through the inter-layer dielectric, to be in contact with the gate electrode, corner protection pattern and source/drain regions.

Abstract: A method for fabricating a semiconductor device includes: forming a plurality of photoresist patterns over a substrate structure; forming an insulation layer for a spacer over a structure including the photoresist patterns; forming a plurality of spacers on sidewalls of the photoresist patterns by anisotropically etching the insulation layer, and forming a first opening through the insulation layer; and forming second openings in the insulation layer to expose the substrate structure.

Abstract: A method and apparatus for trimming a high-resolution digital-to-analog converter (DAC) utilizes floating-gate synapse transistors to trim the current sources in the DAC by providing a trimmable current source. Fowler-Nordheim electron tunneling and hot electron injection are the mechanisms used to vary the amount of charge on the floating gate. Since floating gate devices store charge essentially indefinitely, no continuous trimming mechanism is required, although one could be implemented if desired. By trimming the current sources with high accuracy, a DAC can be built with a much higher resolution and with smaller size than that provided by intrinsic device matching.

Abstract: A system includes a semiconductor device. The semiconductor device includes a first semiconductor layer comprising first transistors, wherein the first transistors are interconnected by at least one metal layer comprising aluminum or copper. The second mono-crystallized semiconductor layer includes second transistors and is overlaying the at least one metal layer, wherein the second mono-crystallized semiconductor layer is less than 150 nm in thickness, and at least one of the second transistors is an N-type transistor and at least one of the second transistors is a P-type transistor.

Abstract: A circuit and method are provided for switching in a semiconductor based high power switch. Complementary p-type based transistors are utilized along insertion loss insensitive paths allowing biasing voltages to alternate between supply and ground, allowing for negative voltage supplies and blocking capacitors to be dispensed with, while improving performance.

Abstract: In addition to a memory macro region and functional circuit regions on a substrate, a semiconductor integrated circuit device includes a dummy pattern region 40 arranged between the functional circuit regions and between the memory macro region 10 and the functional circuit regions and including a dummy pattern. The dummy pattern has a pattern identical to that of diffusion layers and gate electrodes of a memory cell pattern in a memory cell array region. An area ratio of dummy diffusion layer(s) and dummy gate electrode(s) in the dummy pattern region is equal to or greater than that of the diffusion layers and the gate electrode(s) in the memory cell array region.

Abstract: Semiconductor devices (102) and fabrication methods (10) are provided, in which a nitride film (130) is formed over NMOS transistors to impart a tensile stress in ail or a portion of the NMOS transistor to improve carrier mobility. The nitride layer (130) is initially deposited over the transistors at low temperature with high hydrogen content to provide a moderate tensile stress in the semiconductor body prior to back-end processing. Subsequent back-end thermal processing reduces the film hydrogen content and causes an increase in the applied tensile stress.

Abstract: A semiconductor structure, such as a field effect device structure, and more particularly a CMOS structure, includes a gate dielectric that is at least in-part aligned to an active region of a semiconductor substrate over which is located the gate dielectric. The gate dielectric comprises other than a thermal processing product of the semiconductor substrate. In particular, the gate dielectric may be formed using an area selective deposition method such as but not limited to an area selective atomic layer deposition method. Within the context of a CMOS structure, the invention provides particular advantage insofar as the use of a self-aligned method for forming a gate dielectric aligned upon an active region of a semiconductor substrate may avoid a masking process that may otherwise be needed to strip portions of an area non-selective blanket gate dielectric.

Abstract: System and method for transistor level routing is disclosed. A preferred embodiment comprises a semiconductor device including a first semiconductor device formed on a first active area in a substrate, the first semiconductor device having a first gate stack comprising a first high-k dielectric layer, a first metal layer and a first poly-silicon layer. The semiconductor device further includes a second semiconductor device formed on a second active area in the substrate, the second semiconductor device having a second gate stack comprising a second high-k dielectric layer, a second metal layer and a second poly-silicon layer. An electrical connection connects the first semiconductor device with the second semiconductor device and overlies the first active area, the second active area and a portion of the substrate between the first active area and the second active area.

Abstract: A cell library intended to be used to form an integrated circuit, this library defining a first cell including a first MOS transistor of minimum dimensions, and a second cell including a second MOS transistor of lower leakage current, wherein the second cell takes up the same surface area as the first cell, and the second MOS transistor has a gate of same length as the gate of the first MOS transistor across at least a first width in its central portion, and of greater length across at least a second width on either side of the central portion.

Abstract: A semiconductor integrated circuit according to one aspect of the present invention may includes a plurality of driving circuits to drive a respective plurality of word lines with either a first voltage supplied from a first power supply or a second voltage supplied from a second power supply in accordance with a control signal, and a plurality of gate transistors in each of which a gate is connected to one of the plurality of word lines, and a connection state between a storage node and a bit line is changed based on the voltage provided to the word line connected to the gate. In the semiconductor integrated circuit, a gate oxide film of each of the plurality of gate transistors is thinner than a gate oxide film of each of transistors constituting the plurality of driving circuits.

Abstract: Example embodiments relate to a semiconductor memory device and a system in which a plurality of semiconductor layers are stacked on each other. A 3-dimensional (3D) semiconductor memory device may include a plurality of semiconductor layers that are stacked on each other. The plurality of semiconductor layers may have the same memory cell structure. The 3D semiconductor memory device may include a first memory region including at least one semiconductor layer for storing system data and a second memory region including at least one semiconductor layer for storing data aside from the system data. The system data may include at least one piece of data selected from the group consisting of a booting code, a system code, and application software.

Abstract: In a vertical-type memory device and a method of manufacturing the vertical-type memory device, the vertical memory device includes an insulation layer pattern of a linear shape provided on a substrate, pillar-shaped single-crystalline semiconductor patterns provided on both sidewalls of the insulation layer pattern and transistors provided on a sidewall of each of the single-crystalline semiconductor patterns. The transistors are arranged in a vertical direction of the single-crystalline semiconductor pattern, and thus the memory device may be highly integrated.

Abstract: Semiconductor devices and fabrication methods are provided, in which metal transistor replacement gates are provided for CMOS transistors. The process provides dual or differentiated work function capability (e.g., for PMOS and NMOS transistors) in CMOS processes.

Abstract: A semiconductor memory includes a plurality of stripe-like active areas formed by stacking, in a direction perpendicular to a substrate, a plurality of layers extending parallel to the substrate, a first gate electrode formed on first side surfaces of the active areas, the first side surfaces being perpendicular to the substrate, a second gate electrode formed on second side surfaces of the active areas, the second side surfaces being perpendicular to the substrate. The layers are patterned in self-alignment with each other, intersections of the active areas and the first gate electrode form a plurality of memory cells, and the plurality of memory cells in an intersecting plane share the first gate electrode.

Abstract: Silicon germanium (SiGe) is epitaxially grown on a silicon channel above nFET and pFET regions of a substrate. SiGe is removed above the nFET regions. A device includes a silicon channel above the nFET regions and a SiGe channel above the pFET regions.

Abstract: Provided are a thin film transistor (TFT) panel, a method of fabricating the same, and an organic light emitting display device (OLED) including the same. The TFT panel has a TFT region and a capacitor region. A TFT is formed in the TFT region and a capacitor is formed in the capacitor region. The TFT includes an active layer that includes a source and a drain regions. A gate insulation layer is formed on the active layer, and a gate electrode is formed on the gate insulation layer over the active layer. A source and a drain electrodes are formed over the active layer, and connected to the source and drain regions, respectively. In the TFT region, an interlayer insulation layer is formed between the gate electrode and the source/drain electrodes. In the capacitor region, an interlayer insulation layer is formed between a capacitor lower electrode and a capacitor upper electrode to form a capacitor.

Abstract: A gate in a semiconductor device is formed to have a dummy gate pattern that protects a gate. Metal lines are formed to supply power for a semiconductor device and transfer a signal. A semiconductor device includes a quad coupled receiver type input/output buffer. The semiconductor device is formed with a gate line that extends over an active region, and a gate pad located outside of the active region. The gate line and the gate pad are adjoined such that the gate line and a side of the gate pad form a line. Dummy gates may also be applied. The semiconductor device includes a first metal line patterns supplying power to a block having a plurality of cells, a second metal line pattern transferring a signal to the cells, and dummy metal line patterns divided into in a longitudinal direction.

Abstract: A method for forming, on a surface of a thinned-down semiconductor substrate, a contact connected to a metal track of an interconnect stack formed on the opposite surface of the thinned-down substrate, including the steps of: forming, on the side of a first surface of a substrate, an insulating region penetrating into the substrate and coated with a conductive region and with an insulating layer crossed by conductive vias, the vias connecting a metal track of the interconnect stack to the conductive region; gluing the external surface of the interconnect stack on a support and thinning down the substrate; etching the external surface of the thinned-down substrate and stopping on the insulating region; etching the insulating region and stopping on the conductive region; and filling the etched opening with a metal.

Abstract: A semiconductor device comprises a gate structure on a semiconductor substrate and a recessed region in the semiconductor substrate. The recessed region has a widest lateral opening that is near a top surface of the semiconductor substrate. The widest lateral opening undercuts the gate structure.

Abstract: According to an aspect of the present invention, there is provided a semiconductor IC that includes a plurality of standard cells arranged in a first direction on a semiconductor substrate, and a first diffusion layer connected to a first power source and a second diffusion layer connected to a second power source in the each standard cell, wherein the first diffusion layers as well as the second diffusion layers of neighboring standard cells are integrally formed.

Abstract: A display apparatus including a TFT array substrate on which TFTs are formed in an array, a counter substrate disposed so as to face the TFT array substrate, and a sealing pattern for adhering the TFT array substrate and the counter substrate to each other, wherein the counter substrate has a counter electrode, and the TFT array substrate has a first conductive layer, a first insulating film formed on the first conductive layer, a second conductive layer disposed so as to intersect the first conductive layer via the first insulating film, a second insulating film formed on the second conductive layer and having at least two layers, and common electrode wiring provided below the sealing pattern and electrically connected to the counter electrode by the sealing pattern, and the sealing pattern overlaps the second conductive layer via the second insulating film.

Abstract: A display device of high definition, multiple colors and low power consumption includes a display panel having a pixel section in which pixels are arrayed in the form of a matrix at the cross points of a plurality of data lines and a plurality of scanning lines, a scanning circuit for applying voltage sequentially to the plurality of scanning lines, and a data-line driver, which receives display data supplied by a host device, for applying signals corresponding to the display data to the plurality of data lines. Provided external to the display panel is a controller IC having a display memory for storing display data corresponding to the pixel section, an output buffer for reading data out of the display memory and outputting this data to the display panel, and a controller for controlling the display memory and output buffer and communication with the host device.

Abstract: Forming a back-illuminated type CMOS image sensor, includes process for formation of a registration mark on the wiring side of a silicon substrate during formation of an active region or a gate electrode. A silicide film using an active region may also be used for the registration mark. Thereafter, the registration mark is read from the back side by use of red light or near infrared rays, and registration of the stepper is accomplished. It is also possible to form a registration mark in a silicon oxide film on the back side (illuminated side) in registry with the registration mark on the wiring side, and to achieve the desired registration by use of the registration mark thus formed.

Abstract: An EEPROM according to the present invention includes: a semiconductor layer of a first conductive type; and a first insulating film formed on the semiconductor layer. A first impurity region, a second impurity region, a third impurity region, a fourth impurity region, and a fifth impurity region of a second conductive type are formed in top layer portions of the semiconductor layer. On the first insulating film, a select gate, a first floating gate, and a second floating gate are respectively disposed opposite a region between the first impurity region and the second impurity region, a region between the second impurity region and the third impurity region, and a region between the third impurity region and the fourth impurity region. In the first insulating film, a first tunnel window and a second tunnel window are respectively formed at portions in contact with the first floating gate and the second floating gate.

Abstract: A contact layout structure includes a substrate having at least a first region defined thereon, plural sets of first contact layouts positioned along a predetermined direction in the first region, and a plurality of second contact layouts positioned in the first region. Each set of the first contact layouts further comprises two square contact units and two adjacent rectangle contact units positioned in between the two square contact units. Each of the rectangle contact units comprises two opposite long sides and two opposite short sides, and a length of the long sides is not equal to the a length of the short sides.

Abstract: A semiconductor device includes a plurality of MOS transistors, wherein each of the MOS transistors has a drain region, a pair of source regions sandwiching therebetween the drain region, and a pair of normal gates each overlying a space between the drain region and a corresponding one of the source regions. A plurality of dummy gates are provided each between adjacent two of the MOS transistors. The dummy gate electrodes are maintained at an equi-potential with the adjacent drain regions. MOS transistors include a row of pMOS transistors and nMOS transistors, wherein each of pMOS transistors and a corresponding nMOS transistor configure a CMOS gate, and a plurality of CMOS gates configure a ring oscillator.

Abstract: According to the embodiments, standard cells are arranged in an array in a semiconductor device. In the standard cell, a first diffusion area with a plurality of transistors formed in a main surface region of a semiconductor substrate is formed in a region sandwiched between two power supply lines arranged on the semiconductor substrate. Further, the standard cell includes a potential supplying unit. The potential supplying unit is formed in the main surface region of the semiconductor substrate by a diffusion layer of the same conductive type as that of the first diffusion area and is electrically connected directly to the diffusion area through a contact from the lower portion of the power supply line, to supply a potential from the power supply line to the first diffusion area.

Abstract: Gate electrodes 5A through 5F are formed to have the same geometry, and protruding parts of the gate electrodes 5A through 5F extend across an isolation region onto impurity diffusion regions. The gate electrode 5B and P-type impurity diffusion regions 7B6 are connected through a shared contact 9A1 to a first-level interconnect M1H, and the gate electrode 5E and N-type impurity diffusion regions 7A6 are connected through a shared contact 9A2 to a first-level interconnect M1I. In this way, contact pad parts of the gate electrodes 5A through 5F can be located apart from active regions of a substrate for MOS transistors. This suppresses the influence of the increased gate length due to hammerhead and gate flaring. As a result, transistors TrA through TrF can have substantially the same finished gate length.

Abstract: An integrated circuit includes a bulk technology integrated circuit (bulk IC) including a bulk silicon layer and complementary MOSFET (CMOS) transistors fabricated thereon. The integrated circuit also includes a single transistor dynamic random access memory (1T DRAM) cell arranged adjacent to and integrated with the bulk IC.

Abstract: Embodiments of an integrated circuit are provided. In one embodiment, the integrated circuit includes a substrate and a plurality of locally interconnected multi-gate transistors. The plurality of locally interconnected multi-gate transistors includes a continuous fin structure formed on the substrate and first and second multi-gate transistors formed on the substrate and including first and second fin segments of the continuous fin structure, respectively. The continuous fin structure electrically interconnects the first and second multi-gate transistors.

Abstract: A semiconductor integrated circuit includes multiple cells each containing transistors. The transistors include a gate and diffusion layers. The multiple cells are adjacently formed in a first direction perpendicular to the gate. The distance between the cell border and the adjacent and corresponding diffusion layer, the first direction, is the same.

Abstract: The present invention provides a method of inducing stress in a semiconductor device substrate by applying an ion implantation to a gate region before a source/drain annealing process. The source/drain region may then be annealed along with the gate which will cause the gate to expand in certain areas due to said ion implantation. As a result, stress caused by said expansion of the gate is transferred to the channel region in the semiconductor substrate.

Abstract: An integrated circuit has a power rail formed of a first wire in a lower metal layer and a second wire in an upper metal layer and that run in the same direction in their respective layers. A number of vias connect the first and second wires, to form a sandwich power rail structure. Other embodiments are also described and claimed.

Abstract: An array substrate includes first and second gate electrodes on a substrate; a gate insulating layer on the first and second gate electrodes; first and second active layers on the gate insulating layer; an interlayer insulating layer on the first and second active layers; first to fourth ohmic contact layers respectively contacting both sides of the first active layer and both sides of the second active layer; first and second source electrodes and first and second drain electrodes respectively on the first, third, second and fourth ohmic contact layers; a data line connected to the first source electrode; a first passivation layer connected to the first gate electrode; a power line; one end and the other end of a connection electrode respectively connected to the first drain electrode and the second gate electrode; a second passivation layer; and a pixel electrode-connected to the second drain electrode.

Abstract: A semiconductor device having a first semiconductor region and second semiconductor region including impurities formed on an insulating layer formed on a semiconductor substrate, an insulator formed between the first semiconductor region and the second semiconductor region, a first impurity diffusion control film formed on the first semiconductor region and a second impurity diffusion control film formed on the second semiconductor region, a channel layer formed on the first impurity diffusion control film and second impurity diffusion film to cross at right angles with a direction where the first semiconductor region and the second semiconductor region are extended, a gate insulating film formed on the channel layer and a gate electrode formed on the gate insulating layer.

Abstract: An electrical device includes a substrate; first and second active areas; first and second word lines disposed in a first plane; first and second bit lines in a second plane and in electrical communication with first and second active areas; and a reference line disposed in a third plane. A nanotube element disposed in a fourth plane is in electrical communication with first and second active areas and the reference line via electrical connections at a first surface of the nanotube element. The nanotube element includes first and second regions having resistance states that are independently adjustable in response to electrical stimuli, wherein the first and second regions nonvolatilely retain the resistance states. Arrays of such electrical devices can be formed as nonvolatile memory devices. Methods for fabricating such devices are also disclosed.

Abstract: A solid-state imaging device comprises a pixel array including a plurality of pixels arranged in rows and columns, and a readout unit operable to read out pixel signals of the pixels included in the pixel array row by row. The readout unit (i) reads out pixel signals of a row of pixels in column order of the pixel array during a horizontal readout period, except during a readout-standby period that is within the horizontal readout period, and (ii) suspends reading out the pixel signals of the row of pixels in the column order during the readout-standby period.

Abstract: A semiconductor substrate includes semi-insulating portions beneath openings in a patterned hardmask film formed over a semiconductor substructure to a thickness sufficient to prevent charged particles from passing through the hardmask. The semi-insulating portions include charged particles and may extend deep into the semiconductor substrate and electrically insulate devices formed on opposed sides of the semi-insulating portions. The charged particles may advantageously be protons and further substrate portions covered by the patterned hardmask film are substantially free of the charged particles.

Abstract: A gate electrode of one of an nFET and a pFET includes a metal-containing layer in contact with a gate insulating film and a first silicon-containing layer formed on the metal-containing layer, and a gate electrode of the other FET includes a second silicon-containing layer in contact with a gate insulating film and a third silicon-containing layer formed on the second silicon-containing layer. The first silicon-containing layer and the third silicon-containing layer are formed by the same silicon-containing material film.

Abstract: A semiconductor device includes: a p-channel MIS transistor including: a first insulating layer formed on a semiconductor region between a source region and a drain region, and containing at least silicon and oxygen; a second insulating layer formed on the first insulating layer, and containing hafnium, silicon, oxygen, and nitrogen, and a first gate electrode formed on the second insulating layer. The first and second insulating layers have a first and second region respectively. The first and second regions are in a 0.3 nm range in the film thickness direction from an interface between the first insulating layer and the second insulating layer. Each of the first and second regions include aluminum atoms with a concentration of 1×1020 cm?3 or more to 1×1022 cm?3 or less.

Abstract: A process is disclosed of forming metal replacement gates for PMOS transistors with oxygen in the metal gates such that the PMOS gates have effective work functions above 4.85. Metal work function layers in the PMOS gates are oxidized at low temperature to increase their effective work functions to the desired PMOS range. Hydrogen may also be incorporated at an interface between the metal gates and underlying gate dielectrics. Materials for the metal work function layers and processes for the low temperature oxidation are disclosed.

Abstract: A layout of a semiconductor device is capable of reliably reducing a variation in gate length due to the optical proximity effect, and enables flexible layout design to be implemented. Gate patterns (G1, G2, G3) of a cell (C1) are arranged at the same pitch, and terminal ends (e1, e2, e3) of the gate patterns are located at the same position in the Y direction, and have the same width in the X direction. A gate pattern (G4) of a cell (C2) has protruding portions (4b) protruding toward the cell (C1) in the Y direction, and the protruding portions (4b) form opposing terminal ends (eo1, eo2, eo3). The opposing terminal ends (eo1, eo2, eo3) are arranged at the same pitch as the gate patterns (G1, G2, G3), are located at the same position in the Y direction, and have the same width in the X direction.

Abstract: A semiconductor power device supported on a semiconductor substrate that includes a plurality of transistor cells, each cell has a source and a drain region disposed on opposite sides of a gate region in the semiconductor substrate. A gate electrode is formed as an electrode layer on top of the gate region for controlling an electric current transmitted between the source and the drain regions. The gate electrode layer disposed on top of the semiconductor substrate is patterned into a wave-like shaped stripes for substantially increasing an electric current conduction area between the source and drain regions across the gate.

Abstract: An integrated circuit biases the substrate and well using voltages other than those used for power and ground. Tap cells inside the standard cell circuits are removed. New tap cells used to bias the substrate and well reside outside the standard cell circuits. The location of the new voltage power rails is designated prior to placement of the tap cells in the integrated circuit. The tap cells are then strategically placed near the power rails such that metal connections are minimized. Circuit density is thus not adversely impacted by the addition of the new power rails. Transistors are also placed inside the tap cells to address electrostatic discharge issues during fabrication.