Abstract: A semiconductor integrated circuit device comprising a logical circuit including a MIS transistor formed on a semiconductor substrate, a control circuit for controlling a threshold voltage of the MIS transistor forming the logical circuit, an oscillation circuit including a MIS transistor formed on the semiconductor substrate, the oscillation circuit being constructed so that the frequency of an oscillation output thereof can be made variable, and a buffer circuit, in which the control circuit is supplied with a clock signal having a predetermined frequency and the oscillation output of the oscillation circuit so that the control circuit compares the frequency of the oscillation output and the frequency of the clock signal to output a first control signal, the oscillation circuit is controlled by the first control signal so that the frequency of the oscillation output corresponds to the frequency of the clock signal, the control of the frequency of the oscillation output being performed in such a manner that

Abstract: A first electrode layer composed of Pt is formed on an operating layer, and a second electrode layer composed of a material which is different from Pt is formed on the operating layer so as to cover the first electrode layer. A buried electrode layer composed of Pt is formed in the operating layer under the first electrode layer. The first electrode layer, the second electrode layer and the buried electrode layer constitute a gate electrode.

Abstract: In each of basic cells (BC) arranged in array in an SOI layer, PMOS and NMOS transistors are symmetrically formed. Body regions (11) and (12) are formed to divide source/drain layers (1) and (2), respectively, and gate electrodes (3) and (4) are formed on the body regions (11) and (12) respectively to sandwich gate insulating films therebetween. The gate electrodes (3) and (4) are connected at their both ends to gate contact regions (5) to (8), respectively, and the body regions (11) and (12) are connected at their one ends to body contact regions (9) and (10), respectively. The body contact regions (9) and (10) are so arranged as to sandwich the gate contact regions (5) and (7) together with the gate electrodes (3) and (4), respectively. Being of a SOI type, the device achieves high-speed operation and low power consumption.

Abstract: A repeating cell structure in a semiconductor substrate for a BiCMOS logic gate array. The cell structure has three regions shaped as columns. The first columnar region is a P-well and has four vertically aligned active areas of N-type material formed within the columnar region. Each of the active areas has two gate electrodes to form two NMOS transistors. Similarly the second columnar region is a N-well and has four vertically aligned active areas of P-type material. Each such active region forms two PMOS transistors. The third column has two bipolar transistors, each with collector, base and emitter regions vertically aligned. The resulting BiCMOS logic array permits a flexible location of macrocells, which results in a compact implementation of the resulting integrated circuit.

Abstract: In a semiconductor integrated circuit device having a functional cell in which devices constituting a logic circuit of a current mode logic (CML) type are arranged, an input signal and an output signal are complementary signals to each other, and the functional cell is formed into a cross shape so that the devices are arranged so as to be symmetrical in rotation at every 90.degree. for a center point.

Abstract: A square measure of a basic cell and a basic circuit cell of a semiconductor device used a SOI.cndot.CMOS technology is reduced. In the semiconductor device used a SOI.cndot.CMOS technology, the basic cells constituted by two pieces of PMOS and two pieces of NMOS are arranged in order of the PMOS, the PMOS, the NMOS and NMOS or NMOS, the NMOS, the PMOS and the PMOS in a row, and the diffused layer of a portion on which the PMOS and the NMOS adjoin are formed in a manner to adjoin directly. Moreover, the power source wiring and the grounding wiring are arranged around the basic cell in a manner to being held in common with the adjacent cells, and at least one of PMOS diffused layers is arranged so as to be able to be connected with a power source wiring through a contact directly and at least one of NMOS diffused layers is arranged so as to be able to be connected with a grounding wiring through a contact directly.

Abstract: When constructing a number of transistors in transistor forming region (1) on a semiconductor substrate, a plurality of specific functional regions and a plurality of general-purpose functional regions are formed in the transistor forming region (1) in such a way that each of the plurality of specific functional regions alternates with each of the plurality of general-purpose functional regions. Each of the plurality of general-purpose functional regions is comprised of at least one general-purpose functional bank (4) including a row of P-channel field-effect transistors and a row of N-channel field-effect transistors. Each of the plurality of specific functional regions is comprised of at least one specific functional bank (5) including a row of functional blocks (6) each of which can perform a specific function.

Abstract: A semiconductor integrated circuit is disclosed which avoids operating speed degradation resulting from an increase of the gate resistance due to making the size of the device small. In a basic cell 103 comprising a group 101 of P-channel MOS transistors and a group 102 of N-channel MOS transistors, the gate width of all the MOS transistors constituting the basic cell 103 is set below 7 .mu.m, and the gate electrodes 108a, 108b, 109a, 109b are formed to surround the perimeter of source or drain diffusion areas 106a, 106c, 107a, 107c of the MOS transistors to form an electrically closed loop.

Abstract: A semiconductor device capable of solving a problem of a conventional semiconductor device in that a high density integration cannot be expected because each cell, which includes a pair of N and P wells disposed adjacently, requires a countermeasure against latchup individually. The high density integration prevents an effective countermeasure against latchup. The present semiconductor device arranges two cells, which are adjacent in the direction of an alignment of the N wells and P wells, in opposite directions so that two P wells (or two N wells) of the two adjacent cells are disposed successively, and includes an isolation layer extending across the two adjacent cells to enclose the two successively disposed P wells, thereby isolating the two P wells collectively from the substrate.

Abstract: A layout pattern of a memory cell circuit has a plurality of basic cells. Each basic cell has a small aspect ratio. Each basic cell has a NMOS transistor and a PMOS transistor. In the layout pattern, one basic cell is arranged in each row direction and the sixteen basic cells are arranged in each column direction.

Abstract: A semiconductor dynamic random access memory device includes plural memory cell arrays arranged in two columns, and the memory cell arrays of one column has memory cell sub-arrays and peripheral circuits such as sense amplifiers and sub-word line drivers arranged around the memory cell sub-arrays; the memory cells of the sub-arrays are arranged in a first pattern, and the peripheral circuits of adjacent sub-arrays are arranged in symmetry with respect to a line of symmetry perpendicular to the direction of the columns so as to increase a margin of alignment without sacrifice of simplicity of design work.

Abstract: A semiconductor integrated circuit includes a semiconductor chip; an inner cell region; a plurality of input/output cell regions which are located around the inner cell region, and a plurality of pads which are provided between the plurality of input/output regions and sides of the semiconductor chip. Each unit area of the plurality of input/output cell regions is assigned to a corresponding input/output cell so as to be just sufficient for the corresponding input/output cell.

Abstract: A semiconductor wafer incorporating process control monitors and a method of incorporating the same are provided. In one aspect, the semiconductor wafer has a plurality of fields formed in a pattern thereon that is subdivided into n zones and has a center point. The semiconductor wafer is provided with a plurality of integrated circuits each of which is positioned in one of the plurality of fields. The semiconductor wafer also includes a plurality of diagnostic integrated circuits dispersed in a pattern.

Abstract: A memory device comprising a semiconductor material substrate with a dopant of a first type, a first semiconductor material well with a dopant of a second type formed in the substrate; a second semiconductor material well with a dopant of the first type formed in the first well, an array of memory cells formed within the second well. Each memory cell comprises a first electrode and a second electrode respectively formed by a first and a second doped regions with dopant of the second type formed in the second well, and a control gate electrode.

Abstract: An inverter-type basic cell, with a hexagonal contour, comprises one CMOS device pair arrangement including an n-channel transistor and a p-channel transistor. The inverter-type basic cell has a gate region annularly formed and connected in parallel with the n-channel and p-channel transistors, a sectoral drain diffusion region having a vertex at the center of the annularly-formed gate region, and a source diffusion region that is formed outside of the gate region in such a way as to define a shape having two opposing sides that lie on the prolongation of the two radii of the sectoral drain diffusion region.

Abstract: An arrangement and method for making a gate array architecture locates the well taps at the outer corners of each gate cell. The power buses are also located at the outside of the gate cell as well, enabling sharing of the well taps and the power buses. The location of the well taps at the outside corners of the standard cell reduces the number of transistors in a single repeatable cell from eight transistors to four transistors.

Abstract: In a C-MOS type output circuit, desired connections between a P-MOS transistor and an N-MOS transistor are achieved without forming a third wiring layer.

Abstract: A plurality of macro cell layout regions 9 in cell regions 2 on a semiconductor substrate 1 are divided into three portions in a second direction. Each of the divided portions is provided with basic circuits 14a through 14c. In each basic circuit, a first common line 16 is connected to an output node of a clock input driver 11 via a clock output line 17. A plurality of predrivers 15(1) through 15(n) have their input nodes IN connected to the first common line 16 and have their output nodes OUT connected to a second common line 18. A plurality of main drivers 19(1) through 19mhave their input nodes IN connected to the second common line 18 and have their output nodes OUT connected to a third common line 20. The third common line is connected to a plurality of clock signal supply lines 21(1) through 21(s) commonly provided to the basic circuits 14a through 14c. The clock signal supply lines 21(1) through 21(s) are connected to clock input nodes of internal circuits 22 each requiring a clock signal.

Abstract: On transistors P1, P2, N1 and N2 constituting an NAND gate, interconnection pattern W of metal having high melting point and aluminum interconnection patterns Al1 and Al2 are stacked. A local line LL for connecting transistors P1, P2, N1 and N2 to each other is formed by the interconnection pattern W of metal having high melting point, signal lines SL and SL' for signal input/output between the NAND gate and the outside are formed by aluminum interconnection pattern Al1, and power supply lines VL and VL' for applying power supply potentials Vcc and Vss to the NAND gate are formed by the aluminum interconnection pattern Al2. As compared with the prior art in which the local line LL is formed by the aluminum interconnection pattern Al1, the degree of freedom in layout can be improved and the layout area can be reduced.

Abstract: An IC comprises a tub of a first conductivity type, at least one transistor embedded in the tub, and a first pair of isolating regions defining therebetween a tub-tie region coupled to the tub. The tub-tie region comprises a cap portion of the first conductivity type and an underlying buried pedestal portion of a second conductivity type. At least a top section of the pedestal portion is surrounded by the cap portion so that a conducting path is formed between the cap portion and the tub. In a CMOS IC tub-ties of this design are provided for both NMOS and PMOS transistors. In a preferred embodiment, the cap portion of each tub-tie comprises a relatively heavily doped central section and more lightly doped peripheral sections, both of the same conductivity type.

Abstract: A clock driver circuit is furnished in a centrally located macro cell layout region. The clock driver circuit has a plurality of predrivers and a plurality of main drivers. The input and output nodes of the predrivers are short-circuited by a first and a second common line, and the input and output nodes of the main drivers are short-circuited by the second and a third common line. A plurality of clock driver circuits are formed predetermined distances apart and arranged to intersect the clock driver circuit perpendicularly. Each of the clock driver circuits has a plurality of predrivers and a plurality of main drivers. The input and output nodes of the predrivers are short-circuited by a fourth and a fifth common line, and the input and output nodes of the main drivers are short-circuited by the fifth and a sixth common line. The third and the fourth common lines are interconnected.

Abstract: A transistor gate array includes an active transistor region (50a-50n) of transistor gates all oriented in a single direction. Surrounding the active transistor region on all four sides are input/output regions (52a-52d) each containing a row of input/output transistors. All of the I/O devices on all sides of the array are oriented in the same common direction, which is the same direction as the orientation of the active transistor in the active region. This arrangement allows the use of the benefits of high angle ion implantation with fewer ion implant steps. Where some of the transistors are oriented at right angles to others, as in the prior art, four separate directions of high angle ion implantation are required to avoid degradation of electrical properties. With all transistors, including those of the gate array and those of the input/output devices, all oriented in the same direction, only two directions high angle ion implantation are required.

Abstract: The invention provides an improvement in a cell structure for gate arrays. By using the cell in gate arrays, the design flexibility and the symmetry feature of the gate array can be retained. By providing transistors of different sizes, the design can possess more flexibility and more efficiency. Moreover, a denser chip layout can be completed. Thus, average wire lengths used for interconnections in the chip design may be shorter than previously possible. Also, better utilization of available chip area can be made. Thus, it becomes possible to flexibly and optimally use every area of the chip.

Abstract: A gate array basic cell and circuit layout architecture for efficiently routing power supply traces. A basic cell has one or more transistors PMOS and one or more NMOS formed by diffusion regions and gate regions. A portion of the diffusion region extends outward to a point past the end of the gate region. Basic cells are arranged in rows with each basic cell having its p-type diffusion region extending in a direction opposite the n-type diffusion region. Basic cells are arranged in rows. Power supply traces are placed between rows, across the extended diffusion regions. Adjacent rows are shifted with respect to each other. A power supply trace is shared by adjacent rows of basic cells such that a connection can be made between the power supply trace and the extended diffusion regions without additional routing.

Abstract: There is disclosed a multi-power supply integrated circuit including a first pMOS transistor which is formed in a first n-well and operated at a first supply voltage and a second pMOS transistor which is formed in a second n-well and operated at a second supply voltage being lower than the first supply voltage, wherein the first n-well and the second n-well are placed adjacently to put a boundary line therebetween and also the first supply voltage is supplied to both the first and second n-wells. Because a space between the first and second n-wells is made small, a gate array LSI with a reduced chip area is provided. A common n-well may be formed in place of the first and second n-wells.

Abstract: A gate array is disclosed having a programmable polysilicon layer which serves as both the gate electrodes for MOS transistors and routing lines for some connections between gate electrodes. The gate array structure is formed on a semiconductor substrate and has an array of identical base cells located in a core region of the structure. Each such base cell des the following elements: (1) a plurality of transistors, each of which includes a gate electrode; and (2) one or more gate connection strips formed on the substrate and electrically connecting selected gate electrodes of two or more of the transistors. Preferably, the gate connection strips are made from the same material as the selected gate electrodes (e.g., polysilicon) and are integrally connected therewith. The gate connection strips may patterned (i.e., programmed) to form substrate level routing between gates of various transistors.

Abstract: In a semiconductor integrated circuit including an input-stage input buffer circuit, an input terminal of the input buffer circuit is connected to a gate of an input MOS transistor which has a gate length longer than a gate length specified in the applied design rule. Alternatively, in a gate array system of a semiconductor integrated circuit, a number of gates have a gate length longer than the length specified in an applied design rule. An input transistor of the input buffer circuit has gate with a gate length longer than a gate length specified in the applied design rule.

Abstract: A CMOS cell architecture and routing technique is optimized for three or more interconnect layer cell based integrated circuits such as gate arrays. First and second layer interconnect lines are disposed in parallel and are used as both global interconnect lines and interconnect lines internal to the cells. Third layer interconnect lines extend transverse to the first two layer interconnects and can freely cross over the cells. Non-rectangular diffusion regions, shared gate electrodes, judicious placement of substrate contact regions, and the provision for an additional small transistor for specific applications are among numerous novel layout techniques that yield various embodiments for a highly compact and flexible cell architecture. The overall result is significant reduction in the size of the basic cell, lower power dissipation, reduced wire trace impedances, and reduced noise.

Abstract: Several inventions are disclosed. A cell architecture using hexagonal shaped cells is disclosed. The architecture is not limited to hexagonal shaped cells. Cells may be defined by clusters of two or more hexagons, by triangles, by parallelograms, and by other polygons enabling a variety of cell shapes to be accommodated. Polydirectional non-orthogonal three layer metal routing is disclosed. The architecture may be combined with the tri-directional routing for a particularly advantageous design. In the tri-directional routing arraingement, electrical conductors for interconnecting terminals of microelectronic cells of an integrated circuit preferrably extend in three directions that are angularly displaced from each other by 60.degree.. The conductors that extend in the three directions are preferrably formed in three different layers. A method of minimizing wire length in a semiconductor device is disclosed. A method of minimizing intermetal capacitance in a semiconductor device is disclosed.

Abstract: A microelectronic cell includes a semiconductor substrate, an active area formed in the substrate, a gate formed in the active area, and a first contact formed in the active area. The contact has a width D perpendicular to a reference axis defined in the active area, and is spaced from the reference axis by a minimum spacing E. The gate includes a first section which extends substantially parallel to the reference axis, the first contact being disposed between the first section and said reference axis, the first section being spaced from the first contact by a minimum spacing A; a second section which extends substantially parallel to and is spaced from said reference axis by a minimum spacing C<(A+D+E), the second section being spaced from the first section along said reference axis; and a third section which extends at an angle to the reference axis and joins adjacent ends of the first and second sections.

Abstract: Several inventions are disclosed. A cell architecture using hexagonal shaped cells is disclosed. The architecture is not limited to hexagonal shaped cells. Cells may be defined by clusters of two or more hexagons, by triangles, by parallelograms, and by other polygons enabling a variety of cell shapes to be accommodated. Polydirectional non-orthogonal three layer metal routing is disclosed. The architecture may be combined with the tri-directional routing for a particularly advantageous design. In the tri-directional routing arrangement, electrical conductors for interconnecting terminals of microelectronic cells of an integrated circuit preferrably extend in three directions that are angularly displaced from each other by 60.degree.. The conductors that extend in the three directions are preferrably formed in three different layers. A method of minimizing wire length in a semiconductor device is disclosed. A method of minimizing intermetal capacitance in a semiconductor device is disclosed.

Abstract: The invention concerns integrated circuits in which a MACRO is embedded in a standard cell array. One level of metal is devoted exclusively to non-local interconnect, and a layer of polysilicon is devoted to local interconnect, thereby saving significant space.

Abstract: A semiconductor memory device having a plurality of memory cells each comprising two CMOS inverters cross-coupled to each other and arranged at intersections between a plurality of word lines extending in a column direction and a plurality of complementary data line pairs extending in a row direction; wherein p-channel type load MISFETs of the memory cells arranged in the column direction are formed on the main surface of an n-type well region in the direction in which the word lines extend, the source regions of the p-channel type load MISFETs of the memory cells arranged in the column direction are electrically connected to the n-type well region through conductor layers, and each of the conductor layer is formed independently of the memory cells arranged in the column direction.

Abstract: Herein disclosed is a semiconductor integrated circuit device comprising a SRAM having its memory cell composed of transfer MISFETs to be controlled through word lines and drive MISFETs. The gate electrodes of the drive MISFETs and the gate electrodes of the transfer MISFETs of the memory cell, and the word lines are individually formed of different conductive layers. The drive MISFETs and the transfer MISFETs are individually arranged to cross each other in the gate length direction. The word lines are extended in the gate length direction of the gate electrodes of the drive MISFETs and caused to cross the gate electrodes of the drive MISFETs partially.The two transfer MISFETs of the memory cell have their individual gate electrodes connected with two respective word lines spaced from each other and extended in an identical direction. The region defined by the two word lines is arranged therein with the two drive MISFETs and the source lines.

Abstract: A dynamic random access memory array having an array of memory cells. Individual cells of the array are addressable by a plurality of word lines and a plurality of bit lines. The memory cells are disposed in active areas of the array. The array of memory cells includes a first strip of memory cells. The dynamic random access memory array includes a lower metal layer and an upper metal layer disposed above the lower metal layer. The dynamic random access memory array further includes a dielectric layer disposed between the lower metal layer and the upper metal layer. There is further included a first bit line of the plurality of bit lines which includes a lower metal first bit line portion implemented in the lower metal layer. The lower metal first bit line portion is coupled to a first plurality of memory cells of the first strip of memory cells. The first bit line also includes an upper metal first bit line portion implemented in the upper metal layer.

Abstract: In a static random access memory (SRAM), a memory cell ratio is increased without deteriorating an integration degree of this SRAM. The static random access memory is arranged by: trenches formed in a semiconductor substrate and an insulating layer for isolating elements within a memory cell forming region; one pair of word transistors; one pair of driver transistors for constituting a flip-flop by forming channel regions of the driver transistors in side surfaces of the trenches and by cross-connecting gate electrodes thereof and drain electrodes thereof at one pair of input/output terminals of the flip-flop; and one pair of word transistors connected between the one pair of input/output terminals of the flip-flop and a bit line.

Abstract: A basic cell structure of a gate array that allows wiring in a macro cell is implemented solely by using first layer metallic wires and entails neither performance deterioration nor an increase in sell size. The basic cell of the gate array comprises a pMOS transistor having two FETs connected in series to each other and an nMOS transistor also having two FETs also connected in series to each other. The pMOS transistor and the nMOS transistor are formed on a substrate and arranged in parallel to each other, and gate electrodes corresponding to the FETs are commonly provided for the pMOS transistor and the nMOS transistor. In this structure, a first auxiliary wire is provided between the gate electrodes on the same layer as the gate electrodes. A second auxiliary wire is provided between adjacent basic cells also on the same layer as the gate electrodes. Wiring in a macro cell can be completed by using the first and second auxiliary wires of different types to form a two-dimensional structure.

Abstract: A circuit architecture is disclosed wherein power is supplied to a CMOS circuit through a first pair of voltage rails, including a first voltage rail (12) providing a first voltage and a second voltage rail (14) providing a second voltage, and a second pair of voltage rails, including a third voltage rail (16) providing a third voltage and a fourth voltage rail (18) providing a fourth voltage. Components (20, 22) comprising two circuit portions are connected across either the first or second pair of voltage rails. The voltage difference across each pair of voltage rails is less than the threshold voltage of the groups of component (20, 22) so that very little current is drawn. Because the voltage offset between the first and second pairs of rails is greater than the threshold voltage of the groups of components (20, 22), sufficient voltage is provided for switching.

Abstract: A cell apparatus and method for use in building complex integrated circuit devices. The cell apparatus and method for use in building complex integrated circuits includes a cell which has regions dedicated to specific types of circuit elements and a method for designing the cell. A first region within the cell is dedicated to a first type of circuit element. A second region within the cell is dedicated to a second type of circuit element. A third region is dedicated to one or more diverse types of integrated circuit elements for utilization in multiple diverse applications of integrated circuits. The cell can be utilized in conjunction with multiple cells to efficiently form an image representing a complex integrated circuit device. The cell includes an upper edge and a lower edge, a plane dedicated to a ground line, a plane dedicated to a clock line, and a plane dedicated to a voltage supply line.

Abstract: N type impurity regions are formed at the surface of N well similarly to a DRAM memory cell. Electrode layers corresponding to storage nodes and conductive layers 9a and 9b corresponding to cell plates are formed for predetermined impurity regions among the impurity regions. Conductive layers are isolated from each other electrically in a DC fashion and connected to electrode nodes VA and VB, respectively. The sets of capacitors formed by a predetermined number of memory cell capacitors connected in parallel through the N well are connected in series. As a result, a capacitor with excellent area efficiency which utilizes the characteristics of the memory cell capacitor can be realized.

Abstract: A layout arrangement which provides a contouring of cells that allows the individual rectangular cell boundaries to overlap each other to a point at which individual device edges abut one another thereby utilizing die area which is normally lost to use. In order to attain this result, a new cell contour boundary is described about each cell at the edge of each individual device adjacent the exterior of the cell at a distance at which other cells may abut without disturbing the operation of the cell. Then, computer implemented processes are applied to cause the cells to fit abutting the newly described boundaries.

Abstract: A master slice type gate array has a plurality of block areas. Each block area includes a plurality of basic cells arranged in a matrix. Different block areas have transistors with different channel widths. Within each of the block areas, a plurality of basic cells are connected to one another through a wiring layer to form function cells. First layer wirings for the function cells are completed within an area between rows of power source wirings Vdd and Vss of the first layer in the transverse direction. Contacts for connecting the sources and drains of P- and N-channel type MOS transistors to the first layer wirings are arranged in rows. Even if the channel widths are changed, the position of the contacts for forming the function cells and the wiring pattern remain unchanged for every block. Therefore, the master slice type gate array can be optimized for various performance parameters such as speed, integration, power consumption and other factors.

Abstract: A novel configuration for MOS devices employed in a partially generic gate array type chip having large numbers of generally MOS devices. The MOS devices have a non-rectangular configuration and include at least a first and second region of conductivity type differing from the conductivity type of the gate array substrate that are separated by a channel over which an electrode strip such as a gate is formed. The non-rectangular configuration of the MOS devices provides a space savings that permits the presence of a greater number of devices on a single chip as compared to conventional gate array chips. In accordance with another aspect of the invention one or more patternable busses of conductive material, such as polysilicon, interconnect electrode strips of the MOS devices, such as gates strips, that are made of the same conductive material as the busses.

Abstract: A gate array architecture adapted for serial multiplexer-based circuits. In one embodiment, the gate array contains base cells having functional but isolated serial multiplexer circuits therein. In another embodiment, a base cell contains a single serial multiplexer circuit divisible into varying-sized (size corresponding to the number of inputs) derivative serial multiplexer circuits. In either embodiment, the serial multiplexer circuits within the base cell may be formed from P- and N-channel transistors of varying size. The transistor sizes are chosen to optimize the efficiency of serial multiplexer-based circuits.

Abstract: The gate array (10) has a first doped region (14) in a semiconductor substrate (12) and a plurality of contacts (20-20"', 21-21") arranged in rows and columns to the first doped region (14) organized with contacts of each row offset in a column (25) that is spaced with respect to a columns (28) of adjacent rows at which a contact exists. A plurality of gate conductors (35-42) are arranged to circumnavigate successive contacts (20,21) of adjacent rows on opposite sides in a serpentine patterns, preferably that follow partially circular paths. The contacts (20,21) are substantially circular in cross section, and may be provided with cap (32) on each that may also have a substantially circular cross section. The contacts (20-21) are spaced with a predetermined pitch and the gate conductors (35-42) have a width that defines transistor channels between adjacent contacts. The width of the conductors (35-42) allows the conductors to pass in proximity to the contacts (20-21) with a predetermined spacing.

Abstract: In a gate array having a plurality of free transistors and target transistors, a method and apparatus for protecting a gate electrode of a target transistor from gate charge by employing a free transistor as a gate electrode protection device. A target transistor is a transistor that has been determined to need gate charging protection. A free transistor is a transistor in the gate array which is not used to implement the logic design as embodied in the gate array. Initially, a base array is formed without any metal layers. Then, a determination is made as to which transistors require gate charging protection. The gate electrode of each target transistor determined to require gate charging is coupled to an associated drain or source electrode of a free transistor of the gate array. The gate electrode of the free transistor is connected to an appropriate voltage reference to turn the free transistor off.

Abstract: Several inventions are disclosed. A cell architecture using hexagonal shaped cells is disclosed. The architecture is not limited to hexagonal shaped cells. Cells may be defined by clusters of two or more hexagons, by triangles, by parallelograms, and by other polygons enabling a variety of cell shapes to be accommodated. Polydirectional non-orthogonal three layer metal routing is disclosed. The architecture may be combined with the tri-directional routing for a particularly advantageous design. In the tri-directional routing arraingement, electrical conductors for interconnecting terminals of microelectronic cells of an integrated circuit preferrably extend in three directions that are angularly displaced from each other by 60.degree.. The conductors that extend in the three directions are preferrably formed in three different layers. A method of minimizing wire length in a semiconductor device is disclosed. A method of minimizing intermetal capacitance in a semiconductor device is disclosed.

Abstract: Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel s

Abstract: A gate array architecture adapted for circuits containing transmission gates. In one embodiment, the gate array architecture contains a base row having at least four alternating P- and N-channel transistor rows. The transistor rows are positioned between a first voltage and a second voltage rail. In another embodiment, the rows adjacent the first and second voltage rails have larger transistors to facilitate connection of the transistors as inverters or buffers. The rows more remotely positioned from the first and second voltage rails have smaller transistor sizes to facilitate connection of the transistors as transmission gates. The gate array architecture is particularly efficient when used to create serial multiplexer-based circuits.

Abstract: Integrated circuit SRAM cells include a semiconductor substrate having a field region and first, second, third and fourth active regions therein. The first and second active regions each include a horizontal leg and a vertical leg and are mirror images of each other about a vertical axis. The third and fourth active regions each also include a horizontal leg and a vertical leg and are mirror images of each other about a vertical axis. The integrated circuit SRAM cells also include first and second vertically extending gate conductive layers on the semiconductor substrate. The first vertically extending conductive layer extends vertically over the first active region horizontal leg and extends vertically over the third active region horizontal leg. The second vertically extending conductive layer extends vertically over the second active region horizontal leg and extends vertically over the fourth active region horizontal leg.