Abstract: A function cell capable of shortening the term necessary for circuit designing, a semiconductor device including the function cell, and a semiconductor circuit designing method using the function cell are obtained. The semiconductor device includes first and second function cells that realize the same logic circuit function and have different electrical characteristics from each other. The first function cell includes a first externally connected interconnection. The second function cell includes a second externally connected interconnection. The external shape of the first function cell is almost the same as the external shape of the second function cell. The position of the first externally connected interconnection on the first function cell plane is almost the same as the position of the plane.

Abstract: In the sense amplifier layout method of a semiconductor memory device, a plurality of bit lines and bit bar lines are alternately aligned in parallel. One bit line and one bit bar line form a bit line pair. A plurality of MOS transistors for a sense amplifier extend over a predetermined number of bit line pairs in a longitudinal direction of the bit line pairs. Gates of the MOS transistors are formed over at least a portion the predetermined number of bit line pairs.

Abstract: A cross-coupled transistor pair includes separately arranged first and second active areas. A gate area of a first transistor is arranged symmetrically on portions of the first and second active areas. A gate area of a second transistor is also arranged symmetrically on portions of the first and second active areas. A first signal line extends between drain areas of the first transistor and the gate area of the second transistor. A second signal line extends between drain areas of the second transistor and the gate area of the first transistor. Metal lines can be provided to connect a source voltage, data signal lines, or control signals to common source areas of the first and second transistors. Methods for constructing cross-coupled transistor pairs are also provided.

Abstract: A semiconductor memory device may be formed from a pair of transfer MOS transistors 1, 2 controlled by a word line 11 and a pair of data retaining flip-flop circuit formed from serially connected load elements 5, 6 and drive MOS transistors 3, 4. In the semiconductor memory device, the transfer MOS transistors 1, 2 have a threshold voltage greater than a threshold voltage of the drive MOS transistors 3, 4. The memory device may display an improved &bgr; ratio, and reduce the size of the drive MOS transistors to thereby reduce the cell area.

Abstract: The present invention provides a standard cell which can reduce an effective cell size and improve an integration degree of a semiconductor integrated circuit. The standard cell includes a plurality of MOS transistors formed on a semiconductor substrate. Then, a plurality of standard cells are adjacent to each other in upper, lower, left and right directions, and constitute the semiconductor integrated circuit. The present invention is intended to reduce the effective cell size in such a way that a source region of a MOS transistor connected to a power supply voltage or a ground voltage is shared between cells adjacent to each other. Also, even if the source region is not shared, a source region of one cell in the cells adjacent to each other is arranged in an empty space region of the other cell in such a way that it bestrides between the cells adjacent to each other.

Abstract: In a semiconductor device of MOS structure, the element region has a shape such as a square shape which has a plurality of sides and a plurality of corners. On the element region, a conductive film which constitutes one electrode of the MOS structure is formed. The other electrode of the MOS structure is a silicon substrate. The conductive film is provided so as to cover at least sides adjacent to each other and so as not to cover the corners including the corners which are the contact points (intersecting points) of the adjacent sides. Further, in case the element region is in a ring shape, the conductive film is provided so as to cover none of the corners including the inside corners of the ring-shaped element region. By the above-mentioned structure, the occurrence of breakdown in the insulation film in the MOS structure can be prevented, and the reliability thereof can be enhanced.

Abstract: Briefly, in accordance with one embodiment of the invention, an integrated circuit includes: a gate array architecture. The gate array architecture includes a semiconductor substrate having a plurality of N-type diffusion regions and P-type diffusion regions. The diffusion regions have partially overlying polysilicon landing sites to form N-type and P-type transistors. The regions are relatively sized to form two distinct transistor sizes, smaller N- and P-type transistors and larger N- and P-type transistors.

Abstract: An array-type layout for a silicon on insulator (SOI) transistor. A body contact region of the first conductive type is provided. A polysilicon gate structure is arranged in array over the body contact region. The polysilicon gate structure divides the body contact region into an array of alternating source regions of a second conductive type and drain regions of a second conductive type.

Abstract: A complementary metal-oxide semiconductor (CMOS) device, employing circuit conversion to achieve coexistent multiple voltage levels without body effect. The CMOS device, formed by a typical twin-well process, has a high voltage CMOS, a low voltage CMOS and a circuit converter. The circuit converter raises the operation voltage of the low voltage PMOS in the low voltage CMOS (in the N-type substrate) up to that of the high voltage PMOS in the high voltage CMOS. Alternatively, the circuit converter reduces the operation voltage of the low voltage NMOS in the low voltage CMOS to that of the high voltage NMOS in the high voltage CMOS. Thus, the body effect does not occur to the CMOS device.

Abstract: A sense amplifier for use with a dynamic random access memory is formed in a silicon integrated circuit. The pitch of an array of such sense amplifiers is equal to the pitch of pairs of bit lines of a memory array. Each array of sense amplifiers is formed from four rows of transistors of a given n or p-channel type Metal Oxide Semiconductor (MOS) transistor having a U-shaped gate electrode. The gate electrode of the transistors in each row of transistors of the sense amplifier is offset from those in a previous row by a preselected amount. The bit lines passing through the sense amplifier are straight, with no offsets to affect photolithographic performance, and no protuberances to increase the capacitance of the bit lines. Such an array of sense amplifiers has a size equivalent to the minimum size of the pairs of bit lines, and thus does not cause any increase in the width of the array of memory cells.

Abstract: In a unit cell, a first conductive type active region and a second conductive type active region are provided. Those two active regions extend in a first direction. Each of the active regions have first and second ends thereof. The first end of the second conductive type active region opposes the second end of the first conductive type active region. A conductive pattern is provided to extend in the first direction across the first conductive type active region and the second conductive type active region. A first contact region is arranged adjacent the first end of the first conductive type active region in the first direction. A second contact region is arranged adjacent the second end of the second conductive type active region in the first direction.

Abstract: A semiconductor device having an SRAM section in which a p-well, a first n-well, and a second n-well are formed in a semiconductor substrate. Two n-type access transistors and two n-type driver transistors are formed in the p-well. Two p-type load transistors are formed in the first n-well. The second n-well is located under the p-well and the first n-well and also is connected to the first n-well. The potential of the first n-well is supplied from the second n-well. According to the present invention, the SRAM section can be reduced in size.

Abstract: A read only memory (ROM) device includes a semiconductor substrate having a first type of conductivity, and a plurality of memory cells on the semiconductor substrate. Each memory cell includes first and second regions of a second conductivity type opposite the first conductivity type. A first dielectric layer is on the plurality of memory cells, and a plurality of first contacts extend through the first dielectric layer for contacting the first regions. A second dielectric layer is on the first dielectric layer and the plurality of first contacts. A plurality of second contacts extend through the second dielectric layer and overlie the corresponding second regions.

Abstract: In a semiconductor device of MOS structure, the element region has a shape such as a square shape which has a plurality of sides and a plurality of corners. On the element region, a conductive film which constitutes one electrode of the MOS structure is formed. The other electrode of the MOS structure is a silicon substrate. The conductive film is provided so as to cover at least sides adjacent to each other and so as not to cover the corners including the corners which are the contact points (intersecting points) of the adjacent sides. Further, in case the element region is in a ring shape, the conductive film is provided so as to cover none of the corners including the inside corners of the ring-shaped element region. By the above-mentioned structure, the occurrence of breakdown in the insulation film in the MOS structure can be prevented, and the reliability thereof can be enhanced.

Abstract: A semiconductor device of which input/output cells can be made smaller and consequently of which chip area and hence cost can be reduced in the case where different driving capabilities are required for the output cells. A plurality of transistors is formed in each output cell by forming a plurality of gate electrodes on the semiconductor substrate through a gate-insulating film and by forming a plurality of diffusion regions on both sides of each gate electrode. An endmost impurity-diffusion region is divided into a plurality of divisional diffusion regions in the direction of the gate width, and a plurality of transistors having a gate electrode in common is thereby formed. The gate widths of these transistors, which have a gate electrode in common, are smaller than those of other transistors. Therefore, by using at least one of the transistors having the gate in common, an output driver with low current driving capability can be constituted.

Abstract: A compound semiconductor field effect transistor having, between a gate electrode and a drain electrode, a non-gate region which is the channel region not covered by the gate electrode, wherein a plurality of isolation regions are formed in the non-gate region in such a way that they extend in the direction of channel current and contact with the gate electrode. This compound semiconductor field effect transistor is improved in breakdown voltage between drain and gate and yet retains the high-speed operability of transistor.

Abstract: A switched variable capacitor (20), and binary-weighted array (40) of such capacitors (20), are disclosed. The switched variable capacitor (20) includes a switching transistor (14) connected in series with first and second capacitors (12), between the two terminals (A,B). Bias transistors (18) are provided, and of opposite conductivity type as the switching transistor (14) but with their gates connected to the gate of the switching transistor (14). The bias transistors (18), when on, apply a reverse bias voltage to the source/drain regions of the switching transistor (14), to minimize the parasitic junction capacitance, and thus improve the temperature stability of the capacitor (20). A binary-weighted array (40) of switched variable capacitors (20) is also disclosed, as is a voltage-controlled oscillator (50) incorporating such an array (40).

Abstract: A plurality of first basic cells and a plurality of second basic cells are formed on a semiconductor substrate. A gate electrode of each of transistors in the first basic cell has a gate length of the minimum size. A gate electrode of each of transistors in the second basic cell has a second gate length larger than the first gate length. The transistors in the first basic cell are connected to each other, to construct a circuit which is operable at high speed and can be increased in integration density. The transistors in the second basic cell are connected to each other, to construct a circuit which can be reduced in power consumption and is hardly affected by process variations.

Abstract: A semiconductor memory device including a memory cell block having a plurality of memory transistors formed on a semiconductor substrate. The memory transistors include first and second impurity-diffused regions and a gate formed therebetween. A plurality of memory cells are also included in the memory cell block and have lower electrodes connected to the first impurity-diffused regions, ferroelectric films formed on the lower electrodes and first upper electrodes formed on the ferroelectric films and connected to the second impurity-diffused regions. Further included are block selecting transistors formed on the semiconductor substrate and being connected to one end of memory cell block. Second upper electrodes are also formed adjoined to the block selecting transistors and being disconnected from the first upper electrode of the memory cells.

Abstract: A semiconductor (preferably a CMOS) device having one or more latch-up inhibitor diffusion regions. The latch-up inhibitor regions are adjacent to complementary P-channel and N-channel transistors, and typically function to inhibit or prevent latch-up, without increasing the die size of the device.

Abstract: In a gate array having adjacent lines of PFETs and NFETs along a first axis, some gates of PFETs and/or NFETs extend into the region between wells and along a first (x) axis of the lines of transistors to overlap along the axis, so that an extended gate of an nth transistor, a gate of an (n-1)th non-extended transistor and a gate of an (n−1)th non-extended transistor of the opposite polarity lie along an axis (y) perpendicular to the first axis. In a rectangular layout, the upper right transistor (having an extended gate) is connected to the lower left transistor by a short connection along the y axis.

Abstract: A transistor includes an NPN transistor provided with an N-type emitter, a P-type base, an N-type collector, an emitter diffusion region and a collector compensation diffusion region around the base and the emitter for decreasing a saturation voltage and a parasitic PNP transistor in a region where the NPN transistor is formed, the parasitic PNP transistor operating under saturation of the NPN transistor.

Abstract: A semiconductor apparatus and method for making the semiconductor apparatus are provided. The semiconductor memory device can include functional circuit blocks (100) having a multi-layer wiring structure for providing electrical connections between device elements within functional circuit blocks (100). Multi-layer wiring structure can include a wiring layer (M2) disposed in a M2 wiring layer horizontal track (120) and a M2 wiring layer vertical track (122). M2 wiring layer horizontal track (120) provides electrical connections by using wiring layer (M2) disposed in a horizontal direction and M2 wiring layer vertical track (122) provides electrical connections by using wiring layer (M2) disposed in a vertical direction. A wiring layer (M1) can form electrodes having electrical connections to diffusion regions of the device elements in functional circuit blocks (100). Wiring layer (M1) can have a higher sheet resistance and higher melting point than wiring layer (M2).

Abstract: A semiconductor memory array for improving packaging reliability and device speed is disclosed in the present invention. The semiconductor memory array includes a peripheral device region in a center portion of the array, a plurality of memory mat regions enclosing the peripheral device region, a pad region formed in the peripheral device region, a plurality of array control regions between the memory mat regions, each array control region horizontally adjacent to a memory mat region, and a plurality of main amplifier regions disposed between the memory mat regions and the peripheral device region.

Abstract: In a gate array, a gate length is measured by dividing gate electrodes into groups according to their materials to distinguish between those groups. The shape of a contact pad portion (5) of a gate electrode (4) differs according to the groups. A difference described here appears as shape such as cutouts (6a-6c) or projections (6d-6f), which is distinguishable by a scanning electron microscope, for example.

Abstract: The I/O terminal positions of a pass transistor logic circuit cell are distributed in the cell, an output amplifier is provided on the end part of the cell, the pass transistor circuit is arranged in the direction in which a potential supply line extends, a signal polarity inverting circuit is laid out in the cell and the arrangement of wells is different from the arrangement of a conventional CMOS logic circuit.

Abstract: A semiconductor integrated circuit which is capable of being manufactured with a higher packing density and a small-size structure of standard cells is described. In the semiconductor integrated circuit, substrate regions and source regions are shared by adjacent standard cells as well as common contact regions which are located inward displaced respectively from the centers of the substrate regions.

Abstract: In a gate array, a gate length is measured by dividing gate electrodes into groups according to their materials to distinguish between those groups. The shape of a contact pad portion (5) of a gate electrode (4) differs according to the groups. A difference described here appears as shape such as cutouts (6a-6c) or projections (6d-6f), which is distinguishable by a scanning electron microscope, for example.

Abstract: A semiconductor device includes a substrate, a plurality of active regions on the substrate, the active regions having recessed and elevated types and being alternatively in parallel with the substrate, respectively, and a plurality of first and second field insulating layers at field regions adjacent to the active regions, the first field insulating layer being parallel with the substrate and the second field insulating layer being perpendicular to the substrate.

Abstract: A DRAM semiconductor device is provided which includes a semiconductor substrate, a field insulating film formed on the semiconductor substrate, a plurality of active regions in the semiconductor substrate, each surrounded by the field insulating film, a gate electrode traversing each of the plurality of active regions, a pair of source/drain regions formed in each of the plurality of active regions on both sides of the gate electrode, a plurality of bit lines extending along one direction, each connected to one of the pair of source/drain regions, a plurality of word lines extending along a direction perpendicular to the bit lines, each of the plurality of word lines being connected to the gate electrode, and a plurality of capacitor elements extending over said gate electrode each connected to the other of the pair of source/drain regions, wherein each of the plurality of active regions includes an oblique area formed obliquely relative to the bit and word lines and a parallel area formed in parallel to the

Abstract: A semiconductor memory device improves driving capability of bit select transistors without increasing a memory cell array in size, wherein first and second sub-bit lines are elongated along the direction of a bit line and in the reverse direction and are connected to a main bit line through first and second bit select transistors each being independently controllable and the first and second bit select transistors are disposed in a deviated manner without being adjacent to each other with respect to the direction of the bit line.

Abstract: An integrated circuit having a memory cell array in which the strapping of cell components is accomplished within a memory cell. In one embodiment the strapping 750, 752, 756 is placed between the moats 706,724 of transistors that compose cross-coupled inverters within a static random access memory cell.

Abstract: A semiconductor device includes cell areas laid out along a periphery of the device. A plurality of transistors are formed in each cell area, and are separated into at least three transistor groups arranged in a direction perpendicular to a circumferential direction of the semiconductor device. Each transistor group is connected to a high-potential power supply or a low-potential power supply. The semiconductor device has at least one interconnection line common to both the transistor group connected to the high-potential power supply and the transistor group connected to the low-potential power supply. The interconnection line serves to connect those transistor groups to external pads.

Abstract: A master slice layout technology is provided to improve integration density of a semiconductor integrated circuit such as ASIC. In particular, a plurality of gate basic cells are arranged on a semiconductor chip and then a wiring channel grid having non-uniform pitches is defined on the gate basic cells. If a layout of metal wirings is designed along the wiring channel grid, miniaturizable patterns can be set to smaller values while maintaining line widths of predetermined metal wirings such as power supply wirings at preselected values. Since flexibility for the layout of the metal wiring layers is large, miniaturization of the patterns can be attained even if design rules for basic cell process and wiring process are different.

Abstract: A method of forming a pillar CMOS FET device, especially an inverter, and the device so formed is provided. The method includes forming abutting N wells and P wells in a silicon substrate and then forming N+ and P+ diffusions in the P and N wells respectively. A unitary pillar of the epitaxial silicon is grown on the substrate having a base at the substrate overlying both the N and P wells and preferably extending at least from said N+ diffusion to said P+ diffusion in said substrate. The pillar terminates at a distal end. An N well is formed on the side of the pillar overlying the N well in the substrate and a P well is formed on the side of the distal end of the pillar overlying the P well on the substrate and abuts the N well in the pillar. A P+ diffusion is formed in the N well in the pillar adjacent the distal end and a N+ diffusion is formed in the P well in the pillar adjacent the distal end.

Abstract: In a method of manufacturing a semiconductor device comprising a field-effect transistor and a non-volatile memory element at a surface of a semiconductor body, a first and a second active region of a first conductivity type are defined at the surface of the semiconductor body for the transistor and the memory element, respectively. The surface of the semiconductor body is subsequently coated with a first insulating layer providing a sacrificial gate dielectric of the transistor and a floating gate dielectric of the memory element, which first insulating layer is then covered by a silicon-containing layer providing a sacrificial gate of the transistor and a floating gate of the memory element. After formation of the sacrificial gate and the floating gate, the transistor and the memory element are provided with source and drain zones of a second conductivity type.

Abstract: The present invention comprises first unit cells each including PMOS transistors and NMOS transistors, each transistor having a first threshold voltage, second unit cells each including PMOS transistors and NMOS transistors, each transistor having a second threshold voltage, a unit cell array comprised of the first and second unit cells laid in array form, a power switch disposed around the unit cell array and comprised of the PMOS transistors and NMOS transistors each having the second threshold voltage, and input/output circuits disposed around the unit cell array.

Abstract: A semiconductor memory device provided with a plurality of memory cells each including first transistors having first conductivity type and second transistors having a second conductivity type, each memory cell comprising a first active region where channels of the first transistors are formed and a second active region where channels of the second transistors are formed, the first and second active regions being arranged so that the directions of channel currents of the transistors become parallel to each other in each cell and being separated between adjoining memory cells in a direction perpendicular to the directions of channel current.

Abstract: A method and apparatus configures the data bits of partially defective memory devices in order to construct usable memory chip or module packages that meet the specification of a fully or partially functional package.

Abstract: A composite MOS transistor device for a semiconductor integrated circuit includes at least a pair of MOS transistors, or first and second MOS transistors, placed on the same board. The first and second MOS transistors are made up of first and second groups of equally divided transistors with an equal gate width, respectively. These divided transistors are arranged in parallel to each other in the gate longitudinal direction. The divided transistors of these groups are arranged such that the sum of coordinates of respective gates, measured from a centerline, is equalized between these groups along the gate longitudinal direction. Since the sum of errors of respective gates along the length thereof becomes zero in each group of divided transistors, the current difference between the two MOS transistors can be eliminated.

Abstract: In a gate array, a gate length is measured by dividing gate electrodes into groups according to their materials to distinguish between those groups. The shape of a contact pad portion (5) of a gate electrode (4) differs according to the groups. A difference described here appears as shape such as cutouts (6a-6c) or projections (6d-6f), which is distinguishable by a scanning electron microscope, for example.

Abstract: The gate width of a field effect transistor is increased to a value greater than a size of an active region by forming an inclined portion of a gate electrode. As a result, the current driving capability of a field effect transistor is increased without degrading the integration density. The driving capability of the transistor can be further effectively increased by forming an expanded portion of the active region at a location corresponding to the inclined portion of the gate electrode thereby reducing the resistance of the diffusion layer.

Abstract: A complementary Field Effect Transistor includes a first transistor and a second transistor stacked on the first transistor. The angle between the source/drain pair for the first transistor and the source/drain pair for the second transistor is nonzero and other than 180 degrees (e.g., 90 degrees). In one embodiment, each transistor has its own gate, and the active regions for the transistors are separated and situated between the gates. In another embodiment, the active regions for the transistors share a single channel region. In still another embodiment, the transistors share a single gate. In yet another embodiment, the transistors share both a channel region and a gate.

Abstract: A semiconductor device is comprised of: an element isolating film formed on one major surface of a semiconductor substrate; an element forming region formed on the major surface and surrounded by the element isolating film; a gate electrode formed via a gate insulating film on the element forming region and extended over the element isolating film; first and second impurity regions formed in the element forming region, whose portions exposed from a surface of the semiconductor substrate are made in contact with the element isolating film and are located opposite to each other under the gate electrode; a first insulating film formed near the gate electrode on the first impurity region, and extended over the gate electrode and near an extended portion of the gate electrode within the element isolating film; and a second insulating film formed near the gate electrode on the second impurity region.

Abstract: Method and apparatus are disclosed for a low power, high density cell based array structure that permits implementation of designs having compute/drive cell ratios of N:1. The improved performance is provided in part by relocating the substrate and well taps within the compute cell, and in at least some instances by removing the well tap from the drive cell. Further, an extra routing track may be provided by not sharing source/drain areas of adjacent drive cells.

Abstract: Method and apparatus are disclosed for a low power, high density cell based array structure that permits implementation of designs having compute/drive cell ratios of N:1. The improved performance is provided in part by relocating the substrate and well taps within the compute cell, and in at least some instances by removing the well tap from the drive cell. Further, a extra routing track may be provided by not sharing source/drain areas of adjacent drive cells. Still further, a power mesh may be provided which simplifies routing and improves flexibility.

Abstract: A basic cell has a plurality of transistors that are separated from one another for forming an electronic circuit that has a particular function when the transistors are coupled. The basic cell has at least two transistors. One is different in size and orientation from the other.

Abstract: In order to present a basic cell of a master slice type LSI having a high memory density and a high speed logic circuitry, a basic cell is composed of each pair of the PMOS 1, NMOS 4, PMOS 7, and NMOS 10, and three contact holes--besides the contact holes 17, as the contact holes within the MOS channel width W of each MOS, that are connected to the GND power lines 51 and 53, or the Vcc power lines 50 and 52--are formed in the direction perpendicular to each of the power lines.

Abstract: A specific IC layout structure for the MOSFET having a narrow and short channel, especially when the width and the length of the channel are both as small as 1 micron or less, is disclosed. In the IC layout structure, a mask includes a first mask region for defining a first active region, a second mask region for defining a second active region, and a third mask region for defining a channel region, and the third mask region is connected to the first and the second mask regions, respectively. An angle at an joint between the first mask region and the third mask region and/or an angle at an joint between the second mask region and the third mask region are/is greater than 90 degrees so that there is more space beside the channel region provided for the growth of the field oxide. Thus a 3-D oxidation thinning effect can be prevented and the properties of the MOSFET having a narrow and short channel can be stabilized.

Abstract: A field shield isolated transistor is provided wherein the left-hand edge (E1) of a left-hand contact pad (51a) is positioned a distance (d5) to the right of the left-hand edge (F1) of a left-hand field shield gate electrode (41); the right-hand edge (E2) of the left-hand contact pad (51a) is positioned a distance (d6) to the right of the right-hand edge (F2) of the left-hand field shield gate electrode (41); the left-hand edge (E3) of a right-hand contact pad (52a) is positioned a distance (d7) to the left of the left-hand edge (F3) of a right-hand field shield gate electrode (42); and the right-hand edge (E4) of the right-hand contact pad (52a) is positioned a distance (d8) to the left of the right-hand edge (F4) of the right-hand field shield gate electrode (42).