Abstract: A dual structure is introduced to the transistor in a flip-flop or a data input step controlled by a clock of a semiconductor logic circuit. The dual structure is formed by connecting a transistor with a MOS transistor having a channel of the same conductivity type in series with respect to the line of a source or drain and connecting their gates to each other, or by connecting an inverter with p-MOS transistors, one for VDD side and one for VSS side of the output step. The dual structure prevents single event phenomenon in a semiconductor logic circuit, such as inverter, SRAM and data latch circuit.

Abstract: A folded bit line DRAM device is provided. The folded bit line DRAM device includes an array of memory cells. Each memory cell in the array of memory cells includes a pillar extending outwardly from a semiconductor substrate. Each pillar includes a single crystalline first contact layer and a single crystalline second contact layer separated by an oxide layer. A single crystalline vertical transistor is formed along alternating sides of the pillar within a row of pillars. The single crystalline vertical transistor includes an ultra thin single crystalline vertical first source/drain region coupled to the first contact layer, an ultra thin single crystalline vertical second source/drain region coupled to the second contact layer, and an ultra thin single crystalline vertical body region which opposes the oxide layer and couples the first and the second source/drain regions.

Abstract: In accordance with the present invention, the gate length and the gate insulation film thickness are different between the p-channel MOS field effect transistors serving as the driver gates and the n-channel MOS field effect transistors forming the flip flop. Namely, the p-channel MOS field effect transistors serving as the driver gates have a larger gate length and a smaller gate oxide film thickness than the n-channel MOS field effect transistors forming the flip flop.

Abstract: Disclosed herewith is a semiconductor device improved to prevent withstand voltage defects that might occur in each MOSFET used therein and a system to be designed easily and prevented from withstand voltage defects that might occur in each semiconductor used therein. The system includes the first and second input circuits, each being constituted by MOSFETs manufactured in the same process. The first input circuit receives a voltage of a first signal inputted from a first external terminal and divided by first and second resistor means while the AC component of the input signal is transmitted to the input circuit through a capacitor disposed in parallel to the first resistor means. The second input circuit receives a second input signal inputted from a second external terminal and reduced in signal amplitude so as to become smaller than that of the first input signal.

Abstract: A semiconductor device having an SRAM section in which a p-well, a first n-well, and a second n-well are formed in a semiconductor substrate. Two n-type access transistors and two n-type driver transistors are formed in the p-well. Two p-type load transistors are formed in the first n-well. The second n-well is located under the p-well and the first n-well and also is connected to the first n-well. The potential of the first n-well is supplied from the second n-well. According to the present invention, the SRAM section can be reduced in size.

Abstract: A base cell is configured such that P-type regions 11 to 13 are arrayed in a column direction in an N-type well 10, N-type regions 21 to 23 are arrayed in a column direction in a P-type well 20 next to the N-type well, gate lines 34A and 35B passing above a channel between the P-type regions and further between the N-type regions are formed in a row direction, and well contact regions 16C and 26C are formed in the wells 10 and 20 at outer ends thereof, respectively, while no gate contacts are formed at the outer ends. Power supply lines VDD and VSS connected to the well contact regions are formed in the column direction in a second wiring layer above a first wiring layer.

Abstract: The circuit configuration, in particular a logic or digital circuit, has transistors of different conductivity types. The transistors are disposed in spaced-apart rows. The transistor rows alternate with regard to the conductivity types. The transistors of the rows form groups. A group of the first conductivity type is associated with a group of the second conductivity type in an adjacent row and the associated groups together form a digital functional unit. A first, second, and third transistor row each contain transistor groups with an associated group in a downstream adjacent row (in a given direction) and transistor groups with an associated group in an upstream adjacent row. The second transistor row is formed between the first and third transistor rows and contains a transistor group that is associated with a group of the first row, and a transistor group that is associated with a group of the third row.

Abstract: A semiconductor memory device provided with a plurality of memory cells each including first transistors having first conductivity type and second transistors having a second conductivity type, each memory cell comprising a first active region where channels of the first transistors are formed and a second active region where channels of the second transistors are formed, the first and second active regions being arranged so that the directions of channel currents of the transistors become parallel to each other in each cell and being separated between adjoining memory cells in a direction perpendicular to the directions of channel current.

Abstract: In a semiconductor device, first gate electrodes contributing to transistor operations and second gate electrodes not contributing to the transistor operations each have the same gate length, share the common gate length direction, and are arranged in the same pitch. The first gate electrodes and the second gate electrodes are all made to extend, in the gate width direction, beyond the longest active region width. With such a configuration, it is possible to provide a semiconductor device having a pattern structure that will not cause performance degradation of transistors when designing a semiconductor integrated circuit within a semiconductor device.

Abstract: An SRAM memory cell includes two inverters connected in complement with each other. Each inverter includes one NMOS transistor and one PMOS transistor. The gate of the NMOS transistor in one inverter is connected to the drain of the NMOS transistor in the other inverter and this forms a first node. The drain of the NMOS transistor in one inverter is connected to the gate of the NMOS transistor in the other inverter and this forms a second node. The drain of an another PMOS transistor and the gate of still another PMOS transistor are connected to the first node. The drain of the still another PMOS transistor and the gate of the another PMOS transistor are connected to the second node. The gate capacitance and drain capacitance of these PMOS transistors is appended to the two nodes.

Abstract: A method of making a semiconductor structure, includes annealing a structure in a deuterium-containing atmosphere. The structure includes (i) a substrate, (ii) a gate dielectric on the substrate, (iii) a gate on the gate dielectric, (iv) an etch-stop layer on the gate, and (v) an interlayer dielectric on the etch-stop layer.

Abstract: The present invention describes the use of two semiconductor layers, a thin film (TF) layer and a bulk Si wafer layer, to make high density and high speed merged logic and memory IC chips. The memory cells use three-dimensional (3D) SRAM structures. Two kinds of 3D logic cells are disclosed. 3D form of the differential cascode voltage switch (DCVS) architecture, and a 3D form of the DCVS with pass gate (DCVSPG) logic architecture. A high density “system on chip” architecture is described. The high density is achieved by locating large PMOS transistors in the TF Si layer, and the fast NMOS transistors in a bulk Si wafer layer. A single process sequence to simultaneously make the logic and memory circuits on the IC chip is also described.

Abstract: A voltage generation section, which generates voltages for driving the control gates in a plurality of nonvolatile memory cells, has a booster circuit and a voltage control circuit. The voltage control circuit has a plurality of voltage output terminals, and switches and outputs a plurality of voltages inputted from the booster circuit to a plurality of voltage output terminals in accordance with a selection state of the nonvolatile memory cell. The voltage control circuit pre-drives a control gate line by outputting a maximum voltage among the voltages to all of the voltage output terminals in a pre-drive period. A disconnection state, in which no voltage from the booster circuit is outputted, is set in a period prior to the pre-drive period, and a power supply voltage may be outputted instead of the voltage from the booster circuit.

Abstract: A semiconductor device and method of fabrication are disclosed. The device includes a first trench isolation region having an allowable tiling area and a second trench isolation region having an allowable tiling area, wherein the second trench isolation region is doped differently from the first trench isolation region. First tile structures disposed within first trench isolation region have a first set of design parameters while second tile structures disposed within the second trench isolation region have a second set of design parameters. At least one of the first set of design parameters is different from a corresponding design parameter in the second set of design parameters. The corresponding design parameters may include the density, size, pitch, shape, exclusion distance, minimum width, minimum length, and minimum area. The first trench isolation region may be doped with a first-type dopant and the second trench isolation region may be undoped or doped with an opposite second-type dopant.

Abstract: A cross-coupled transistor pair includes separately arranged first and second active areas. A gate area of a first transistor is arranged symmetrically on portions of the first and second active areas. A gate area of a second transistor is also arranged symmetrically on portions of the first and second active areas. A first signal line extends between drain areas of the first transistor and the gate area of the second transistor. A second signal line extends between drain areas of the second transistor and the gate area of the first transistor. Metal lines can be provided to connect a source voltage, data signal lines, or control signals to common source areas of the first and second transistors. Methods for constructing cross-coupled transistor pairs are also provided.

Abstract: A base cell is configured such that P-type regions 11 to 13 are arrayed in a column direction in an N-type well 10, N-type regions 21 to 23 are arrayed in a column direction in a P-type well 20 next to the N-type well, gate lines 34A and 35B passing above a channel between the P-type regions and further between the N-type regions are formed in a row direction, and well contact regions 16C and 26C are formed in the wells 10 and 20 at outer ends thereof, respectively, while no gate contacts are formed at the outer ends. Power supply lines VDD and VSS connected to the well contact regions are formed in the column direction in a second wiring layer above a first wiring layer.

Abstract: A semiconductor device suppressing increase of the number of types of exposure mask for implantations, preventing complication of manufacturing steps and suppressing the manufacturing cost and manufacturing steps therefor are provided. An impurity implantation region (R81) is formed by first implantation with an exposure mask for implantation having an opening at the lower right and this exposure mask for implantation is turned over for forming another impurity implantation region (R82) by second implantation, thereby forming three types of impurity implantation regions including the impurity implantation region (R81) formed through the first implantation, the impurity implantation region (R82) formed through the second implantation and still another impurity implantation region (R83) formed through the first implantation and the second implantation. Four types of regions inclusive of a region (R84) not subjected to impurity implantation can be formed with a single type of exposure mask for implantation.

Abstract: A method and apparatus for a driver layout is described. The layout includes an first number of gate lines arranged along a first axis and a second equal number of gates arranged along a second axis, such that the first set of gates lines is orthogonal to the second set of gates lines. The layout includes a total of N discrete transistors.

Abstract: A memory array including a bit cell row, a strap cell row, a first power supply line, and a first offset supply line is provided. The bit cell row may include a bit cell that includes a first transistor disposed in a first bit cell body region. The first transistor may include a first active region. The strap cell row may include a strap cell that includes a first strap cell body region. The first strap cell body region may be conductively coupled to the first bit cell body region. The first power supply line may be electrically coupled to the first active region and may provide a first supply voltage potential to the first active region. The first offset supply line may be electrically coupled to the first strap cell body region and may provide a first offset voltage potential to the first bit cell body region via the first strap cell body region. The first supply voltage potential is operable to be different from the first offset voltage potential.

Abstract: According to the disclosed method, the surface of a semiconductor wafer is covered by a protective oxide. The semiconductor wafer is then placed in a CVD reactor at a first temperature. Contaminants and the protective oxide are then removed from the surface of the semiconductor wafer at the first temperature. While contaminants and the protective oxide are being removed by the action of HCl and DCS, any silicon being removed from the surface of the silicon wafer, is being replenished so that there is no net change in the amount of silicon on the surface of the water. After removal of the contaminants and the protective oxide, epitaxial growth is performed on the surface of the semiconductor wafer at the first temperature. A structure comprising an epitaxially grown region can be fabricated according to the disclosed method.

Abstract: The present invention provides a semiconductor device comprising a semiconductor substrate, and transistors formed on the semiconductor substrate, wherein control electrode terminals constituting external electrode terminals of the transistors, and first electrode terminals which transmit output signals, are provided on a main surface of the semiconductor substrate, wherein the control electrode terminals are provided at least one, and a plurality of the first electrode terminals are arranged on one side and a plurality of the first electrode terminals are arranged on the other side with the control electrode terminals being interposed therebetween, wherein a portion including the control electrode terminals and a plurality of the first electrode terminals located on one side of the control electrode terminals constitute a first transistor portion, and wherein a portion including the control electrode terminals and a plurality of the first electrode terminals located on the other side of the control electrode

Abstract: A method for measuring bridge induced by mask layout amendment. Provide a mask with a layout that comprises a conductor line pattern, numerous gate patterns which are connected with conductor line pattern, and numerous contact pattern groups, each contact pattern group has numerous contact patterns and at least surrounds one terminal, which does not contact with conductor line, of one corresponding gate pattern. Then, amend this layout and transfer amended layout into a substrate to form a conductor line, numerous gates and numerous contact groups in and on this substrate. Finally, electrically couple these contact groups with a terminal, then, apply an electrical signal into this conductor line and measure whether the electrical signal appears at this terminal.

Abstract: A method for designing routes for multilevel interconnections in a semiconductor device having at least a field effect transistor having a gate electrode, where the route extends between a diffusion region and the gate electrode. Each interconnection connected to the gate electrode is given an area which does not exceed a predetermined antenna effect reference value by inserting a buffer, such as a logic gate, into the interconnection on the same level as the interconnection.

Abstract: A composite MOS transistor device for a semiconductor integrated circuit includes at least a pair of MOS transistors, or first and second MOS transistors, placed on the same board. The first and second MOS transistors are made up of first and second groups of equally divided transistors with an equal gate width, respectively. These divided transistors are arranged in parallel to each other in the gate longitudinal direction. The divided transistors of these groups are arranged such that the sum of coordinates of respective gates, measured from a centerline, is equalized between these groups along the gate longitudinal direction. Since the sum of errors of respective gates along the length thereof becomes zero in each group of divided transistors, the current difference between the two MOS transistors can be eliminated.

Abstract: An MOS integrated circuit, such as an input-output buffer, exhibits improved resistance to damage from electrostatic discharge (ESD) by balancing the ESD current flow through active and inactive sections of drivers. Better balance of the ESD current flow is achieved by increasing the width and length of nulti-finger channels of semiconductor material defining the gates of the drivers in the active section. Wider, longer gates of the drivers in the active section increase their ability to carry current, thereby resulting in a more symmetrical distribution of ESD current between the active and inactive sections without degrading the IC's normal performance.

Abstract: The present invention provides a double gate transistor and a method for forming the same that facilitates the formation of different transistors having different threshold voltages. The embodiments of the present invention form transistors having different body widths. By forming double gate transistors with different body widths, the preferred embodiment forms double gate transistors that have different threshold voltages, without adding excessive process complexity. The preferred embodiment of the present invention is implemented using a fin type double gated structure. In a fin type structure, the double gates are formed on each side of the body, with the body being disposed horizontally between the gates.

Abstract: A semiconductor integrated circuit having an embedded array wherein basic cells are arranged in a matrix is designed and manufactured (S1); a test is performed on whether an electrical behavior of a prototype of a semiconductor integrated circuit meets required specifications (S2); if meets, a non-use-area pattern in an embedded array area is detected and removed based on layout data of contact holes to get modified pattern (S4); a mask with a modified pattern is prepared (S5); and the mask is substituted for the mask before modification, thereby manufacturing a semiconductor integrated circuits from which a non-use area is removed (S6).

Abstract: A semiconductor integrated circuit is provided with logic circuits having transistors. The semiconductor integrated circuit is also provide with a clock tree including clock drivers which have transistors to distribute a clock signal to the logic circuits. Gate lengths of the transistors provided in the clock drivers are longer than that of the transistors provided in the logic circuits.

Abstract: A semiconductor integrated circuit is capable of filling the need for more memory space through the effective use of an already-designed core block. A block (1) including a CPU, an array (4a) of a plurality of bonding pads, and RAMs (21a, 22a) which are first memories located on the same side of the array (4a) as the block (1) are already designed. The requirement for increased memory capacity can be filled with ease by the addition of RAMs (24a, 25a) which are second memories located on the opposite side of the array (4a) from the block (1). Since the second memories are different in physical configuration from the first memories, it is easy to design a physical configuration to achieve required memory capacity outside a core block (8a) within a single-chip microcomputer (9c).

Abstract: A semiconductor memory device provided with a plurality of memory cells each including first transistors having first conductivity type and second transistors having a second conductivity type, each memory cell comprising a first active region where channels of the first transistors are formed and a second active region where channels of the second transistors are formed, the first and second active regions being arranged so that the directions of channel currents of the transistors become parallel to each other in each cell and being separated between adjoining memory cells in a direction perpendicular to the directions of channel current.

Abstract: In a gate array, a gate length is measured by dividing gate electrodes into groups according to their materials to distinguish between those groups. The shape of a contact pad portion (5) of a gate electrode (4) differs according to the groups. A difference described here appears as shape such as cutouts (6a-6c) or projections (6d-6f), which is distinguishable by a scanning electron microscope, for example.

Abstract: Some advanced integrated circuits are fabricated as silicon-on-insulator structures, which facilitate faster operating speeds, closer component spacing, lower power consumption, and so forth. Unfortunately, current bonded-wafer techniques for making such structures are costly because they waste silicon. Accordingly, one embodiment of the invention provides a smart-bond technique that allows repeated use of a silicon wafer to produce hundreds and potentially thousands of silicon-on-insulator structures, not just one or two as do conventional methods. More precisely, the smart bond technique entails bonding selected first and second regions of a silicon substrate to an insulative substrate and then separating the two substrates to leave silicon protrusions or islands on the insulative substrate. The technique is also suitable to forming three-dimensional integrated circuits, that is, circuits having two or more circuit layers.

Abstract: An embodiment of a memory cell includes a series of four substantially oblong parallel active regions, arranged side-by-side such that the inner active regions of the series include source/drain regions for p-channel transistors, and the outer active regions include source/drain regions for n-channel transistors. Another embodiment of the memory cell includes six transistors having gates substantially parallel to one another, where three of the gates are arranged along a first axis and the other three gates are arranged along a second axis parallel to the first axis. In another embodiment, the memory cell may include substantially oblong active regions arranged substantially in parallel with one another, with substantially oblong local interconnects arranged above and substantially perpendicular to the active regions.

Abstract: A basic cell is disclosed, which is small in area and has sufficient connection flexibility. for achieving a semiconductor integrated circuit with a higher density and a reduced manufacturing cost. In a basic cell, a terminal wire, which is connected to a transistor terminal with a contact, is placed in a first metal wiring layer, and a plurality of terminal wire connection points, which can be connected to a second metal wire through a first via, are provided on the terminal wire. Further, in a semiconductor integrated circuit, a circuit wire in a second metal wiring layer is placed along grid points with a fixed pitch, and is connected to a terminal connection point of a transistor terminal, which is displaced from the grid points, through a terminal wire provided in the first metal wiring layer.

Abstract: In a semiconductor storage device, a line of lower-side backing wiring is provided on a line of gate wiring via an insulation layer, and a line of upper-side backing wiring is provided further on the top layer thereof via another insulation layer. Contacts between the gate wiring and upper-side backing wiring are distributed and arranged on two or more different lines extending in a vertical direction with respect to a direction to which the gate wiring extends, and any contacts adjacent to each other of the contacts are arranged on different lines. The lower-side backing wiring passes through between the adjacent contacts.

Abstract: MOS transistors (TR1, TR2) are arranged closer to a pad (SP) in descending order of current-driving capability. Namely, the MOS transistors (TR1, TR2) are arranged from closer part to the pad (SP) in descending order of value of W/L obtained by dividing a gate width (W) of a gate electrode by a gate length (L) of the same. When a transistor has a large current-driving capability, the value of source-to-drain current is high. For this reason, the MOS transistors are arranged from closer part to the pad for source electrode in descending order of current-driving capability, to thereby reduce the amount of voltage drop in an interconnect line. A current value of the transistor becomes lower as a distance between the pad and the transistor increases. As a result, it is allowed to reduce influence on the transistor characteristics exerted by voltage drop due to interconnection resistance.

Abstract: A semiconductor device having a memory cell including first and second load transistors, first and second driver transistors, and first and second transfer transistors. The semiconductor device includes first and second gate-gate electrode layers, first and second drain-drain wiring layers, and first and second drain-gate wiring layers. The first drain-gate wiring layer and the second drain-gate wiring layer are located in different layers. The first drain-gate wiring layer is located below the first drain-drain wiring layer, and the second drain-gate wiring layer is located in above the first drain-drain wiring layer. This structure provides a semiconductor device that has reduced cell area. The invention also provides a memory system and electronic apparatus that include the above semiconductor device.

Abstract: The gate tunnel leakage current is increased in the up-to-date process, so that it is necessary to reduce the gate tunnel leakage current in the LSI which is driven by a battery for use in a cellular phone and which needs to be in a standby mode at a low leakage current. In a semiconductor integrated circuit device, the ground source electrode lines of logic and memory circuits are kept at a ground potential in an active mode, and are kept at a voltage higher than the ground potential in an unselected standby mode. The gate tunnel leakage current can be reduced without destroying data.

Abstract: An improved cell layout for a C3MOS circuit with inductive broadbanding positions the inductor at a distance from the active region to improve isolation and aligns the edges of the resistor, inductor, and transistor regions near the common edge of adjacent cells to decrease the length of the cell-to-cell interconnect lines.

Abstract: The present invention provides an array of customizable functional cells having high density and high drive capacity. It further provides an architecture that maximizes the width of P-channel transistors in an array of standard cells to compensate for the lower speed operation of P-type devices. More particularly, the invention discloses a digital circuit comprising a plurality of inputs for receiving respective logic signal and circuitry, coupled to the inputs, for passing one of the signals responsive to the order in which a transition is received on each of the inputs.

Abstract: A radio-frequency (RF) integrated circuit is described. In one embodiment, the IC comprises multiple metal layers forming multiple transistors on a non-epitaxial substrate. The transistors are step and mirror symmetric. Also, the RF signal lines are on a top metal layer above all other metal layers and the power and ground planes are on a bottom metal layer below all other metal layers. The top and bottom metal layers are separated by a shield that extends beyond the RF signal lines by a distance that is at least the same distance that the shield is away from the RF lines. Low frequency signals are on signal lines below the top metal layer.

Abstract: A semiconductor memory device which can suppress the occurrence of corner rounding through the resist patterning process to achieve a reduction in cell size and higher integration. A relationship between a channel width DT.W of the drive transistor, a channel length DT.L of the drive transistor, a channel width WT.W of the word transistor and a channel length WT.L of the word transistor is given by: (DT.W/WT.W)/(WT.L/DT.L)<1.2. The channel width DT.W of the drive transistor is equal to the channel width WT.W of the word transistor, to reduce steps in the patterns of p-type active regions. The channel length WT.L of the word transistor is larger than the channel length DT.L of the drive transistor, that is, (WT.L/DT.L)>1.

Abstract: A semiconductor device is provided. The device includes a gate electrode formed over a first conductivity type well. An LDD region is formed on either gate electrode side having a second conductivity type dopant diffusion with a low dopant concentration and a source/drain region with a high dopant concentration. The device includes a contact section connecting one side of the source drain regions having the same potential as the first conductivity type well and disposed so as to contact the LDD region on this side of the source drain. The device also includes a contact section connecting the other side of the source drain regions having a potential different from the first conductivity type well and disposed so as to not come in contact with the LDD region on this side of the source drain.

Abstract: An information processing structure is disclosed that is formed of single electron circuits each operating rapidly and stably by way of a single electron operation. The information processing structure includes a MOSFET (11), and a plurality of quantum dots (13) disposed immediately above a gate electrode (12) of the MOSFET and each of which is made of a microconductor or microsemiconductor of a nanometer scale in size. Between each of the quantum dots and the gate electrode is there formed an energy barrier that an electron is capable of directly tunneling. The total number of such electrons moved between the quantum dots and the gate electrode is used to represent information. In the structure, a power source electrode (14) is disposed in contact with the quantum dots and a pair of information electrodes (15) is disposed across a quantum dot in contact therewith for having electric potentials applied thereto, representing data of information.

Abstract: A highly flexible, heterogeneous architecture for portable, high density, high performance standard cell and gate array applications is disclosed. The architecture is based on the three basic cells and their derivatives, particularly a transmission gate cell, a logic cell, and a drive cell. For gate array implementations, the cells are arranged in a pre-determined regular array format. For standard cell implementations, the arrangement of the cells may be optimized to suit each target logic gate. Optimized transistor sizing is achievable through leaf cells, software sizing, or both.

Abstract: A full CMOS SRAM cell is provided. The SRAM cell includes first and second active regions formed on a semiconductor substrate, arranged parallel to each other. A third active region is formed on the semiconductor substrate between the first active region and the second active region parallel to the first active region, and a fourth active region is formed on the semiconductor substrate between the third active region and the second active region parallel to the second active region. A word line intersects the first and second active regions. A first common conductive electrode intersects the first active region and the third active region, and a second common conductive electrode intersects the second active region and the fourth active region.

Abstract: The I/O terminal positions of a pass transistor logic circuit cell are distributed in the cell, an output amplifier is provided on the end part of the cell, the pass transistor circuit is arranged in the direction in which a potential supply line extends, a signal polarity inverting circuit is laid out in the cell and the arrangement of wells is different from the arrangement of a conventional CMOS logic circuit.

Abstract: A differential circuit to be used as a latch-up for asymmetric-double-gate complementary metal oxide semiconductor (DGCMOS) devices is provided. Specifically, the differential circuit comprises an asymmetric-DGCMOS device having the weak gates tied to input circuitry and strong gates that are used in cross-coupling.

Abstract: A method for forming a gate dielectric having regions with different dielectric constants. A low-K dielectric layer is formed over a semiconductor structure. A dummy dielectric layer is formed over the low-K dielectric layer. The dummy dielectric layer and low-K dielectric layer are patterned to form an opening. The dummy dielectric layer is isontropically etched selectively to the low-K dielectric layer to form a stepped gate opening. A high-K dielectric layer is formed over the dummy dielectric and in the stepped gate opening. A gate electrode is formed on the high-K dielectric layer.

Abstract: A memory cell configuration includes, as a memory cell, a ferroelectric transistor having a first gate intermediate layer and a first gate electrode between source/drain regions at the surface of a semiconductor substrate. The first gate intermediate layer contains at least one ferroelectric layer. Beside the first gate intermediate layer, a second gate intermediate layer and a second gate electrode are disposed between the source/drain regions, the second gate intermediate layer containing a dielectric layer. The first gate electrode and the second gate electrode are connected to one another through a diode structure. Strip-type doped well regions are provided in the semiconductor substrate, which well regions run between the source/drain regions of the respective ferroelectric transistor.