Abstract: First and second impurity doped regions are formed in a semiconductor substrate. A first gate electrode is formed on the first impurity doped region with a first gate insulation film interposed therebetween. A second gate electrode is formed on the second impurity doped region with a second gate insulation film interposed therebetween. A first sidewall insulation film is formed on either side of the first gate electrode. A second sidewall insulation film has a thickness different from that of the first sidewall insulation film and are formed on either side of the second gate electrode. A third sidewall insulation film is formed on the first sidewall insulation film on the side of the first gate electrode. A fourth sidewall insulation films have a thickness different from that of the third sidewall, insulation film and are formed on the second sidewall insulation film on the side of the second gate electrode.

Abstract: A base cell is configured such that P-type regions 11 to 13 are arrayed in a column direction in an N-type well 10, N-type regions 21 to 23 are arrayed in a column direction in a P-type well 20 next to the N-type well, gate lines 34A and 35B passing above a channel between the P-type regions and further between the N-type regions are formed in a row direction, and well contact regions 16C and 26C are formed in the wells 10 and 20 at outer ends thereof, respectively, while no gate contacts are formed at the outer ends. Power supply lines VDD and VSS connected to the well contact regions are formed in the column direction in a second wiring layer above a first wiring layer.

Abstract: Concave portions and convex portions are formed on an insulating layer. First bit lines are arranged on the convex portions. A width of the first bit lines is set to L, and a space between the first bit lines is set to L+2S. Each of the first bit lines is electrically connected to a drain diffusion layer by a contact plug. Second bit lines are arranged in a trench between the first bit lines. A width of the second bit lines is set to L, and a space between the first and second bit lines is equal to a width S of a side wall. Each of the second bit lines is electrically connected to a drain diffusion layer by a contact plug.

Abstract: A semiconductor device layout involving the following: arranging active regions of a plurality of transistors having at least more than one first and second electrodes disposed on a substrate; arranging a plurality of gates of transistors between more than one first and second electrodes of those active regions respectively by positioning at least more than one gates having predetermined width and length at a constant gap on the substrate; and arranging a plurality of dummy gates having predetermined width and length between a plurality of transistors (or between and outside transistors) at the same gap as that of the gates of transistors on the substrate, so that all the gates of transistors are arranged at a constant gap to minimize the variance of process deviations and accordingly reduce the difference of threshold voltage of transistors, thereby increasing reliability of the semiconductor device.

Abstract: A semiconductor memory device having a hierarchical I/O line structure is provided. The semiconductor memory array includes a memory cell array which is divided into a plurality of sub-arrays by sub-word line driver areas and bit line sense amplifier areas; local input/output (I/O) lines which are arranged in the bit line sense amplifier areas; and global I/O lines which are arranged in the sub-word line driver areas, wherein at least one end of each of the local I/O lines is formed in a bit line sense amplifier area. The semiconductor memory device may also have a dummy bit line sense amplifier area capable of dividing local I/O lines in a bit line sense amplifier area, and can reduce the number of sub-word line driver areas such that the chip size can be reduced.

Abstract: In a semiconductor integrated circuit device with a transistor, there are a single diffusion layer and a gate base electrode provided outside of the diffusion layer to extend in a pitch direction. N (N is an odd positive integer) gate electrodes are provided above the diffusion layer in parallel in the pitch direction to extend from the gate base electrode in a height direction orthogonal to the pitch direction to pass through the diffusion layer. Source nodes are provided on the diffusion layer along one of the N gate electrodes on a side outside the N gate electrodes in a direction opposing to the pitch direction as a head gate electrode. Drain nodes are provided on the diffusion layer along another of the N gate electrodes on a side outside the N gate electrodes in the pitch direction as a last gate electrode. The drain nodes are less than the source nodes.

Abstract: A complementary metal-oxide-semiconductor static random access memory cell that is formed by a pair of P-channel multiple-gate field-effect transistors (P-MGFETs), a pair of N-channel multiple-gate field-effect transistors (N-MGFETs), a second pair of N-MGFETs that has a drain respectively connected to a connection linking the respective drain of the N-MGFET of the first pair of N-MGFET to the drain of the P-MGFET of the pair of P-MGFETs; a pair of complementary bit lines, each respectively connected to the source of the N-MGFET of the second pair of N-MGFETS; and a word line connected to the gates of the N-MGFETs of the second pair of N-MGFETs.

Abstract: According to one exemplary embodiment, a semiconductor data array comprises an active segment situated on a substrate. The semiconductor data array can be, for example, a ROM array. The semiconductor data array further comprises a first word line situated over the active segment and a second word line situated substantially parallel to the first word line, where the second word line is not situated over the active segment. The semiconductor data array further comprises a column situated over the active segment, the first word line, and the second word line. The semiconductor data array further comprises a contact situated on the active segment, where the contact couples the active segment to the column, where the contact is separated from the first word line by a first distance and from the second word line by a second distance, and where the first distance is less than the second distance.

Abstract: The present invention is related to an array substrate for use in a liquid crystal display.

Abstract: The semiconductor device of the invention includes transistors for a driver and dummy patterns formed to be adjacent to the end portion of each output bit group constituting a cathode driver, anode drivers and anode drivers.

Abstract: Accurate determination of gate dielectric thickness is required to produce high-reliability and high-performance ultra-thin gate dielectric semiconductor devices. Large area gate dielectric capacitors with ultra-thin gate dielectric layers suffer from high gate leakage, which prevents the accurate measurement of gate dielectric thickness. Accurate measurement of gate dielectric thickness of smaller area gate dielectric capacitors is hindered by the relatively large parasitic capacitance of the smaller area capacitors. The formation of first and second dummy structures on a wafer allow the accurate determination of gate dielectric thickness. First and second dummy structures are formed that are substantially similar to the gate dielectric capacitors except that the first dummy structures are formed without the second electrode of the capacitor and the second dummy structures are formed without the first electrode of the capacitor structure.

Abstract: In a MOS array, current loss at distances further away from the drain and source contacts is compensated for by adjusting the length of the polygate. In an array with drain and source contacts near the middle of the structure, the length of the polygate tapers off along the width of the polygate towards both ends of the polygate.

Abstract: In a semiconductor device in which first and second transistors are configured so as to have the same electric characteristics as each other, a dummy gate is arranged between the first and second transistors in parallel to gates of the first and second transistors, and arrangement of source and drain regions formed on both sides of the gate of the first transistor, and arrangement of source and drain regions formed on both sides of the gate of the second transistor are the same as each other.

Abstract: In an integrated circuit device, element power supply lines connected to a circuit containing a plurality of cells, element ground lines connected thereto, a trunk power supply line connected to each of the element power supply lines, and a trunk ground line connected to each of the element ground lines are provided in a first wiring layer. A branch power supply line connected to the trunk power supply line and a branch ground line connected to the trunk ground line are provided in an upper wiring layer located above the first wiring layer.

Abstract: A standard cell for a plurality of power supplies comprises a first power line and a second power line electrically isolated from the first power line. An N well is arranged in spaced relation with the whole peripheral boundaries of the standard cell. In the case where the standard cells are arranged adjacently to each other in the direction along the power lines or in the direction orthogonal thereto, the N well in the standard cell for a plurality of power supplies is isolated from the N wells of the adjacent standard cells in the direction along the power lines or in the direction orthogonal thereto, as the case may be.

Abstract: The present invention provides a fundamental cell, semiconductor integrated circuit device, wiring method and wiring apparatus for designing a layout of a functional circuit block or a semiconductor integrated circuit device using the fundamental cells, with a higher degree of freedom of wirings. The connection terminals 2 and 3 of the fundamental cell 1 are terminals for supplying the power source voltage VDD and ground potential VSS to the N and P type wells. The terminals may be defined as a contact structure between a metal layer and N and P type well areas, and alternatively defined as stacked VIA structure for multilayered metal wiring layers and N and P type well areas if desired in correspondence with the manufacturing process used for manufacturing the semiconductor integrated circuit device implementing the fundamental cell 1. The fundamental cell 1 has neither the connection terminals 2 and 3, nor the power source voltage VDD and ground potential VSS to those two PMOS and NMOS transistors.

Abstract: The invention provides integrated semiconductor devices that are formed upon an SOI substrate having different crystal orientations that provide optimal performance for a specific device. Specifically, an integrated semiconductor structure including at least an SOI substrate having a top semiconductor layer of a first crystallographic orientation and a semiconductor material of a second crystallographic orientation, wherein the semiconductor material is substantially coplanar and of substantially the same thickness as that of the top semiconductor layer and the first crystallographic orientation is different from the second crystallographic orientation is provided. The SOI substrate is formed by forming an opening into a structure that includes at least a first semiconductor layer and a second semiconductor layer that have different crystal orientations. The opening extends to the first semiconductor layer.

Abstract: Standard cell layout efficiency is improved by utilization of a MOS interconnect that minimizes features and geometries requiring compliance with space intensive design rules. Source diffusion regions of MOS structures have a substantially constant width extension extending toward a substrate pick-up diffusion and shares a common silicidation therewith to effect an ohmic contact thereto.

Abstract: A semiconductor device that enables a test for individual IC chips mounted on an interposer is provided. In the semiconductor device having the interposer on which a first IC chip and a second IC chip are mounted, the first IC chip and the second IC chip are connected to outside the interposer by input wring and output wiring, respectively, and a transistor element serving as a switch is inserted in series into the wiring connecting between the first IC chip and the second IC chip.

Abstract: Memory integrated circuitry includes an array of memory cells formed over a semiconductive substrate and occupying area thereover, at least some memory cells of the array being formed in lines of active area formed within the semiconductive substrate which are continuous between adjacent memory cells. Adjacent memory cells are isolated from one another relative to the continuous active area formed therebetween by a conductive line formed over said continuous active area between said adjacent memory cells. At least some adjacent lines of continuous active area within the array are isolated from one another by LOCOS field oxide formed therebetween. The respective area consumed by individual memory cells is less than 8F2, where “F” is no greater than 0.25 micron.

Abstract: A gate array integrated circuit is provided, which includes first and second voltage supply rails and a row of P-channel type transistors and adjacent N-channel type transistors located between first and second voltage supply rails. Adjacent ones of the P-channel and N-channel transistors have common control terminals. A multiple-bit memory cell is fabricated in the row and includes first and second latches, a read output, a first pass gate coupled between the first latch and the read output, and a second pass gate coupled between the second latch and the read output. The first pass gate includes a first one of the P-channel or N-channel transistors. The second pass gate includes a second one of the same type of the P-channel or N-channel transistors. The first and second same type transistors share a common diffusion region.

Abstract: In a CMOS basic cell used in fabrication of a gate array semiconductor integrated circuit, each of the gate and the diffusion region of a P-channel transistor is in a hooked shape having bent parts respectively bending to the left and right at the upper and lower portions thereof. Similarly, each of the gate and the diffusion region of an N-channel transistor is in a hooked shape having bent parts respectively bending to the left and right at the upper and lower portions thereof. In the case where a semiconductor integrated circuit is fabricated by arranging basic cells having the same structure on the right and left hand sides of this basic cell, the basic cells adjacent to each other are overlapped by portions thereof corresponding to one grid, so that the portions in the hooked shapes can be alternately inlaid with each other. Accordingly, the semiconductor integrated circuit attains a smaller layout area.

Abstract: The object is the present invention is to provide a semiconductor device including a circuit employing two or more field-effect transistor that are desired to have equal characteristics, capable of realizing high reliability and superior transistor characteristics. The transistors which are desired to have equal characteristics are placed in the semiconductor device so as to have the same STI trench width (the width of shallow trench isolation adjacent to an active in which the transistor is formed). By such composition, stress growing in the active due to the shallow trench isolation is equalized among the transistors and thereby the characteristics of the transistors can be equalized.

Abstract: A semiconductor chip has a circuit block, a power supply line and a ground line. A condenser chip in which a noise reduction condenser connected to the circuit block is stacked on the semiconductor chip. Because the condenser chip is stacked on the semiconductor chip, it is not necessary to provide a noise reduction condenser on the semiconductor chip and also not to provide a noise reduction condenser on a substrate on which the semiconductor chip is mounted.

Abstract: A semiconductor integrated circuit device has a plurality of design patterns composed of circuit elements or wires formed on a substrate. The respective finished sizes of the plurality of design patterns have a plurality of minimum size values which differ from one design pattern to another depending on the geometric feature of each of the design patterns.

Abstract: A semiconductor intergrated circuit including p-type active regions and n-type active regions provided on a semiconductor substrate. Gate interconnect lines are arranged in a first predetermined direction on the p-type active regions and the n-type active regions. One of the p-type active regions and the n-type regions is provided with at least one protruding part for holding contact holes. A width along a second predetermined direction of the protruding part is larger than a width along the second direction of a space defined between two adjacent gate interconnect lines on the p-type active regions and the n-type active regions.

Abstract: Well bias circuitry for selectively biasing the voltages of the well areas of an integrated circuit. In one embodiment, the well bias circuitry includes a switching cell located in a row of cells of the integrated circuit for selectively coupling a voltage supply line to a well bias line. The switching cell may include two level shifters, each for providing a voltage to a gate of a coupling transistor to make the coupling transistor non conductive in response to an enable signal. The switching cells may be sequentially coupled such that the coupling transistors of each of the switching cells are not made conductive at the same time so as to reduce inrush current due to changing the well bias from a well bias voltage to a supply voltage. In one example, the switching cells may include delay circuitry for delaying the change in state of the enable signal before being provided to the next switching cell.

Abstract: A metal-oxide-silicon (MOS) device that at least includes a silicon-based substrate, a nanometer scaled oxide layer formed on the silicon-based substrate and a metal layer formed on the oxide layer, is disclosed. The present invention basically uses a nanometer scaled oxide structure that result in a non-uniform tunneling current to enhance light-emitting efficiency. The manufacturing steps of the MOS device according to the present invention are quite similar to those of conventional MOS device, so the MOS device according to the present invention can be integrated with the current silicon-based integrated circuit chip. Further the application fields of the silicon-based chip and material can be extended. The cost of MOS device can be reduced and its practicality can be increased.

Abstract: An integrated circuit including a field effect transistor (FET) is provided in which the gate conducter has an even number of fingers disposed between alternating source and drain regions of a substrate. The fingers are disposed in a pattern over an area of the substrate having a length in a horizontal direction, the area equaling the length multiplied by a width in a vertical direction that is occupied by an odd number of the fingers.

Abstract: A semiconductor integrated circuit is provided, which comprises a first cell comprising a plurality of transistors, a second cell comprising a PMOS transistor section and an NMOS transistor section, the PMOS transistor section comprising a first PMOS transistor and a second PMOS transistor connected to the first PMOS transistor in series, the NMOS transistor section comprising a first NMOS transistor and a second NMOS transistor connected to the first NMOS transistor in series. A predetermined scheme is used to connect between the first cell and the second cell, between the plurality of transistors in the first cell, and between the PMOS transistor section and the NMOS transistor section in the second cell.

Abstract: Disclosed herein are a semiconductor device and a method of manufacturing the same that increases the reliability of these devices as size design limitations decrease. Generally, a first insulating film, and wiring, including conductive film patterns and second insulating film patterns are formed on a substrate. Third insulating film patterns including a silicon-oxide-based material are formed on sidewalls of the wiring, and contact patterns and spacers on the sidewalls thereof for defining contact hole regions are formed on the wiring. The contact holes contact surfaces of the third insulating film patterns and pass through the first insulating film. Thus, the thickness of a second insulating film pattern used in the wiring can be minimized, thereby increasing a gap-fill margin between the wiring. A parasitic capacitance between the wiring can be reduced because silicon oxide spacers with a low dielectric constant are formed on sidewalls of the wiring.

Abstract: A very efficient gate array core cell in which the base core cell consists of a group of 6 PMOS transistors and a group of 6 NMOS transistors. It also includes pre-wiring of 2 of the 6 PMOS transistors, with 2 of the 6 NMOS transistors at polysilicon level or at local interconnect level while leaving the remaining PMOS and NMOS transistors as individual transistors to be interconnected during the functional ASIC metallization process. The core cell also has 2 polysilicon or local interconnect wires embedded in it, which can be used to interconnect transistors for logic function implementation. The core cell defined in this invention is highly flexible and has been analyzed to interconnect all types of logic and memory functions needed for ASIC designs. The layout of the transistors, pre-wiring of the strategic transistors at polysilicon level or at local interconnect level, and embedded polysilicon or local interconnect wires reduce the core cell size significantly.

Abstract: A semiconductor integrated circuit includes cells, cell rows and potential feeders. Each cell includes a partial trunk that is used to constitute a power supply trunk and/or a ground trunk, and that is electrically isolated from the remaining components within the cell. Each cell row includes a plurality of cells placed adjacently, and the power supply trunk and/or ground trunk composed of the partial trunks. The potential feeders selectively connect one of the power supply trunk and ground trunk of any one of the plurality of cell rows to the components within the cells to supply them with the potential of the power supply trunk and/or ground trunk. This enables the components in the adjacent cells to be supplied with different potentials.

Abstract: A MOS device with first and second freestanding semiconductor bodies formed on a substrate. The first freestanding semiconductor body has a first portion thereof disposed at a non-orthogonal, non parallel orientation with respect to a first portion of the second freestanding semiconductor body. These portions of said first and second freestanding semiconductor bodies have respective first and second crystalline orientations. A first gate electrode crosses over at least part of said first portion of said first freestanding semiconductor body at a non-orthogonal angle, as does a second gate electrode over the first portion of the second freestanding semiconductor body.

Abstract: A method for improving performance of a transistor oriented in <110> orientation is described. Contacts on either side of the gate are misaligned with respect to one another. The placement of the contacts changes the stress pattern so that the direction of a large part of the tensile strain is diverted from the direction of the current flow.

Abstract: The present invention provides a dual gate transistor and a method for forming the same that results in improved device performance and density. The present invention uses a double gate design to implement a dual gate transistor. A double gate is a gate which is formed on both sides of the transistor body. The present invention thus provides a transistor with two double gates in series that provide improved current control over traditional dual gate designs. The preferred embodiment of the present invention uses a fin type body with dual double-gates. In a fin type structure, the double gates are formed on each side of a thin fin shaped body, with the body being disposed horizontally between the gates.

Abstract: In the driver for driving display having an anode driver, a cathode driver, and memory portions of a semiconductor device of the invention, anode driver regions connected to the memory portions are laid out equally in the chip, and SRAMs and are arranged equally in the vicinity of each of anode driver regions so that drawing of wiring becomes easy and size of the chip is miniaturized.

Abstract: A semiconductor device comprises two transistors where a gate electrode of one transistor and source or drain of another transistor are located in the same rail. A monolithic three dimensional array contains a plurality of such devices. The transistors in different levels of the array preferably have a different orientation.

Abstract: A memory cell (10) is a so-called CMOS type cell. P-wells (W1P, W2P, W3P) and N-wells (W4N, W5N) are formed in a main surface (5S) of a semiconductor substrate (5), and the wells (W2P, W4N, W1P, W5N, W3P) are aligned in this order. Driver transistors (11DN, 12DN) are formed in the wells (W2P, W3P), respectively. Load transistors (11LP, 12LP) are formed in the wells (W4N, W5N), respectively. Two access transistors (11AN, 12AN) are formed in the single well (W1P). N+-type impurity regions (FN30, FN10) constituting one of storage nodes are provided in different wells, and N+-type impurity regions (FN31, FN11) constituting the other of the storage nodes are also provided in different wells.

Abstract: A semiconductor integrated circuit which is capable of being manufactured with a higher packing density and a small-size structure of standard cells is described. In the semiconductor integrated circuit, substrate regions and source regions are shared by adjacent standard cells as well as common contact regions which are located inward displaced respectively from the centers of the substrate regions.

Abstract: A semiconductor device, such as a power MOSFET, Schottky rectifier or p-n rectifier, has a voltage-sustaining zone (20) between a first (21, 23, 31a) and second (22) device regions adjacent to respective first and second opposite surfaces (11, 12) of a semiconductor body 10. Trenched field-shaping regions (40) including a resistive path (42) extend through the voltage-sustaining zone (20) to the underlying second region (22), so as to enhance the breakdown voltage of the device. The voltage-sustaining zone (20) and the trenched field-shaping regions (40) are present in both the active device area (A) and in the peripheral area (P) of the device. A further resistive path (53) extends across the first surface (11), outwardly over the peripheral area (P). This further resistive path (53) provides a potential divider that is connected to the respective resistive paths (42) of successive underlying trenched field-shaping regions (40) in the peripheral area (P).

Abstract: The present invention introduces several methods for implementing integrated circuits that use gridless non Manhattan routing to connect the integrated circuit components. In one embodiment, the non Manhattan routed integrated circuits are created by creating an initial route and then compacting the design down. In another embodiment, a gridless non Manhattan integrated circuits are implemented by adapting a gridless Manhattan routing system into a gridless non Manhattan routing system by rotating a plane of a tile based maze router.

Abstract: A method for forming a gate dielectric having regions with different dielectric constants. A low-K dielectric layer is formed over a semiconductor structure. A dummy dielectric layer is formed over the low-K dielectric layer. The dummy dielectric layer and low-K dielectric layer are patterned to form an opening. The dummy dielectric layer is isontropically etched selectively to the low-K dielectric layer to form a stepped gate opening. A high-K dielectric layer is formed over the dummy dielectric and in the stepped gate opening. A gate electrode is formed on the high-K dielectric layer.

Abstract: A semiconductor device monitor structure is described which can detect localized defects due to floating-body effects, particularly on SOI device wafers. The monitor structure includes a plurality of cells containing PFET or NFET devices, disposed at a perimeter of the structure which is bordered by an insulating region such as shallow trench isolation (STI). Each cell includes polysilicon gate structures having a characteristic spacing given by a first distance, and a portion extending beyond the perimeter a second distance. The cells are constructed in accordance with progressively varying ground rules, so that the first distance and second distance are non-uniform between cells. The cells may be bit fail mapped for single-cell failures, thereby enabling detection of localized defects due to floating-body effects.

Abstract: A semiconductor integrated circuit which is capable of being manufactured with a higher packing density and a small-size structure of standard cells is described. In the semiconductor integrated circuit, substrate regions and source regions are shared by adjacent standard cells as well as common contact regions which are located inward displaced respectively from the centers of the substrate regions.

Abstract: In a gate array having adjacent lines of PFETs and NFETs along a first axis, some gates of PFETs and/or NFETs extend into the region between wells and along a first (x) axis of the lines of transistors to overlap along the axis, so that an extended gate of an nth transistor, a gate of an (n−1)th non-extended transistor and a gate of an (n−1)th non-extended transistor of the opposite polarity lie along an axis (y) perpendicular to the first axis. In a rectangular layout, the upper right transistor (having an extended gate) is connected to the lower left transistor by a short connection along the y axis.

Abstract: P-type active regions (1) and n-type active regions (2) are provided on a semiconductor substrate (not shown). Three gate interconnect lines (3, 4, 5) are arranged on the p-type active regions (1) and the n-type active regions (2). The p-type active regions (1) are provided with protruding parts for holding therein contact holes (6, 7). The contact holes (6, 7) are each arranged on the side opposite to that facing the n-type active regions (2) (in FIG. 1, on the upper part of the p-type active region (1)). The contact hole (6) in one protruding part is provided between the gate interconnect lines (3) and (4). The contact hole (7) in other protruding part is formed between the gate interconnect lines (4) and (5).

Abstract: Prior known static random access memory (SRAM) cells are required that a diffusion layer be bent into a key-like shape in order to make electrical contact with a substrate with a P-type well region formed therein, which would result in a decrease in asymmetry leading to occurrence of a problem as to the difficulty in micropatterning. To avoid this problem, the P-type well region in which an inverter making up an SRAM cell is formed is subdivided into two portions, which are disposed on the opposite sides of an N-type well region NW1 and are formed so that a diffusion layer forming a transistor has no curvature while causing the layout direction to run in a direction parallel to well boundary lines and bit lines. At intermediate locations of an array, regions for use in supplying power to the substrate are formed in parallel to word lines in such a manner that one regions is provided per group of thirty two memory cell rows or sixty four cell rows.

Abstract: A compact SRAM cell that incorporates refractory metal-silicon-nitrogen resistive elements as its pull-up transistors is described which includes a semi-conducting substrate, a pair of NMOS transfer devices formed vertically on the sidewalls of an etched substrate by a metal conductor providing electrical communication between an n+ region in the substrate and a bitline on top, a pair of pull-down nMOS devices on the substrate connected to ground interconnects, and a pair of vertical high-resistive elements formed of a refractory metal-silicon-nitrogen and function as a load for connecting to Vdd. The invention further describes a method for fabricating such compact SRAM cell.

Abstract: A semiconductor memory device having a plurality of memory cells each comprising two CMOS inverters cross-coupled to each other and arranged at intersections between a plurality of word lines extending in a column direction and a plurality of complementary data line pairs extending in a row direction; wherein p-channel type load MISFETs of the memory cells arranged in the column direction are formed on the main surface of an n-type well region in the direction in which the word lines extend, the source regions of the p-channel type load MISFETs of the memory cells arranged in the column direction are electrically connected to the n-type well region through conductor layers, and each of the conductor layer is formed independently of the memory cells arranged in the column direction.