Abstract: The present invention provides an electronic circuitry system receiving the modulated alternating electric field from a computing device, the electronic circuitry is attached to the body of the user and further the electronic circuitry system communicates with the computing device. The electronic circuitry system includes a first electrode capactively coupled with the modulated alternating electric field, an electronic sub-circuit for receiving and processing the modulated alternating electric field from the first electrode and a second electrode connected to said electronic sub-circuit to float the modulated alternating electric field through the body of the user with respect to the ground. The electronic circuitry further includes a hub device for communicating with said communication unit.

Abstract: Semiconductor devices are provided including an active pillar protruding from a substrate; a first gate electrode and a second gate electrode adjacent to a sidewall of the active pillar and vertically overlapping with each other, the first and second gate electrodes being insulated from each other; a first intergate insulating layer covering a first surface of the first gate electrode; and a second intergate insulating layer covering a second surface, opposite the first surface, of the second gate electrode and spaced apart from the first intergate insulating layer. The first intergate insulating layer and the second intergate insulating layer define an air gap therebetween.

Abstract: A package structure is disclosed, which includes a substrate having a body, a plurality of conductive pads formed on the body and a surface passivation layer formed on the body and having a plurality of openings for exposing the conductive pads; a plurality of conductive vias formed in the openings of the surface passivation layer and electrically connected to the conductive pads; a plurality of circuits formed on the surface passivation layer and electrically connected to the conductive vias, wherein the circuits have a plurality of electrical contacts; at least a pattern portion formed on the surface passivation layer and intersecting with the circuits; and a second passivation layer formed on the surface passivation layer, the circuits and the pattern portion and having a plurality of openings for exposing portions of the electrical contacts of the circuits, thereby strengthening the bonding between the circuits and the passivation layers.

Abstract: A semiconductor device includes a first channel layer, a second channel layer protruding from the first channel layer, a pipe gate including a silicide area surrounding the first channel layer, a tunnel insulating layer surrounding the second channel layer, a data storage layer surrounding the second channel layer with the tunnel insulating layer interposed therebetween, and interlayer insulating layers and conductive patterns which are alternately stacked while surrounding the second channel layer with the data storage layer and the tunnel insulating layer interposed therebetween.

Abstract: A semiconductor device includes a first semiconductor substrate and a second semiconductor substrate laminated with an insulating layer, a first transmission line formed on the first semiconductor substrate, the first transmission line including a signal line and a ground, a second transmission line formed on the second semiconductor substrate, the second transmission line including a signal line and a ground, a first via layer for the signal lines, the first via layer for the signal lines being formed of a conductor layer formed within a via hole, a first via layer for the grounds, the first via layer for the grounds being formed of a conductor layer formed within a via hole, and a second via layer for the grounds, the second via layer for the grounds being formed of a conductor layer formed within a via hole.

Abstract: A semiconductor device includes first and second gate electrode structures and a connection plug. The first gate electrode structure is buried in a semiconductor portion and has array stripes inside a first cell array of transistor cells and a contact stripe outside the first cell array, the contact stripe structurally connected with the array stripes. The second gate electrode structure is buried in the semiconductor portion and has array stripes inside a second cell array of transistor cells. An array isolation region of the semiconductor portion separates the first and second gate electrode structures. The connection plug extends between a first surface of the semiconductor portion and the contact stripe of the first gate electrode structure.

Abstract: A testing apparatus for testing a number of different characteristics of a circuit board includes at least two probes, at least one measuring meter, and a storage device. After a circuit schematic diagram of the circuit board and a circuit wiring diagram of the circuit board have been compared, the location of each electric contact is determined. The probes necessary for testing particular characteristics are connected in turn to the measuring meter. The circuit board is moved to align the electric contacts with the probes, and bring the probes into electrical contact with the electric contacts for testing.

Abstract: A monolithic three dimensional memory device includes a semiconductor substrate having a major surface and a doped well region of a first conductivity type extending substantially parallel to the major surface of the semiconductor substrate, a plurality of NAND memory strings extending substantially perpendicular to the major surface of the semiconductor substrate, and a plurality of substantially pillar-shaped support members extending substantially perpendicular to the major surface of the semiconductor substrate, each support member including an electrically insulating outer material surrounding an electrically conductive core material that extends substantially perpendicular to the major surface of the semiconductor substrate and electrically contacting the doped well region.

Abstract: A three-dimensional (3D) semiconductor device includes first interlayer dielectric layers and word lines that are alternately stacked on a substrate; select lines formed on the first interlayer dielectric layers and the word lines; etch stop patterns formed on the select lines to contact the select lines; channel holes formed to pass through the select lines, the first interlayer dielectric layers, and the word lines; channel layers formed on surfaces of the channel holes; insulating layers formed in the channel holes, the insulating layers having an upper surface that is lower than upper surfaces of the etch stop patterns; impurity-doped layers formed in channel holes on upper surface of the insulating layers; and a second interlayer dielectric layer formed over the etch stop patterns and the impurity-doped layers.

Abstract: The present invention discloses a hexagonal programmable array based on a silicon nanowire field effect transistor and a method for fabricating the same. The array includes a nanowire device, a nanowire device connection region and a gate connection region, wherein, the nanowire device has a cylinder shape, and includes a silicon nanowire channel, a gate dielectric layer, and a gate region, the nanowire channel being surrounded by the gate dielectric layer, and the gate dielectric layer being surrounded by the gate region; the nanowire devices are arranged in a hexagon shape to form programming unit, the nanowire device connection region is a connection node of three nanowire devices and secured to a silicon supporter. The present invention can achieve a complex control logic of interconnections and is suitable for a digital/analog and a mixed-signal circuit having a high integration degree and a high speed.

Abstract: A semiconductor device has 3n, 3n+1, and 3n+2 connector lines that are formed together. The 3n+1 connector line is located between the 3n connector line and the 3n+2 connector line. The first fringe pattern pad is located at the terminus of the 3n connector line and is formed with a wider space than the width of the 3n connector line. The second fringe pattern pad is located at the terminus of the 3n+1 connector line and is formed with a wider width than the width of the 3n+1 connector line. The third fringe pattern pad is located at the terminus of the 3n+2 connector line and is formed with a wider width than the width of the 3n+2 connector line. The second fringe pattern pad is positioned closer to a memory array as compared with the terminus of each connector line with the first and third fringe pattern pads.

Abstract: A system and method for a distributed metal routing is disclosed. An embodiment comprises a metal_0 layer with a metal_1 layer overlying the metal_0 layer. The metal_1 layer comprises separate parallel lines, with lines having different signals being distributed across the metal_1 layer. Such a layout decreases the parasitic resistance within the metal_0 layer as it decreases the distance current travels. Additionally, the distributed layout in metal_1 allows connections to be made to a metal_2 layer without the need for a hammer head connection of vias.

Abstract: A semiconductor device includes a logic circuit and an active element circuit. The logic circuit is provided with semiconductor elements formed in a semiconductor substrate. The active element circuit is provided with transistors formed using semiconductor layers formed over a diffusion insulating film formed above a semiconductor substrate. The active element circuit is controlled by the logic circuit.

Abstract: A multi-field effect transistor (FET) device includes a first FET device arranged on a substrate, the first FET device including a first active region and a second active region, a second FET device arranged on the substrate, the second FET device including a first active region and a second active region, and a first conductive interconnect electrically connecting the first active region of the first FET device to the first active region of the second FET device, the first conductive interconnect having a first cross sectional area proximate to the first active region of the first FET device that is greater than a second cross sectional area proximate to the first active region of the second FET device.

Abstract: A semiconductor structure includes first and second chips assembled to each other. The first chip includes N of first conductive lines, M of second conductive lines disposed on the first conductive lines, N of third conductive lines perpendicularly on the second conductive lines and parallel to the first conductive lines, N of first vias connected to the first conductive lines, M sets of second vias connected to the second conductive lines, and N sets of third vias connected to the third conductive lines. The second and first conductive lines form an overlapping area. The third conductive lines and N sets of the third vias include at least two groups respectively disposed in a first and a third regions of the overlapping area. M sets of second vias include at least two groups respectively disposed in a second region and a fourth region of the overlapping area.

Abstract: There is provided a wiring material including a core layer made of metal and a clad layer made of metal and a fiber in which the core layer is copper or an alloy containing copper and the clad layer is formed of copper or the alloy containing copper and the fiber having a thermal expansion coefficient lower than that of copper, the wiring material having a stacked structure in which at least one surface of the core layer is closely adhered to the clad layer, and the fiber in the clad layer is arranged so as to be parallel to the surface of the core layer.

Abstract: A display apparatus and an organic display apparatus are disclosed. In one aspect, the display apparatus includes a display substrate divided into a display region for displaying an image via a plurality of pixels for emitting light and a non-display region around the display region. It includes a pad unit formed on the non-display region. It also includes a fan-out unit for connecting the display region and the pad unit. It further includes a plurality of line groups sequentially formed, wherein each line group includes a first fan-out line, a second fan-out line insulated from the first fan-out line by a first insulating layer, and a third fan-out line insulated from the second fan-out line by a second insulating layer, and wherein the third fan-out line at least partially overlaps with at least one of the first and second fan-out lines.

Abstract: A 3D phase change memory device can store multiple bits per cell represented by a plurality of non-overlapping ranges of resistance all of which are established by different resistance ranges corresponding to respective amorphous phase thickness of the phase change memory material. An array of access devices can underlie a plurality of conductive layers, separated from each other and from the array of access devices by insulating layers. An array of pillars extending through the plurality of conductive layers contact corresponding access devices. The phase memory material is between the pillars and conductive layers. Circuitry is configured to program data in the memory cells using programming pulses having shapes that depend on the resistance range of the cell before programming and the data values to be stored.

Abstract: A layout of a standard cell is stored on a non-transitory computer-readable medium and includes a first conductive pattern, a second conductive pattern, a plurality of active area patterns and a first central conductive pattern. The plurality of active area patterns is isolated from each other and arranged in a first row and a second row between the first and second conductive patterns. The first row is adjacent the first conductive pattern and includes a first active area pattern and a second active area pattern among the plurality of active area patterns. The second row is adjacent the second conductive pattern and includes a third active area pattern and a fourth active area pattern among the plurality of active area patterns. The first central conductive pattern is arranged between the first and second active area patterns. The first central conductive pattern overlaps the first conductive pattern.

Abstract: A method for manufacturing a semiconductor chip stack device is provided. The method includes forming a first connecting element array on a surface of a first semiconductor chip; forming a second connecting element array on a surface of a second semiconductor chip, the second array comprising more connecting elements than the first array and the pitch of the first array being a multiple of the pitch of the second array; applying the first chip against the second chip; and setting up test signals between the first and second chips to determine the matching between the connecting elements of the first array and the connecting elements of the second array.

Abstract: A 3D semiconductor device includes an electrode structure has electrodes stacked on a substrate, semiconductor patterns penetrating the electrode structure, charge storing patterns interposed between the semiconductor patterns and the electrode structure, and blocking insulating patterns interposed between the charge storing patterns and the electrode structure. Each of the blocking insulating patterns surrounds the semiconductor patterns, and the charge storing patterns are horizontally spaced from each other and configured in such a way as to each be disposed around a respective one of the semiconductor patterns. Also, each of the charge storing patterns includes a plurality of horizontal segments, each interposed between vertically adjacent ones of the electrodes.

Abstract: A semiconductor device includes a logic region disposed in a central region of the semiconductor device, and a peripheral region disposed in an outer region thereof. The logic region includes a line-shaped logic transistor and a box-shaped decoupling capacitor. The peripheral region includes a line-shaped peripheral transistor and a line-shaped peripheral dummy transistor disposed adjacent to the peripheral transistor.

Abstract: A test pattern of a semiconductor device includes a plurality of active regions defined in a semiconductor substrate and arranged in parallel with each other, a plurality of gate patterns formed over the plurality of active regions, a plurality of gate contacts formed over the plurality of gate patterns, first junction contacts formed over respective end portions of odd-numbered active regions among the plurality of active regions, second junction contacts formed over respective end portions of even-numbered active regions among the plurality of active regions, and a contact pad configured to couple the first junction contacts and the plurality of gate contacts.

Abstract: To decrease the burden of digital processing, provided is an AD conversion apparatus comprising a pattern generating section that, for each target bit specified one bit at a time moving downward in the output data, generates a pattern signal having a pulse width or number of pulses corresponding to a weighting of the target bit; an integrating section that integrates the pattern signals according to a judgment value for judging a value of the target bit each time a pattern signal is generated, and outputs a reference signal obtained by accumulating the integrated value of each pattern signal; a comparing section that, each time generation of a pattern signal is finished, compares the input signal to the reference signal; and an output section that outputs the output data to have values corresponding to the comparison results obtained after each generation of a pattern signal corresponding to a bit is finished.

Abstract: An array of vertically stacked tiers of memory cells includes a plurality of horizontally oriented access lines within individual tiers of memory cells and a plurality of horizontally oriented global sense lines elevationally outward of the tiers. A plurality of select transistors is elevationally inward of the tiers. A plurality of pairs of local first and second vertical lines extends through the tiers. The local first vertical line within individual of the pairs is in conductive connection with one of the global sense lines and in conductive connection with one of the two source/drain regions of one of the select transistors. The local second vertical line within individual of the pairs is in conductive connection with another of the two source/drain regions of the one select transistor. Individual of the memory cells include a crossing one of the local second vertical lines and one of the horizontal access lines and programmable material there-between.

Abstract: A method and layout for forming word line decoder devices and other devices having word line decoder cells provides for forming metal interconnect layers using non-DPL photolithography operations and provides for stitching distally disposed transistors using a lower or intermediate metal layer or a subjacent conductive material. The transistors may be disposed in or adjacent longitudinally arranged word line decoder or other cells and the conductive coupling using the metal or conductive material lowers gate resistance between transistors and avoids RC signal delays.

Abstract: According to one embodiment, a resistance change memory includes a first interconnect line extending in a first direction, a second interconnect line extending in a second direction intersecting with the first direction, and a cell unit which is provided at the intersection of the first interconnect line and the second interconnect line and which includes a memory element and a non-ohmic element that are connected in series. The memory element stores data in accordance with a change in a resistance state. The non-ohmic element includes a metal layer, a first semiconductor layer containing a first impurity, and a second semiconductor layer which is provided between the first semiconductor layer and the metal layer and which has an unevenly distributed layer.

Abstract: A three-dimensional semiconductor device comprises active patterns arranged two-dimensionally on a substrate, electrodes arranged three-dimensionally between the active patterns, and memory regions arranged three-dimensionally at intersecting points defined by the active patterns and the electrodes. Each of the active patterns is used as a common current path for an electrical connection to two different memory regions that are formed at the same height from the substrate.

Abstract: A finFET block architecture uses end-to-end finFET blocks. A first set of semiconductor fins having a first conductivity type and a second set of semiconductor fins having a second conductivity type can be aligned end-to-end. An inter-block isolation structure separates the semiconductor fins in the first and second sets. The ends of the fins in the first set are proximal to a first side of the inter-block isolation structure and ends of the fins in the second set are proximal to a second side of the inter-block isolation structure. A patterned gate conductor layer includes a first gate conductor extending across at least one fin in the first set of semiconductor fins, and a second gate conductor extending across at least one fin in the second set of semiconductor fins. The first and second gate conductors are connected by an inter-block conductor.

Abstract: Described is a method for adjusting an operating temperature of MOS power components composed of a plurality of identical individual cells and a component for carrying out the method. As a characteristic feature, the gate electrode network (4) of the active chip region is subdivided into several gate electrode network sectors (B1, B2, B3) which are electrically isolated from one another by means of isolating points and to each of which a different gate voltage is fed via corresponding contacts.

Abstract: A 3D nonvolatile memory has memory elements arranged in a three-dimensional pattern defined by rectangular coordinates having x, y and z-directions and with a plurality of parallel planes stacked in the z-direction over a semiconductor substrate. It has vertical local bit lines and a plurality of staircase word lines. Each staircase word line has a series of alternating segments and risers elongated respectively in the x-direction and z-direction traversing across the plurality of planes in the z-direction with a segment in each plane. Methods of forming a slab of multi-plane memory with staircase word lines include processes with one masking and with two maskings for forming each plane.

Abstract: Disclosed is a method to construct a device that includes a plurality of nanowires (NWs) each having a core and at least one shell. The method includes providing a plurality of radially encoded NWs where each shell contains one of a plurality of different shell materials; and differentiating individual ones of the NWs from one another by selectively removing or not removing shell material within areas to be electrically coupled to individual ones of a plurality of mesowires (MWs). Also disclosed is a nanowire array that contains radially encoded NWs, and a computer program product useful in forming a nanowire array.

Abstract: An integrated circuit, manufactured by a process having a nominal minimum pitch of metal lines, includes a plurality of metal lines and a plurality of standard cells under the plurality of metal lines. The plurality of metal lines extends along a first direction, and the plurality of metal lines are separated, in a second direction perpendicular to the first direction, by integral multiples of the nominal minimum pitch. At least one of the plurality of standard cells has a cell height along the second direction, and the cell height is a non-integral multiple of the nominal minimum pitch.

Abstract: A purpose of the present invention is to provide a preferable separation structure of wells when a photoelectric conversion unit and a part of a peripheral circuit unit or a pixel circuit are separately formed on separate substrates and electrically connected to each other. To this end, a solid-state imaging device includes a plurality of pixels including a photoelectric conversion unit and a amplification transistor configured to amplify a signal generated by the photoelectric conversion unit; a first substrate on which a plurality of the photoelectric conversion units are disposed; and a second substrate on which a plurality of the amplification transistors are disposed. A well of a first conductivity type provided with a source region and a drain region of the amplification transistor is separated from a well, which is disposed adjacent to the well in at least one direction, of the first conductivity type provided with the source region and the drain region of the amplification transistor.

Abstract: A semiconductor device and method of manufacturing a semiconductor device include a plurality of first active regions and a second active region being formed on a substrate. The second active region is formed between two of the first active regions. A plurality of gate structures is formed on respective first active regions. A dummy gate structure is formed on the second active region, and a first voltage is applied to the dummy gate structure.

Abstract: A semiconductor device includes a substrate configured with a plurality of conductive traces. The traces are configured to electrically couple to an integrated circuit (IC) die and at least one of the plurality of conductive traces includes first electrically conductive portions in a first electrically conductive layer of the substrate, second electrically conductive portions in a second electrically conductive layer of the substrate, and first electrically conductive connections between the first electrically conductive portions and the second electrically conductive portions. The first and second electrically conductive portions and the first electrically conductive connections form a continuous path along at least a portion of the at least one of the conductive traces. Time delay of conducting a signal along the at least one of the conductive traces is within a specified amount of time of time delay of conducting a signal along another one of the plurality of conductive traces.

Abstract: There is provided a semiconductor device including: plural bit cells each including the same circuit; plural electrodes supplied with power from outside, wherein each of the respective plural electrodes is mounted above the same circuit within the plural bit cells. Further, there is provided a semiconductor package including: the semiconductor device; a substrate mounted with the semiconductor device; an external input terminal formed on the substrate; an external output terminal formed on the substrate; an input wiring pattern connecting the semiconductor device mounted above the substrate and the external input terminal; an output wiring pattern connecting the semiconductor device mounted above the substrate and the external output terminal; and plural power supply lines, arranged without contact with each other on the same face of the substrate, and connecting the plural electrodes mounted to the semiconductor device to the corresponding electrode from the plural external power input electrodes.

Abstract: A method is provided for fabricating a transistor. The method includes providing a semiconductor substrate; and configuring a channel region along a first direction. The method also includes forming trenches at both sides of the channel region along a second direction; and forming a magnetic material layer in each of the trenches. Further, the method includes magnetizing the magnetic material layers to form a magnetic field in the channel region between adjacent magnetic material layers; and forming source/drain regions at both ends of the channel region along the first direction.

Abstract: An electronic circuit, includes a plurality of electronic devices configured as interconnected to provide one or more circuit functions and at least one interconnect structure that includes a first patterned conductor connected to a terminal of a first electronic device in the electronic circuit. A second patterned conductor is connected to a terminal of a second electronic device in the electronic circuit. A first electrode is connected to a portion of the first patterned conductor, and a second electrode is connected to a portion of the second patterned conductor. A metal oxide region is formed between the first electrode and the second electrode. The metal oxide region provides a reprogrammable switch function between the first patterned conductor and the second patterned conductor by providing a conductivity that is selectively controlled by a direction and an amount of current that passes through the metal oxide region during a switch setting operation for the metal oxide region.

Abstract: Semiconductor devices are described, along with methods and systems that include them. One such device includes a diffusion region in a semiconductor material, a terminal coupled to the diffusion region, and a field plate coupled to the terminal and extending from the terminal over the diffusion region to shield the diffusion region. Additional embodiments are also described.

Abstract: A first wiring (1) has a bending portion (2), a first wiring region (1a) extending from the bending portion (2) in the X direction, and a second wiring region (1b) extending from the bending portion (2) in the Y direction. A via (3) is formed under the wiring (1). The via (3) is formed so as not to overlap with a region of the bending portion (2) in the first wiring region (1a). The length of the via (3) in the X direction (x) is longer than the length thereof in the Y direction (y) and both ends of the via (3) in the Y direction overlap with both ends of the first wiring region (1a) in the Y direction.

Abstract: A 3D stacked multichip module comprises a stack of W IC die. Each die has a patterned conductor layer, including an electrical contact region with electrical conductors and, in some examples, device circuitry over a substrate. The electrical conductors of the stacked die are aligned. Electrical connectors extend into the stack to contact landing pads on the electrical conductors to create a 3D stacked multichip module. The electrical connectors may pass through vertical vias in the electrical contact regions. The landing pads may be arranged in a stair stepped arrangement. The stacked multichip module may be made using a set of N etch masks with 2N-1 being less than W and 2N being greater than or equal to W, with the etch masks alternatingly covering and exposing 2n-1 landing pads for each mask n=1, 2 . . . N.

Abstract: Provided are semiconductor device cells, methods for forming the semiconductor device cells and a layout style for the semiconductor device cells. The device cells may be repetitive cells used throughout an integrated circuit. The layout style utilizes an area at the polysilicon level that is void of polysilicon and which can accommodate conductive leads therein or thereover. The conductive leads are formed of material typically used for contacts or vias and are disposed beneath the first metal interconnect level which couples device cells to one another. The subjacent local conductive leads may form subjacent signal lines allowing for additional power mesh lines to be included within the limited number of metal tracks that can be accommodated within a device cell and in accordance with metal track design spacing rules.

Abstract: A semiconductor device and method of making such device is presented herein. The semiconductor device includes a plurality of memory cells, a plurality of p-n junctions, and a metal trace of a first metal layer. Each of the plurality of memory cells includes a first gate disposed over a first dielectric, a second gate disposed over a second dielectric and adjacent to a sidewall of the first gate, a first doped region in the substrate adjacent to the first gate, and a second doped region in the substrate adjacent to the second gate. The plurality of p-n junctions are electrically isolated from the doped regions of each memory cell. The metal trace extends along a single plane between a via to the second gate of at least one memory cell in the plurality of memory cells, and a via to a p-n junction within the plurality of p-n junctions.

Abstract: To suppress variation of a signal in a semiconductor device. By suppressing the variation, formation of a stripe pattern in displaying an image on a semiconductor device can be suppressed, for example. A distance between two adjacent signal lines which go into a floating state in different periods (G1) is longer than a distance between two adjacent signal lines which go into a floating state in the same period (G0, G2). Consequently, variation in potential of a signal line due to capacitive coupling can be suppressed. For example, in the case where the signal line is a source signal line in an active matrix display device, formation of a stripe pattern in a displayed image can be suppressed.

Abstract: A Gallium Nitride (GaN) series of devices—transistors and diodes are disclosed—that have greatly superior current handling ability per unit area than previously described GaN devices. The improvement is due to improved layout topology. The devices also include a simpler and superior flip chip connection scheme and a means to reduce the thermal resistance. A simplified fabrication process is disclosed and the layout scheme which uses island electrodes rather than finger electrodes is shown to increase the active area density by two to five times that of conventional interdigitated structures. Ultra low on resistance transistors and very low loss diodes can be built using the island topology. Specifically, the present disclosure provides a means to enhance cost/effective performance of all lateral GaN structures.

Abstract: Techniques and mechanisms for providing embedded Input/Output (IO) blocks in a floor plan of a semiconductor device are provided, where the embedded IO blocks constitute partial columns (i.e., they do not extend from the bottom through to the top of the semiconductor device). In some embodiments, the partial column IO banks are skewed away from one another. In some embodiments, the partial column IO banks are located away from the center of the semiconductor device. Techniques and mechanisms for implementing symmetrical package routing using skewed partial column IO banks are also provided.

Abstract: A layout of a semiconductor device is capable of reliably reducing a variation in gate length due to the optical proximity effect, and enables flexible layout design to be implemented. Gate patterns (G1, G2, G3) of a cell (C1) are arranged at the same pitch, and terminal ends (e1, e2, e3) of the gate patterns are located at the same position in the Y direction, and have the same width in the X direction. A gate pattern (G4) of a cell (C2) has protruding portions (4b) protruding toward the cell (C1) in the Y direction, and the protruding portions (4b) form opposing terminal ends (eo1, eo2, eo3). The opposing terminal ends (eo1, eo2, eo3) are arranged at the same pitch as the gate patterns (G1, G2, G3), are located at the same position in the Y direction, and have the same width in the X direction.

Abstract: A semiconductor chip includes a plurality of contact pads, which are arranged in an edge area on a surface of the semiconductor chip. In a semiconductor area of the semiconductor chip, every contact pad of the plurality of contact pads has an associated pad cell provided, which includes at least one of a driver or a receiver and is configured to drive output signals or receive input signals on its associated contact pad, if the driver or receiver is connected to the contact pad. Additionally, for a contact pad which is used as a supply contact pad, the driver or receiver of the associated pad cell is not connected to the contact pad or any other contact pad for driving output signals or receiving input signals on the same.

Abstract: A cell array includes a memory cell region in which memory cells are formed and a peripheral region that is provided around the memory cell region. In the memory cell region, first lines are extended in parallel with a first direction, and the first lines are repeatedly formed at first intervals in a second direction orthogonal to the first direction. In the peripheral region, each of the first lines located at (4n?3)-th (n is a positive integer) and (4n?2)-th positions in the second direction from a predetermined position has a contact connecting portion on one end side in the first direction of the first line. In the peripheral region, each of the first lines located at (4n?1)-th and 4n-th positions in the second direction from the predetermined position has the contact connecting portion on the other end side in the first direction of the first line. The contact connecting portion is formed so as to contact a contact plug extended in a laminating direction.