Abstract: A method includes providing a semiconductor wafer having a plurality of pillar structures extending orthogonally from the semiconductor wafer. An electrically conducting interconnect element is deposited onto at least selected vertical pillar transistors and a non-volatile variable resistive memory cell is deposited onto the electrically conducting interconnect layer to form a vertical transistor memory array.

Abstract: The package includes a substrate, a first chip, a second chip, multiple first bumps and multiple second bumps. The substrate has a first region and a second region. The first region is substantially coplanar with the second region. The first bumps connect the first chip and the second chip. The second bumps connect the first chip and the second region of the substrate, wherein the second chip is over the first region of the substrate. The second bumps have a height greater than that of the first bumps plus the second chip. The substrate does not have an opening accommodating the second chip. The first bumps may be gold bumps or solder bumps. The second bumps may be solder bumps.

Abstract: A memory device includes a number of memory cells and a bit line structure coupled to a group of the memory cells. The bit line structure includes an upper portion having a first width, and a lower portion having a second width, where the first width is less than the second width.

Abstract: According to one embodiment, a switch array includes first and second switches provided in a switch unit. The first switch includes first and second memory cell transistors and a first pass transistor. A second switch includes third and fourth memory cell transistors and a second pass transistor. The first and second memory cell transistor is provided in a first active region. The first pass transistor is provided in a second active region in the substrate. The third and fourth memory cell transistor is provided in the first active region. The second pass transistor is provided in the second active region adjacent to the first pass transistor in the channel length direction. The first and second active regions are adjacent to each other in a channel width direction.

Abstract: This invention prevents a break in a signal wire disposed between wire ends due to attenuation and improves production yields of devices. In a standard cell, a first signal wire extends in a first direction. Second and third signal wires extend in a second direction substantially perpendicular to the first direction and are facing each other across the first signal wire. The second and third signal wires have the widths larger than the width of the first signal wire.

Abstract: A semiconductor device 100 includes: a silicon substrate 102; a first gate 114a including a gate electrode 108 formed on the silicon substrate 102 and sidewalls 112 formed on the sidewalls of the gate electrode 108; a silicide layer 132 formed lateral to the sidewalls 112 of the first gate 114a on a surface of the silicon substrate 102; and a contact 164 which overlaps at least partially in plan view with the first gate 114a and reaches to the silicide layer 132 of the surface of the silicon substrate 102; wherein an insulator film is located between the contact 164 and the gate electrode 108 of the first gate 114a.

Abstract: A layout structure of a MOSFET is provided. The layout structure of the MOSFET includes a plurality of MOSFET cells, a first source/drain metal bus structure and a second source/drain metal bus structure. The first source/drain metal bus structure is electrically connected to first sources/drains of the MOSFET cells, and a width thereof is gradually decreased in a predetermined direction. The second source/drain metal bus structure is electrically connected to second sources/drains of the MOSFET cells, and a width thereof is gradually increased in the predetermined direction.

Abstract: Integrated mask-programmable device, having a plurality of metal levels including a top metal level, a bottom metal level and a first intermediate metal level formed between the top and bottom metal levels, and a plurality of via levels arranged between the bottom and the first intermediate metal levels and between the first intermediate and the top metal levels and connecting each metal level to adjacent metal levels. The plurality of metal levels forms a first, a second and at least a third terminal, the top and bottom metal levels having at least two metal regions, and the first intermediate metal level having at least three metal regions. The first terminal is connected to third terminal or the second terminal is connected to the third terminal by modifying a single metal or via level.

Abstract: Embodiments of the invention include a semiconductor integrated circuit package that includes a substrate which can have an integrated circuit die attached thereto. The package includes a dedicated high-speed ground plane that is electrically isolated from the ground plane used to ground the low speed circuitry of the package.

Abstract: A 3D memory device includes a plurality of ridge-shaped stacks, in the form of multiple strips of conductive material separated by insulating material, arranged as strings which can be coupled through decoding circuits to sense amplifiers. Diodes are connected to the bit line structures at either the string select of common source select ends of the strings. The strips of conductive material have side surfaces on the sides of the ridge-shaped stacks. A plurality of conductive lines arranged as word lines which can be coupled to row decoders, extends orthogonally over the plurality of ridge-shaped stacks. Memory elements lie in a multi-layer array of interface regions at cross-points between side surfaces of the conductive strips on the stacks and the conductive lines.

Abstract: A semiconductor integrated circuit includes a plurality of bonding pads formed along an edge of a semiconductor substrate; a plurality of I/O cells arranged along the edge under the plurality of bonding pads; an upper layer wire mesh including a plurality of upper layer wirings; and a core region formed on the semiconductor substrate. In the semiconductor integrated circuit, the core region has an area larger than an area occupied by the upper layer wire mesh in a plane parallel to a surface of the semiconductor substrate.

Abstract: A semiconductor device includes a semiconductor chip, a first substrate, and a second substrate. The first substrate includes a plurality of wires and a plurality of first electrodes, each first electrode being connected with each wire. The second substrate includes the semiconductor chip that is mounted thereon, and a plurality of second electrodes with, each second electrode being connected with the each first electrode of the first substrate. The widths of the wires of the first substrate are different depending on the lengths of the wires. By changing the widths of the wires depending on their lengths, it is possible to reduce variation in stiffness of the electrodes and vicinities of electrodes, whereby variation in ultrasonic bonding strength can be reduced.

Abstract: An array with cells that have adjacent similar structures that are displaced from each other across a common cell border in a direction that is not perpendicular to the cell border thus avoiding an across cell border design rule violation between the adjacent similar structures. A method of forming reduced area memory arrays by displacing adjacent similar structures along a common cell border. A method of building arrays using conventional array building software by forming unit pairs with cells that are not identical and are not mirror images or rotated versions of each other.

Abstract: An object is to provide a semiconductor device in which lower power consumption is realized by lowering voltage for data writing without increase in types of power supply potentials. Another object is to provide a semiconductor device in which threshold voltage drop of a selection transistor is suppressed without increase in types of power supply potentials for data writing. A diode-connected transistor is electrically connected in series with a word line electrically connected to a gate of an n-channel selection transistor. A capacitor is provided between the word line and a bit line electrically connected to one of a source and a drain of the selection transistor; alternatively, the capacitance between the bit line and the word line is used. In data writing, the timing of selecting the word line is earlier than the timing of selecting the bit line.

Abstract: Example embodiments relate to an interconnection substrate and a semiconductor chip package and a display system including the same. The interconnection substrate may include a base film, a signal line provided on the base film, a power line provided on the base film as a line pattern including a plurality of bent portions, and a ground line provided on the base film in parallel with the power line. The interconnection substrate may further include a semiconductor chip provided on the base film, wherein the power, ground, and/or signal lines are electrically connected to the semiconductor chip to form a semiconductor chip package. A display system may include the above semiconductor chip package, a screen displaying an image, and a PCB generating a signal. The semiconductor chip may be connected between the PCB and the screen and relay the generated signal from the PCB to the screen.

Abstract: In a manufacturing method of a non-volatile memory, a substrate is provided, and strip-shaped isolation structures are formed in the substrate. A first memory array including memory cell columns is formed on the substrate. Each memory cell column includes memory cells connected in series with one another, a source/drain region disposed in the substrate outside the memory cells, select transistors disposed between the source/drain region and the memory cells, control gate lines extending across the memory cell columns and in a second direction, and first select gate lines respectively connecting the select transistors in the second direction in series. First contacts are formed on the substrate at a side of the first memory array and arranged along the second direction. Each first contact connects the source/drain regions in every two adjacent active regions.

Abstract: A memory system having electromechanical memory cells and decoders is disclosed. A decoder circuit selects at least one of the memory cells of an array of such cells. Each cell in the array is a crossbar junction at least one element of which is a nanotube or a nanotube ribbon. The decoder circuit is constructed of crossbar junctions at least one element of each junction being a nanotube or a nanotube ribbon.

Abstract: A non-Flash non-volatile cross-trench memory array formed using an array of trenches formed back-end-of-the-line (BEOL) over a front-end-of-the-line (FEOL) substrate includes two-terminal memory elements operative to store at least one bit of data that are formed at a cross-point of a first trench and a second trench. The first and second trenches are arranged orthogonally to each other. At least one layer of memory comprises a plurality of the first and second trenches to form a plurality of memory elements. The non-volatile memory can be used to replace or emulate other memory types including but not limited to embedded memory, DRAM, SRAM, ROM, and FLASH. The memory is randomly addressable down to the bit level and erase or block erase operation prior to a write operation are not required.

Abstract: An integrated circuit formed of nonvolatile memory array circuits, logic circuits and linear analog circuits is formed on a substrate. The nonvolatile memory array circuits, the logic circuits and the linear analog circuits are separated by isolation regions formed of a shallow trench isolation. The nonvolatile memory array circuits are formed in a triple well structure. The nonvolatile memory array circuits are NAND-based NOR memory circuits formed of at least two floating gate transistors that are serially connected such that at least one of the floating gate transistors functions as a select gate transistor to prevent leakage current through the charge retaining transistors when the charge retaining transistors is not selected for reading. Each column of the NAND-based NOR memory circuits are associated with and connected to one bit line and one source line.

Abstract: The present disclosure provides a read only memory (ROM) cell array. The ROM cell array includes a plurality of fin active regions oriented in a first direction and formed on a semiconductor substrate; a plurality of gates formed on the plurality of fin active regions and oriented in a second direction perpendicular to the first direction; and a plurality of ROM cells formed by the plurality of fin active regions and the plurality of gates, the plurality of ROM cells being coded such that each cell of a first subset of ROM cells has a source electrically connected to a Vss line, and each cell of a second subset of ROM cells has a source electrically isolated. Each cell of the first subset of ROM cells includes a drain contact having a first contact area and a source contact having a second contact area at least 30% greater than the first contact area.

Abstract: An integrated circuit die is described that includes an array of tiles arranged in columns. The integrated circuit die includes interface tiles having at least one row of through die vias. The integrated circuit die includes metal layers that include horizontal wiring tracks and metal layers that include vertical wiring tracks. At least some of the metal layers having vertical wiring segments include horizontal wiring segments. Each horizontal wiring segment is coupled to a first wiring segment of a horizontal wiring track that is interrupted by the at least one row of through die vias and is coupled to a second wiring segment of the horizontal wiring track that is interrupted by the at least one row of through die vias. Each horizontal wiring segment extends between the at least one row of through die vias and at least one row of through die vias in an adjoining interface tile.

Abstract: In a 6F2 cell structure of a memory device and a method of fabricating the same, the plurality of active regions may have a first area at both end portions and a second area at a central portion. A portion of a bit-line contact pad may be positioned on the second area and the other portion may be positioned on a third area of the substrate that may not overlap with the plurality of active regions. The bit line may be connected with the bit-line contact pad at the third area. The cell structure may be more easily formed despite a 6F2-structured unit cell. The plurality of active regions may have an elliptical shape including major and minor axes. The plurality of active regions may be positioned in a major axis direction to thereby form an active row, and may be positioned in a minor axis direction in such a structure that a center of the plurality of active regions is shifted from that of an adjacent active region in a neighboring active row.

Abstract: A select gate transistor has a select gate electrode composed of a first-level conductive layer and a second-level conductive layer. The first-level conductive layer has contact areas. The second-level conductive layer has its portions removed that are located above the contact areas. Two adjacent select gate electrodes that are adjacent to each other in the column direction are arranged such that the contact areas of one select gate electrode are not opposed to the contact areas of the other select gate electrode. One select gate electrode has its first- and second-level conductive layers removed in their portions that are opposed to the contact areas of the other select gate electrode.

Abstract: A memory-array is disclosed in which an array of non-linear conductors such as diodes is constructed having an area per memory cell of 4F2 and comprises a plurality of conductors fabricated as doped semiconductor conducting lines in the substrate such that, during normal operation, an unselected conductor has a zero bias to the substrate and a selected conductor has a reverse bias to the substrate for minimizing current leakage

Abstract: The present invention is directed to reduce the chip area of a semiconductor integrated circuit. A semiconductor integrated circuit of the invention includes a first transistor, a second transistor disposed adjacent to the first transistor along a Y axis, and a third transistor disposed adjacent to the second transistor along an X axis. The semiconductor integrated circuit further includes a fourth transistor disposed adjacent to the third transistor along the Y axis and disposed adjacent to the first transistor along the X axis. The first to fourth transistors share a well, and an output signal of the first transistor and an output signal of the second transistor have phases opposite to each other. An output signal of the second transistor and an output signal of the third transistor have phases opposite to each other. An output of the third transistor and an output signal of the fourth transistor have phases opposite to each other.

Abstract: A semiconductor memory device includes: a semiconductor region extending vertically from a first region of a substrate; a plurality of gate electrodes disposed on the first region of the substrate in a vertical direction, but separated from each other along a sidewall of the semiconductor region; a gate dielectric layer disposed between the semiconductor region and the plurality of gate electrodes; a substrate contact electrode extending vertically from the impurity-doped second region of the substrate; and an insulating region formed as an air gap between the substrate contact electrode and at least one of the plurality of gate electrodes.

Abstract: Disclosed is a method to construct a device that includes a plurality of nanowires (NWs) each having a core and at least one shell. The method includes providing a plurality of radially encoded NWs where each shell contains one of a plurality of different shell materials; and differentiating individual ones of the NWs from one another by selectively removing or not removing shell material within areas to be electrically coupled to individual ones of a plurality of mesowires (MWs). Also disclosed is a nanowire array that contains radially encoded NWs, and a computer program product useful in forming a nanowire array.

Abstract: In an integrated circuit device, element power supply lines connected to a circuit containing a plurality of cells, element ground lines connected thereto, a trunk power supply line connected to each of the element power supply lines, and a trunk ground line connected to each of the element ground lines are provided in a first wiring layer. A branch power supply line connected to the trunk power supply line and a branch ground line connected to the trunk ground line are provided in an upper wiring layer located above the first wiring layer.

Abstract: A detector including an electrode formed from a first layer of conductive material, a readout line formed from a second layer of conductive material, and a via electrically connecting the readout line and the electrode. In one embodiment, the detector includes a source electrode and a drain electrode formed from the first layer of conductive material, and a data line formed from the second layer of conductive material, such that the source and drain electrodes are vertically offset from the data line. Alternatively, in another embodiment, the detector includes a gate electrode formed from the first layer of conductive material, and a scan line formed from the second layer of conductive material, such that the gate electrode is vertically offset from the scan line.

Abstract: A semiconductor device includes first lines extending in a first direction and formed in a first wiring layer in a predetermined arrangement order, second lines formed in a second wiring layer different from the first wring layer in the predetermined arrangement order, and contacts electrically connecting between the first lines and the second lines so as to match the arrangement order. In the semiconductor device, at least adjacent two tracks are defined in a linear manner parallel to a second direction perpendicular to the first direction. Then, each of the second lines includes a first line portion extending along one of the two tracks, a second line portion extending along another of the two tracks, and a connection portion connecting between the first and second line portions, while two or more of the contacts are formed at the connection portion.

Abstract: A gate in a semiconductor device is formed to have a dummy gate pattern that protects a gate. Metal lines are formed to supply power for a semiconductor device and transfer a signal. A semiconductor device includes a quad coupled receiver type input/output buffer. The semiconductor device is formed with a gate line that extends over an active region, and a gate pad located outside of the active region. The gate line and the gate pad are adjoined such that the gate line and a side of the gate pad form a line. Dummy gates may also be applied. The semiconductor device includes a first metal line patterns supplying power to a block having a plurality of cells, a second metal line pattern transferring a signal to the cells, and dummy metal line patterns divided into in a longitudinal direction.

Abstract: A semiconductor memory apparatus includes a first pad group located along a first edge of a plurality of banks, a second pad group located along a second edge of the plurality of banks opposite the first pad group, and a pad control section configured to provide first and second bonding signals and to implement control operation in response to a test mode signal and a bonding option signal to selectively employ signals from the first and second pad groups.

Abstract: Disclosed are a liquid crystal display and a substrate for the same. The substrate comprises first wires formed in one direction on the substrate; second wires intersecting and insulated from the first wires; pixel electrodes formed in pixel regions defined by the first wires and the second wires; and switching elements connected to the first wires, the second wires and the pixel electrodes, wherein an interval between two adjacent second wires has a predetermined dimension that repeatedly varies from one set of adjacent second wires to the next, and a side of the pixel electrodes adjacent to the second wires is shaped in a pattern identical to the second wires such that the pixel electrodes have a wide portion and a narrow portion.

Abstract: An improved integrated circuit cell architecture is provided for configurability between a memory cell or logic elements. The cell architecture is configured on variable layers above a first layer of metal, with the first layer of metal and layers therebelow reserved as fixed layers. By coupling a maximum of two layout cells together, a single-port or dual-port memory cell is realized. Likewise, by interconnecting transistors within a single cell or transistors among two or more cells, a logic device is realized. Within each cell, the bit lines are arranged on a layer separate from the wordlines, and extend orthogonal to each other.

Abstract: An object is to provide a semiconductor memory device which stores data with the use of a transistor having small leakage current between a source and a drain in an off state as a writing transistor. In a matrix including a plurality of memory cells, gates of the writing transistors are connected to writing word lines. In each of the memory cells, a drain of the writing transistor is connected to a gate of a reading transistor, and the drain is connected to one electrode of a capacitor. Further, the other electrode of the capacitor is connected to a reading word line. In the semiconductor memory device in which the memory cells are connected in series so as to have a NAND structure, gates of the reading transistors are provided alternately, and the reading word line and the writing word line are shared.

Abstract: Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes lateral and upper hydrogen blocking patterns disposed to prevent hydrogen from diffusing into the cell array region. Accordingly, hydrogen is effectively prevented from being trapped in a tunnel dielectric, thereby improving the reliability of the semiconductor device. In the method, when a cell array contact plug is formed, a lateral hydrogen blocking pattern and an upper hydrogen blocking pattern are formed at the same time. Thus, an additional process for forming a hydrogen blocking pattern is unnecessary, thereby simplifying a process.

Abstract: The present invention relates to a flexible analog/digital configuration, preferably on a chip, that can be used for receiving various inputs, processing those inputs, and displaying/communicating the results and/or providing a response thereto. More particularly, the present invention can measure multiple parameters and, when properly programmed, can easily organize the data from multiple sensors or other analog or digital sources. It can present or display different, or similar, pages for setting up each measurement (or each measured parameter) (e.g., by sensor, class of sensors, etc.) to enable an easy to use approach for individuals without needing to know the specifics as to many parameters. This user-friendly approach can be performed using a configurable chip module system.

Abstract: A 3D memory device is based on an array of conductive pillars and a plurality of patterned conductor planes including left side and right side conductors adjacent the conductive pillars at left side and right side interface regions. Memory elements in the left side and right side interface regions comprise a programmable element and a rectifier. The conductive pillars can be selected using two-dimensional decoding, and the left side and right side conductors in the plurality of planes can be selected using decoding on a third dimension, combined with left and right side selection.

Abstract: A semiconductor device having plural active and passive elements on one semiconductor substrate is manufactured in the following cost effective manner even when the active and passive elements include double sided electrode elements. When the semiconductor substrate is divided into plural field areas, an insulation separation trench that penetrates the semiconductor substrate surrounds each of the field areas, and each of the either of the plural active elements or the plural passive elements. Further, each of the plural elements has a pair of power electrodes for power supply respectively disposed on each of both sides of the semiconductor substrate to serve as the double sided electrode elements.

Abstract: A semiconductor integrated circuit includes a function block arranged on a substrate, a first buffering cell arranged adjacent to a first side of the function block, a second buffering cell arranged adjacent to a second side adjacent to the first side of the function block, and signal wiring passing over the function block obliquely relative to the first side and the second side, connecting the first buffering cell and the second buffering cell.

Abstract: A semiconductor device includes a plurality of MOS transistors, wherein each of the MOS transistors has a drain region, a pair of source regions sandwiching therebetween the drain region, and a pair of normal gates each overlying a space between the drain region and a corresponding one of the source regions. A plurality of dummy gates are provided each between adjacent two of the MOS transistors. The dummy gate electrodes are maintained at an equi-potential with the adjacent drain regions. MOS transistors include a row of pMOS transistors and nMOS transistors, wherein each of pMOS transistors and a corresponding nMOS transistor configure a CMOS gate, and a plurality of CMOS gates configure a ring oscillator.

Abstract: An integrated circuit includes a plurality of signal lines. A first signal line layer includes a plurality of first signal lines. A second signal line layer includes a plurality of second signal lines arranged on top of and insulated from the first signal line layer. A third signal line layer includes a plurality of third signal lines arranged on top of and insulated from the second signal line layer. A contact extends through the second signal line layer and connects at least one of the plurality of third signal lines to at least one of the first signal lines. At least one of the second signal lines further extends in a second direction to bend around the contact such that a predetermined distance separates the plurality of second signal lines from the contact.

Abstract: It is an object to provide a semiconductor integrated circuit which can easily be designed and has a low wiring resistance, and a method and apparatus for designing the semiconductor integrated circuit. In a semiconductor integrated circuit apparatus according to the invention, a first wiring layer is provided with a plurality of signal wirings having an equal width which is disposed in parallel with each other at a regular interval, and at least two of the signal wirings which are adjacent to each other are electrically connected to each other.

Abstract: This invention prevents a break in a signal wire disposed between wire ends due to attenuation and improves production yields of devices. In a standard cell, a first signal wire extends in a first direction. Second and third signal wires extend in a second direction substantially perpendicular to the first direction and are facing each other across the first signal wire. The second and third signal wires have the widths larger than the width of the first signal wire.

Abstract: A fabrication method for a BGA or LGA package includes a low-cost metal leadframe with internally extended leads. I/O attach lands can be placed at any location on the metal leadframe, including the center of the package. An I/O attach land can be fabricated at any position upon an extended lead (e.g., near the center of the package). During fabrication of the package, an isolation saw cut to the bottom of the package can be used to electrically disconnect the leadframe circuit from the peripheral extension traces to prevent tampering with the IC die by probing the edge metal traces.

Abstract: A device includes a semiconductor substrate, a first local bit line formed in the semiconductor substrate and elongated in a first direction, a first insulating layer on the semiconductor substrate, a first global bit line formed on the first insulating layer, a first path formed in the first insulating layer to couple a first end of the first local bit line with the first global bit line, and a second path formed in the first insulating layer to couple a second end of the first local bit line with the first global bit line.

Abstract: A semiconductor device includes a first pad, a second pad and a third pad. The first pad and the third pad are electrically connected to each other. The first pad and the second pad are used for bonding. The second pad and the third pad are used for probing. According to this structure, Small size semiconductor device having high reliability even after a probing test can be provided.

Abstract: Gate electrodes 5A through 5F are formed to have the same geometry, and protruding parts of the gate electrodes 5A through 5F extend across an isolation region onto impurity diffusion regions. The gate electrode 5B and P-type impurity diffusion regions 7B6 are connected through a shared contact 9A1 to a first-level interconnect M1H, and the gate electrode 5E and N-type impurity diffusion regions 7A6 are connected through a shared contact 9A2 to a first-level interconnect M1I. In this way, contact pad parts of the gate electrodes 5A through 5F can be located apart from active regions of a substrate for MOS transistors. This suppresses the influence of the increased gate length due to hammerhead and gate flaring. As a result, transistors TrA through TrF can have substantially the same finished gate length.

Abstract: A thin film transistor substrate and fabricating method thereof by which the size of the thin film transistor substrate is reduced by constructing data signal supply lines, each of which supplies a pixel data voltage to a data line, with different metal lines, respectively includes gate and data lines crossing each other on a substrate, with a gate insulating layer disposed therebetween, a thin film transistor formed on each intersection between the gate and data lines, a display area on which a pixel electrode connected to the thin film transistor is formed, a first data signal supply line comprising a first conductive layer connected to the data line in a non-display area located at a periphery of the display area, and a second data signal supply line alternating with the first data signal supply line, with the gate insulating layer disposed therebetween, the second data signal supply line comprising a second conductive layer connected to the data line.

Abstract: An integrated circuit biases the substrate and well using voltages other than those used for power and ground. Tap cells inside the standard cell circuits are removed. New tap cells used to bias the substrate and well reside outside the standard cell circuits. The location of the new voltage power rails is designated prior to placement of the tap cells in the integrated circuit. The tap cells are then strategically placed near the power rails such that metal connections are minimized. Circuit density is thus not adversely impacted by the addition of the new power rails. Transistors are also placed inside the tap cells to address electrostatic discharge issues during fabrication.