Abstract: A mesoporous silica having adjustable pores is obtained to form a template and thus a three-terminal metal-oxide-semiconductor field-effect transistor (MOSFET) photodetector is obtained. A gate dielectric of a nano-structural silicon-base membrane is used as infrared light absorber in it. Thus, a semiconductor photodetector made of pure silicon having a quantum-dot structure is obtained with excellent near-infrared optoelectronic response.

Abstract: One or more quantum dots are used to control current flow in a transistor. Instead of being disposed in a channel between source and drain, the quantum dot (or dots) are vertically separated from the source and drain by an insulating layer. Current can tunnel between the source/drain electrodes and the quantum dot (or dots) by tunneling through the insulating layer. Quantum dot energy levels can be controlled with one or more gate electrodes capacitively coupled to some or all of the quantum dot(s). Current can flow between source and drain if a quantum dot energy level is aligned with the energy of incident tunneling electrons. Current flow between source and drain is inhibited if no quantum dot energy level is aligned with the energy of incident tunneling electrons. Here energy level alignment is understood to have a margin of about the thermal energy (e.g., 26 meV at room temperature).

Abstract: A storage layer is arranged facing an array of micro-tips. The storage layer includes a plurality of insulated conductive dots designed to store electric charges. Each micro-tip includes a high-permittivity element integral to a transistor channel connecting a source and a drain. The channel has a conductance able to be modified by the electric field created by the charge of the dot arranged facing the high-permittivity element. The system can include an actuator for relative displacement of the storage layer with respect to the micro-tips. The system can include an array of electrodes able to cause displacement of the charges from one dot to the other.

Abstract: According to an exemplary embodiment, a bipolar/dual FET structure includes a bipolar transistor situated over a substrate. The bipolar/dual FET structure further includes an enhancement-mode FET and a depletion-mode FET situated over the substrate. In the bipolar/dual FET structure, the channel of the enhancement-mode FET is situated above the base of the bipolar transistor and the channel of the depletion-mode FET is situated below the base of the bipolar transistor. The channel of the enhancement-mode FET is isolated from the channel of the depletion-mode FET so as to decouple the enhancement-mode FET from the depletion mode FET.

Abstract: State-of-the-art synthesis of carbon nanostructures (25) by chemical vapor deposition involve heating a catalyst material to high temperatures up 700-1000° C. in a furnace and flowing hydrocarbon gases through the reactor over a period of time. In order to enable a self assembly of nanostructures (25) on microchips (10) without damaging the microchip (10) by high temperatures the proposed manufacturing method comprises: A layer (1) contains indentations (3) on which nanostructures (25) are to be integrated and the indentations (3) are heated up by a current (I) conducted to the layer (1) via contact pads (2).

Abstract: A semiconductor includes a semiconductor substrate, a gate stack on the semiconductor substrate, and a stressor having at least a portion in the semiconductor substrate and adjacent to the gate stack. The stressor includes a first stressor region and a second stressor region on the first stressor region, wherein the second stressor region extends laterally closer to a channel region underlying the gate stack than the first stressor region.

Abstract: There is provided a hetero junction field effect transistor including: a first layer of a nitride based, group III-V compound semiconductor; a second layer of a nitride based, group III-V compound semiconductor containing a rare earth element, overlying the first layer; a pair of third layers of a nitride based, group III-V compound semiconductor, overlying the second layer, the third layers being spaced from each other; a gate electrode disposed between the third layers at least a region of the second layer; and a source electrode overlying one of the third layers and a drain electrode overlying an other of the third layers. A method of fabricating the hetero junction field effect transistor is also provided.

Abstract: The present invention is related to a ferroelectric storage medium for ultrahigh density data storage device and a method for fabricating the same. A supercell having high anisotropy is formed by controlling crystal structure and symmetry of unit structure (supercell) of artificial lattice by using an ordered alignment of predetermined ions having orientation of (perpendicular) deposition direction. Unit atomic layers of oxides having different polarization characteristic are deposited so that the supercell itself shows electric polarization having only two, upward and downward directions as one block of supercell having single-directional polarization. Oxide artificial lattices can be formed so as to have solely 180 degree domain structure, thus a single electric domain having improved anisotropic characteristic can be formed, thereby allowing capability of ultrahigh density data storage and long term data retention.

Abstract: A nitride semiconductor device comprises: a laminated body; a first and second main electrode provided in a second and third region, respectively, adjacent to either end of the first region on the major surface of the laminated body; and a third main electrode. The laminated body includes a first semiconductor layer of a nitride semiconductor and a second semiconductor layer of a nondoped or n-type nitride semiconductor having a wider bandgap than the first semiconductor layer, the second semiconductor layer being provided on the first semiconductor layer. The third main electrode is provided on the major surface of the laminated body and opposite to the control electrode across the second main electrode.

Abstract: A field effect transistor of an embodiment of the present invention includes, a semiconductor substrate containing Si atoms; a protruding structure formed on the semiconductor substrate; a channel region formed in the protruding structure and containing Ge atoms; an under channel region formed under the channel region in the protruding structure and containing Si and Ge atoms, the Ge composition ratio among Si and Ge atoms contained in the under channel region continuously changing from the channel region side to the semiconductor substrate side; a gate insulating film formed on the channel region; and a gate electrode formed on the gate insulating film on the channel region.

Abstract: An electronic device has a source electrode, a drain electrode spaced apart from said source electrode, and at least one of a conducting material, dielectric material and a semiconductor material disposed between said source electrode and said drain electrode. At least one of the source electrode, the drain electrode and the semiconductor material includes at least one nanowire.

Abstract: An electronic device can include a transistor structure of a first conductivity type, a field isolation region, and a layer of a first stress type overlying the field isolation region. For example, the transistor structure may be a p-channel transistor structure and the first stress type may be tensile, or the transistor structure may be an n-channel transistor structure and the first stress type may be compressive. The transistor structure can include a channel region that lies within an active region. An edge of the active region includes the interface between the channel region and the field isolation region. From a top view, the layer can include an edge the lies near the edge of the active region. The positional relationship between the edges can affect carrier mobility within the channel region of the transistor structure.

Abstract: A CNT channel layer of a transistor is cut along a direction perpendicular to the channel to form a plurality of CNT patches, which are used to connect between a source and a drain. The arrangement of the CNT channel layer formed of a plurality of CNT patches can increase the probability that part of CNT patches becomes a semiconductive CNT patch. Since part of a plurality of CNT patches forming the channel layer is formed of a semiconductive CNT patch, a transistor having a good on/off ratio can be provided.

Abstract: A strained Fin Field Effect Transistor (FinFET) (and method for forming the same) includes a relaxed first material having a sidewall, and a strained second material formed on the sidewall of the first material. The relaxed first material and the strained second material form a fin of the FinFET.

Abstract: Provided are an electronic device to which vertical carbon nanotubes (CNTs) are applied and a method of manufacturing the same.

Abstract: Provided are a method of manufacturing a semiconductor nanowire sensor device and a semiconductor nanowire sensor device manufactured according to the method. The method includes preparing a first conductive type single crystal semiconductor substrate, forming a line-shaped first conductive type single crystal pattern from the first conductive type single crystal semiconductor substrate, forming second conductive type epitaxial patterns on both sidewalls of the first conductive type single crystal pattern, and forming source and drain electrodes at both ends of the second conductive type epitaxial patterns.

Abstract: A phase controllable field effect transistor device is described. The device provides first and second scattering sites disposed at either side of a conducting channel region, the conducting region being gated such that on application of an appropriate signal to the gate, energies of the electrons in the channel region defined between the scattering centres may be modulated.

Abstract: A floating body germanium (Ge) phototransistor and associated fabrication process are presented. The method includes: providing a silicon (Si) substrate; selectively forming an insulator layer overlying the Si substrate; forming an epitaxial Ge layer overlying the insulator layer using a liquid phase epitaxy (LPE) process; forming a channel region in the Ge layer; forming a gate dielectric, gate electrode, and gate spacers overlying the channel region; and, forming source/drain regions in the Ge layer. The LPE process involves encapsulating the Ge with materials having a melting temperature greater than a first temperature, and melting the Ge using a temperature lower than the first temperature. The LPE process includes: forming a dielectric layer overlying deposited Ge; melting the Ge; and, in response to cooling the Ge, laterally propagating an epitaxial growth front into the Ge from an underlying Si substrate surface.

Abstract: A transistor device having a conformal depth of impurities implanted by isotropic ion implantation into etched junction recesses. For example, a conformal depth of arsenic impurities and/or carbon impurities may be implanted by plasma immersion ion implantation in junction recesses to reduce boron diffusion and current leakage from boron doped junction region material deposited in the junction recesses. This may be accomplished by removing, such as by etching, portions of a substrate adjacent to a gate electrode to form junction recesses. The junction recesses may then be conformally implanted with a depth of arsenic and carbon impurities using plasma immersion ion implantation. After impurity implantation, boron doped silicon germanium can be formed in the junction recesses.

Abstract: A transistor includes: a first semiconductor layer and a second semiconductor layer with a first region and a second region, which are sequentially formed above a substrate; a first p-type semiconductor layer formed on a region of the second semiconductor layer other than the first and second regions; and a second p-type semiconductor layer formed on the first p-type semiconductor layer. The first p-type semiconductor layer is separated from a drain electrode by interposing therebetween a first groove having a bottom composed of the first region, and from a source electrode by interposing therebetween a second groove having a bottom composed of the second region.

Abstract: A field effect transistor comprises a source and a drain, and a channel layer of Si1-x-yGexCy crystal (1>x>0, 1>y?0). Ge composition increases toward a drain end, in a vicinity of a source end of the channel layer.

Abstract: A semiconductor device may include a semiconductor substrate and at least one non-volatile memory cell. The at least one memory cell may include spaced apart source and drain regions, and a superlattice channel including a plurality of stacked groups of layers on the semiconductor substrate between the source and drain regions. Each group of layers of the superlattice channel may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and an energy band-modifying layer thereon, which may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. A floating gate may be adjacent the superlattice channel, and a control gate may be adjacent the second gate insulating layer.

Abstract: The present invention relates to a method of fabricating a nanoscale multi-junction quantum dot device wherein it can minimize constraints depending on the number or shape of patterns and a line width, and in particular, overcome shortcomings depending on the proximity effect occurring between patterns while employing the advantages of electron beam lithography to the utmost by forming a new conductive layer between the patterns and utilizing it as a new pattern.

Abstract: A semiconductor device is supported by a substrate with a smaller lattice constant. A metamorphic buffer provides a transition from the smaller lattice constant of the substrate to the larger lattice constant of the semiconductor device. In one application, the semiconductor device has a lattice constant of between approximately 6.1 and 6.35 angstroms, metamorphic buffer layers include Sb (e.g., AlInSb buffer layers), and the substrate has a smaller lattice constant (e.g., Si, InP or GaAs substrates).

Abstract: A nanowire (100) according to the present invention includes a plurality of contact regions (10a, 10b) and at least one channel region (12), which is connected to the contact regions (10a, 10b). The channel region (12) is made of a first semiconductor material and the surface of the channel region (12) is covered with an insulating layer that has been formed selectively on the channel region (12). The contact regions (10a, 10b) are made of a second semiconductor material, which is different from the first semiconductor material for the channel region (12), and at least the surface of the contact regions (10a, 10b) includes a conductive portion.

Abstract: Aluminum free high electron mobility transistors (HEMTs) and methods of fabricating aluminum free HEMTs are provided. In some embodiments, the aluminum free HEMTs include an aluminum free Group III-nitride barrier layer, an aluminum free Group III-nitride channel layer on the barrier layer and an aluminum free Group III-nitride cap layer on the channel layer.

Abstract: A method of fabricating a semiconductive film stack for use as a polysilicon germanium gate electrode to address problems associated with implant and diffusion of dopants. Achieving a sufficiently high active dopant concentration at a gate-dielectric interface while avoiding gate penetration of dopants such as boron is problematic. A higher gate implant dosage or annealing temperature is needed, and boron penetration through the thin gate oxide is inevitably enhanced. Both problems are exacerbated as the gate dielectric becomes thinner. In order to achieve a high level of active dopant concentration next to the gate dielectric without experiencing problems associated with gate depletion and penetration, a method and procedures of applying a diffusion-blocking layer is described with respect to an exemplary MOSFET application. However, a diffusion-blocking concept is also presented, which is readily amenable to a variety of semiconductor related technologies.

Abstract: A semiconductor device may include a stress layer and a strained superlattice layer above the stress layer and including a plurality of stacked groups of layers. More particularly, each group of layers of the strained superlattice layer may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

Abstract: Carbon nanotube, method for positioning the same, field effect transistor made using the carbon nanotube, method for making the field-effect transistor, and a semiconductor device are provided. The carbon nanotube includes a bare carbon nanotube and a functional group introduced to at least one end of the bare carbon nanotube.

Abstract: A semiconductor device may include a strained superlattice layer including a plurality of stacked groups of layers, and a stress layer above the strained superlattice layer. Each group of layers of the strained superlattice layer may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

Abstract: Methods and apparatuses for nanoenabled memory devices and anisotropic charge carrying arrays are described. In an aspect, a memory device includes a substrate, a source region of the substrate, and a drain region of the substrate. A population of nanoelements is deposited on the substrate above a channel region, the population of nanolements in one embodiment including metal quantum dots. A tunnel dielectric layer is formed on the substrate overlying the channel region, and a metal migration barrier layer is deposited over the dielectric layer. A gate contact is formed over the thin film of nanoelements. The nanoelements allow for reduced lateral charge transfer. The memory device may be a single or multistate memory device.

Abstract: A semiconductor device may include a substrate, an insulating layer adjacent the substrate, and a semiconductor layer adjacent a face of the insulating layer opposite the substrate. The device may further include source and drain regions on the semiconductor layer, a superlattice adjacent the semiconductor layer and extending between the source and drain regions to define a channel, and a gate overlying the superlattice. The superlattice may include a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and an energy band-modifying layer thereon. The energy band-modifying layer may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

Abstract: A resonant transistor includes a substrate, a source and a drain formed on the substrate, an input electrode and a carbon nanotube gate. A gap is formed between the source and the drain. The input electrode is formed on the substrate. The carbon nanotube gate is clamped on one end by a contact electrode and positioned, preferably cantilevered, over the gap and over the input electrode.

Abstract: A MOS device includes first and second source/drains spaced apart relative to one another. A channel is formed in the device between the first and second source/drains. A gate is formed in the device between the first and second source/drains and proximate the channel, the gate being electrically isolated from the first and second source/drains and the channel. The gate is configured to control a conduction of the channel as a function of a potential applied to the gate. The MOS device further includes an energy filter formed between the first source/drain and the channel. The energy filter includes a superlattice structure wherein a mini-band is formed. The energy filter is operative to control an injection of carriers from the first source/drain into the channel. The energy filter, in combination with the first source/drain, is configured to produce an effective zero-Kelvin first source/drain.

Abstract: A method for forming and the structure of a strained lateral channel of a field effect transistor, a field effect transistor and CMOS circuitry is described incorporating a drain, body and source region on a single crystal semiconductor substrate wherein a hetero-junction is formed between the source and body of the transistor, wherein the source region and channel are independently lattice strained with respect the body region. The invention reduces the problem of leakage current from the source region via the hetero-junction and lattice strain while independently permitting lattice strain in the channel region for increased mobility via choice of the semiconductor materials and alloy composition.

Abstract: A method for fabricating a semiconductor device which protects the ohmic metal contacts and the channel of the device during subsequent high temperature processing steps is explained. An encapsulation layer is used to cover the channel and ohmic metal contacts. The present invention provides a substrate on which a plurality of semiconductor layers are deposited. The semiconductor layers act as the channel of the device. The semiconductor layers are covered with an encapsulation layer. A portion of the encapsulation layer and the plurality of semiconductor layers are removed, wherein ohmic metal contacts are deposited. The ohmic metal contacts are then annealed to help reduce their resistance. The encapsulation layer ensures that the ohmic metal contacts do not migrate during the annealing step and that the channel is not harmed by the high temperatures needed during the annealing step.

Abstract: A field effect transistor (FET) includes a semiconductor region of a first conductivity type and a well region of a second conductivity type extending over the semiconductor region. A gate electrode is adjacent to but insulated from the well region, and a source region of the first conductivity type is in the well region. A heavy body region is in electrical contact with the well region, and includes a material having a lower energy gap than the well region.

Abstract: A field effect transistor (FET) includes a first semiconductor layer and a second semiconductor layer, the second semiconductor layer being formed on the first semiconductor layer and having a band gap energy greater than that of the first semiconductor layer. The first and second semiconductor layers are made of a Group III-V compound semiconductor layer, formed on the first semiconductor layer are a gate electrode 36 and a source electrode 35, formed on the second semiconductor layer is a drain electrode 37, and the drain electrode and the gate electrode are formed respectively on opposing planes of a semiconductor structure which contains the first and second semiconductor layers. This arrangement enables a drain's breakdown voltage to be increased in the FET, because the gate electrode 36 and the drain electrode 37 are respectively disposed, in a spatial separation of each other, on different planes instead of the same plane of the semiconductor structure.

Abstract: The present invention discloses use of quantum dot gate FETs as a nonvolatile memory element that can be used in flash memory architecture as well as in a nonvolatile random access memory (NVRAM) configuration that does not require refreshing of data as in dynamic random access memories. Another innovation is the design of quantum dot gate nonvolatile memory and 3-state devices using modulation doped field-effect transistors (MODFETs), particularly MOS-gate field effect transistors. The cladded quantum dot gate MODFETs can be designed in Si—SiGe, InGaAs—InP and other material systems. The incorporation of 3-state FET devices in static random access memory (SRAM) cell is described to result in advanced multi-state memory operation. Unlike conventional SRAMs, the 3-state QD-FET based of SRAMs provides 3 and 4-state memory operation due to the utilization of the intermediate states particularly in CMOS configuration.

Abstract: A GaN-based heterostructure field effect transistor capable of accomplishing higher output, higher breakdown voltage, higher speed, higher frequency, and the like. A heterostructure field effect transistor including a channel layer (4) of GaN and a barrier layer (6) of AlGaN, wherein the surface of a transistor element has an insulating film (10).

Abstract: Binary Group III-nitride high electron mobility transistors (HEMTs) and methods of fabricating binary Group III-nitride HEMTs are provided. In some embodiments, the binary Group III-nitride HEMTs include a first binary Group III-nitride barrier layer, a binary Group III-nitride channel layer on the first barrier layer; and a second binary Group III-nitride barrier layer on the channel layer. In some embodiments, the binary Group III-nitride HEMTs include a first AIN barrier layer, a GaN channel layer and a second AIN barrier layer.

Abstract: A light source is provided including an LED component having an emitting surface, which may include: i) an LED capable of emitting light at a first wavelength; and ii) a re-emitting semiconductor construction which includes a second potential well not located within a pn junction having an emitting surface; or which may alternately include a first potential well located within a pn junction and a second potential well not located within a pn junction; and which additionally includes a converging optical element.

Abstract: A hybrid semiconductor structure which includes a horizontal semiconductor device and a vertical carbon nanotube transistor, where the vertical carbon nanotube transistor and the horizontal semiconductor device have at least one shared node is provided. The at least one shared node can include, for example, a drain, source or gate electrode of a FET, or an emitter, collector, or base of a bipolar transistor.

Abstract: A semiconductor device may include a substrate and spaced apart source and drain regions defining a channel region therebetween in the substrate. The substrate may have a plurality of spaced apart superlattices in the channel and/or drain regions. Each superlattice may include a plurality of stacked groups of layers, with each group including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer thereon. The at least one non-semiconductor monolayer may be constrained within a crystal lattice of adjacent base semiconductor portions.

Abstract: A semiconductor device may include at least one pair of spaced apart stress regions, and a strained superlattice layer between the at least one pair of spaced apart stress regions and including a plurality of stacked groups of layers. Each group of layers of the strained superlattice layer may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

Abstract: A semiconductor device includes, an AlGaN electron supply layer having a [000-1] crystalline orientation in a thickness direction to a substrate plane, a GaN electron traveling layer formed on the AlGaN electron supply layer, a gate electrode formed above the GaN electron traveling layer, and a source electrode and a drain electrode between which the gate electrode is located, the source and drain electrode being formed on the GaN electron traveling layer.

Abstract: A field effect transistor including an i-type first semiconductor layer and a second semiconductor layer formed on the first semiconductor layer and having a band gap energy higher in magnitude than that of the first semiconductor layer. The first semiconductor layer and second semiconductor layer are each made of a gallium nitride-based compound semiconductor layer. A gate electrode is formed on the second semiconductor layer and a second electrode is formed on the first semiconductor layer. Thus, the field effect transistor is constructed in such a manner as the first semiconductor layer and second semiconductor layer are interposed between the gate electrode and the second electrode. Thus field effect transistor is able to discharge the holes that are accumulated in the channel from the elemental structure and to improve the withstand voltage of the field effect transistor.

Abstract: A semiconductor device includes: a first semiconductor layer represented by a composition formula AlxGa1-xN (0?x?1); a first conductivity type or non-doped second semiconductor layer represented by a composition formula AlyGa1-yN (0?y?1, x<y) and formed on the first semiconductor layer; a second conductivity type third semiconductor layer represented by a composition formula AlxGa1-xN (0?x?1) and selectively formed on the second semiconductor layer; a gate electrode formed on the third semiconductor layer; a source electrode electrically connected to the second semiconductor layer; and a drain electrode electrically connected to the second semiconductor layer. The distance between the drain electrode and the third semiconductor layer is longer than the distance between the source electrode and the third semiconductor layer.

Abstract: A semiconductor-based structure includes first and second layers bonded directly to each other at an interface. Parallel to the interface, the lattice spacing of the second layer is different than the lattice spacing of the first layer. The first and second layers are each formed of essentially the same semiconductor. A method for making a semiconductor-based structure includes providing first and second layers that are formed of essentially the same semiconductor. The first and second layers have, respectively, first and second surfaces. The second layer has a different lattice spacing parallel to the second surface than the lattice spacing of the first layer parallel to the first surface. The method includes contacting the first and second surfaces, and annealing to promote direct atomic bonding between the first and second layers.

Abstract: A field effect transistor with a heterostructure includes a strained monocrystalline semiconductor layer formed on a carrier material, which has a relaxed monocrystalline semiconductor layer made of a first semiconductor material (Si) as the topmost layer. The strained monocrystalline semiconductor layer has a semiconductor alloy (GexSi1-x), where the proportion x of a second semiconductor material can be set freely. Furthermore, a gate insulation layer and a gate layer are formed on the strained semiconductor layer. To define an undoped channel region, drain/source regions are formed laterally with respect to the gate layer at least in the strained semiconductor layer. The possibility of freely setting the Ge proportion x enables a threshold voltage to be set as desired, whereby modern logic semiconductor components can be realized.