Abstract: A stacked semiconductor device and a method for fabricating the stacked semiconductor device are disclosed. The stacked semiconductor device includes a first insulating interlayer having an opening that partially exposes a substrate, wherein the substrate includes single crystalline silicon, and a first seed pattern that fills the opening, wherein the first seed pattern has an upper portion disposed over the opening, and the upper portion is tapered away from the substrate. The stacked semiconductor device further includes a second insulating interlayer formed on the first insulating interlayer, wherein a trench that exposes the upper portion of the first seed pattern penetrates the second insulating interlayer, and a first single crystalline silicon structure that fills the trench.

Abstract: In a layout for a semiconductor device, each active region comprises a first active region, a right active region on the right side of the first active region, a left active region on the left side of the first active region, an upper active region on the upper side of the first active region and a lower active region on the lower side of the first active region, wherein the first active region, the right active region, the left active region, the upper active region and the lower active region each have an inclined portion having a bit-line contact region; and first and second portions having a storage node contact region, first and second ends formed on left and right ends of the inclined portion at a predetermined tilt angle with respect to the inclined portion, the active region being intersected by two word lines and one bit line.

Abstract: A semiconductor device and a method of manufacturing are provided. A dielectric layer is formed over a substrate, and a first silicon-containing layer, undoped, is formed over the dielectric layer. Atomic-layer doping is used to dope the undoped silicon-containing layer. A second silicon-containing layer is formed over first silicon-containing layer. The process may be expanded to include forming a PMOS and NMOS device on the same wafer. For example, the first silicon-containing layer may be thinned in the PMOS region prior to the atomic-layer doping. In the NMOS region, the doped portion of the first silicon-containing layer is removed such that the remaining portion of the first silicon-containing layer in the NMOS is undoped. Thereafter, another atomic-layer doping process may be used to dope the first silicon-containing layer in the NMOS region to a different conductivity type. A third silicon-containing layer may be formed doped to the respective conductivity type.

Abstract: A semiconductor device of the present invention has a semiconductor substrate having a transistor formed thereon; a multi-layered interconnect formed on the semiconductor substrate, and having a plurality of interconnect layers, respectively composed of an interconnect and an insulating film, stacked therein; and a capacitance element having a lower electrode (lower electrode film), a capacitor insulating film, and an upper electrode (upper electrode film), all of which being embedded in the multi-layered interconnect, so as to compose a memory element, and further includes at least one layer of damascene-structured copper interconnect (second-layer interconnect) formed between the capacitance element and the transistor; the upper surface of one of the interconnects (second-layer interconnect) and the lower surface of the capacitance element are aligned nearly in the same plane; and at least one layer of copper interconnect (plate line interconnect) is formed over the capacitance element.

Abstract: To decrease the burden of digital processing, provided is an AD conversion apparatus comprising a pattern generating section that, for each target bit specified one bit at a time moving downward in the output data, generates a pattern signal having a pulse width or number of pulses corresponding to a weighting of the target bit; an integrating section that integrates the pattern signals according to a judgment value for judging a value of the target bit each time a pattern signal is generated, and outputs a reference signal obtained by accumulating the integrated value of each pattern signal; a comparing section that, each time generation of a pattern signal is finished, compares the input signal to the reference signal; and an output section that outputs the output data to have values corresponding to the comparison results obtained after each generation of a pattern signal corresponding to a bit is finished.

Abstract: A non-volatile memory device includes a semiconductor substrate having a peripheral circuit region and a cell region, wherein the cell region of the semiconductor substrate is lower in height than the peripheral circuit region of the semiconductor substrate, a control gate structure disposed over the cell region of the semiconductor substrate and comprising a plurality of inter-layer dielectric layers that are alternately stacked with a plurality of control gate electrodes, a first insulation layer covering the cell region of the semiconductor substrate where the control gate structure is formed, a selection gate electrode disposed over the first insulation layer, and a peripheral circuit device disposed over the peripheral circuit region of the semiconductor substrate.

Abstract: A method of integrated circuit fabrication is provided, and more particularly fabrication of a semiconductor apparatus with a metallic alloy. An exemplary structure for a semiconductor apparatus comprises a first silicon substrate having a first contact comprising a silicide layer between the substrate and a first metal layer; a second silicon substrate having a second contact comprising a second metal layer; and a metallic alloy between the first metal layer of the first contact and the second metal layer of the second contact.

Abstract: A 3-D memory is provided. Each word line layer has word lines and gaps alternately arranged along a first direction. Gaps include first group and second group of gaps alternately arranged. A first bit line layer is on word line layers and has first bit lines along a second direction. A first conductive pillar array through word line layers connects the first bit line layer and includes first conductive pillars in first group of gaps. A first memory element is between a first conductive pillar and an adjacent word line. A second bit line layer is below word line layers and has second bit lines along the second direction. A second conductive pillar array through word line layers connects the second bit line layer and includes second conductive pillars in second group of gaps. A second memory element is between a second conductive pillar and an adjacent word line.

Abstract: An integrated circuit chip includes a silicon substrate, a first circuit in or over said silicon substrate, a second circuit device in or over said silicon substrate, a dielectric structure over said silicon substrate, a first interconnecting structure in said dielectric structure, a first pad connected to said first node of said voltage regulator through said first interconnecting structure, a second interconnecting structure in said dielectric structure, a second pad connected to said first node of said internal circuit through said second interconnecting structure, a passivation layer over said dielectric structure, wherein multiple opening in said passivation layer exposes said first and second pads, and a third interconnecting structure over said passivation layer and over said first and second pads.

Abstract: The present disclosure is directed to a semiconductor die having a chip outline boundary, a die seal, a row of input/output contact pads separated from the chip outline boundary by the die seal, a first row of solder bump connections positioned between the row of input/output contact pads and the die seal, and a second row of solder bump connections separated from the first row of solder bump connections by the row of input/output contact pads.

Abstract: An object of the present invention is to provide a structure of a thin film circuit portion and a method for manufacturing a thin film circuit portion by which an electrode for connecting to an external portion can be easily formed under a thin film circuit. A stacked body including a first insulating film, a thin film circuit formed over one surface of the first insulating film, a second insulating film formed over the thin film circuit, an electrode formed over the second insulating film, and a resin film formed over the electrode, is formed. A conductive film is formed adjacent to the other surface of the first insulating film of the stacked body to be overlapped with the electrode. The conductive film is irradiated with a laser.

Abstract: A method for forming an interconnect structure with nanocolumnar intermetal dielectric is described involving the construction of an interconnect structure using a solid dielectric, and introducing a regular array of vertically aligned nanoscale pores through stencil formation and etching to form a hole array and subsequently pinching off the tops of the hole array with a cap dielectric. Variations of the method and means to construct a multilevel nanocolumnar interconnect structure are also described.

Abstract: An integrated circuit device includes a dynamic array section that includes a gate electrode level region that has linear conductive features defined in accordance with a gate level virtual grate. Each of at least three consecutively positioned virtual lines of the gate level virtual grate has at least one linear conductive feature defined thereon. A first virtual line of the at least three virtual lines has two linear conductive segments defined thereon and separated by a first end-to-end spacing. A second virtual line of the at least three virtual lines has another two linear conductive segments defined thereon and separated by a second end-to-end spacing. A size of the first end-to-end spacing as measured along the first virtual line is substantially equal to a size of the second end-to-end spacing as measured along the second virtual line.

Abstract: A semiconductor structure having a transistor and a thermo electronic structure. The transistor has a control electrode for controlling a flow of carriers through a semiconductor layer between a pair of electrodes. The thermo electronic structure has a first portion disposed on at least one of the pair of electrodes and a second portion disposed over a region of the semiconductor layer proximate the control electrode between the control electrode and said at least one of the pair of electrode. The thermo electronic structure extends from the first portion to the second portion for removing heat generated heat from said region in the semiconductor layer.

Abstract: Embodiments of the invention describe compact memory arrays. In one embodiment, the memory cell array includes first, second, and third gate lines disposed over a substrate, the second gate lines are disposed between the first and the third gate lines. The first, the second, and the third gate lines form adjacent gate lines of the memory cell array. The memory cell array further includes first metal lines disposed over the first gate lines, the first metal lines coupled to the first gate lines; second metal lines disposed over the second gate lines, the second metal lines coupled to the second gate lines; and third metal lines disposed over the third gate lines, the third metal lines coupled to the third gate lines. The first metal lines, the second metal lines and the third metal lines are disposed in different metallization levels.

Abstract: A three-dimensional semiconductor device includes a semiconductor substrate, a plurality of conductive layers and insulating layers, and a plurality of contacts. The plurality of conductive layers and insulating layers are stacked alternately above the semiconductor substrate. The plurality of contacts extend in a stacking direction of the plurality of conductive layers and insulating layers. The plurality of conductive layers form a stepped portion having positions of ends of the plurality of conductive layers gradually shifted from an upper layer to a lower layer. The plurality of contacts are connected respectively to each of steps of the stepped portion. The stepped portion is formed such that, at least from an uppermost conductive layer to a certain conductive layer, the more upwardly the conductive layer is located, the broader a width of the step is.

Abstract: A method of fabricating an array substrate for a display device includes: forming a buffer layer on a substrate having a pixel region; sequentially forming a gate electrode of impurity-doped polycrystalline silicon, a gate insulating layer and an active layer of intrinsic polycrystalline silicon on the buffer layer in the pixel region; forming an interlayer insulating layer of an inorganic insulating material on the active layer; sequentially forming a source barrier pattern, a source ohmic contact layer and a source electrode on the interlayer insulating layer, sequentially forming a drain barrier pattern, a drain ohmic contact layer and a drain electrode on the interlayer insulating layer, and sequentially forming a first dummy pattern, a second dummy pattern and a data line on the interlayer insulating layer; forming a first passivation layer on a surface of the interlayer insulating layer including the source electrode, the drain electrode and the data line formed thereon; forming a gate line on the first

Abstract: A semiconductor device includes a first metal layer disposed on a semiconductor substrate; an insulating layer disposed on the first metal layer; and a second metal layer disposed on the insulating layer and having an electrode pad surface exposed to the outside, wherein a recess is disposed in the insulating layer and the second metal layer; and at least the second metal layer is disposed in the recess of the insulating layer.

Abstract: A stacked non-volatile memory device comprises a plurality of bit line and word line layers stacked on top of each other. The bit line layers comprise a plurality of bit lines that can be formed using advanced processing techniques making fabrication of the device efficient and cost effective. The device can be configured for NAND operation.

Abstract: There is provided a technique capable of reducing a layout area of a standard cell configuring a digital circuit even under a circumstance that a new layout rule introduced in accordance with microfabrication of a MISFET is provided. For example, a protruding wiring PL1A protrudes from a power supply wiring L1A at each corner of both ends of a standard cell CL toward an inside of the standard cell CL (in a Y direction), and a bent portion BD1A which is bent from the protruding wiring PL1A in an X direction is formed. And, this bent portion BD1A and a p-type semiconductor region PDR are connected to each other via a plug PLG.

Abstract: A multilevel interconnect structure in a semiconductor device includes a first insulating layer formed on a semiconductor wafer, a Cu interconnect layer formed on the first insulating layer, a second insulating layer formed on the Cu interconnect layer, and a metal oxide layer formed at an interface between the Cu interconnect layer and the second insulating layer. The metal oxide layer is formed by immersion-plating a metal, such as Sn or Zn, on the Cu interconnect layer and then heat-treating the plated layer in an oxidizing atmosphere.

Abstract: A memory cell for reducing the cost and complexity of modifying a revision identifier (ID) or default register values associated with an integrated circuit (IC) chip, and a method for manufacturing the same. The cell, which may be termed a “Meta-Memory Cell” (MMCEL), is implemented on metal layers only and utilizes a dual parallel metal ladder structure that traverses and covers each metal and via layer from the bottom to the top of the metal layer structure of the chip. One of the metal ladders is connected to a power supply at the bottom metal layer, corresponding to a logic 1, and another metal ladder is connected to ground at the bottom metal layer, corresponding to a logic 0. The output of the MMCEL can thus be inverted at any metal or via layer and can be inverted as often as required. Significant cost savings are achieved because a revision ID or default register bits may be modified by altering only those metal layers where design changes are necessary.

Abstract: A method and layout for forming word line decoder devices and other devices having word line decoder cells provides for forming metal interconnect layers using non-DPL photolithography operations and provides for stitching distally disposed transistors using a lower or intermediate metal layer or a subjacent conductive material. The transistors may be disposed in or adjacent longitudinally arranged word line decoder or other cells and the conductive coupling using the metal or conductive material lowers gate resistance between transistors and avoids RC signal delays.

Abstract: An integrated circuit device includes a plurality of dynamic array sections, each of which includes three or more linear conductive segments formed within its gate electrode level in a parallel manner to extend lengthwise in a first direction. An adjoining pair of dynamic array sections are positioned to have co-located portions of outer peripheral boundary segments extending in the first direction. At least one of the linear conductive segments within the gate electrode level of a given dynamic array section is a non-gate linear conductive segment that does not form a gate electrode of a transistor. The non-gate linear conductive segment of either of the adjoining pair of dynamic array sections spans the co-located portion of outer peripheral boundary segment toward the other of the adjoining pair of dynamic array sections, and is contained within gate electrode level manufacturing assurance halo portions of the adjoining pair of dynamic array sections.

Abstract: An electronic device includes an active layer located over a substrate with the active layer having a logic circuit and an eDRAM cell. The electronic device also includes a first metallization level located over the active layer that provides logic interconnects and metal capacitor plates. The logic interconnects are connected to the logic circuit and the metal capacitor plates are connected to the eDRAM cell. The electronic device additionally includes a second metallization level located over the first metallization level that provides an interconnect connected to at least one of the logic interconnects, and a bit line that is connected to the eDRAM cell. A method of manufacturing an electronic device is also included.

Abstract: A method of forming a memory device includes forming a first interlayer insulating layer on a semiconductor substrate, forming a first electrode in the first interlayer insulating layer, the first electrode having a top surface of a rectangular shape extending in a first direction, and forming a variable resistance pattern on the first electrode, the variable resistance pattern having a bottom surface of a rectangular shape extending in a second direction crossing the first direction, the bottom surface of the variable resistance pattern contacting the first electrode, wherein the area of contact between the lower electrode and the variable resistance pattern is substantially equal to a multiplication of a minor axis length of a top surface of the first electrode and a minor axis length of a bottom surface of the variable resistance pattern.

Abstract: A memory array including a diffusion layer, a poly layer, a metal one layer, a metal two layer, and a contact. The diffusion layer comprises diffusion lines extending in a first direction. The poly layer comprises poly lines extending in the first direction and being arranged on top of and insulated from the diffusion layer. The metal one layer comprises metal one lines extending in the first direction and being arranged on top of and insulated from the poly layer. The metal two layer comprises a metal two line extending in the first direction and being arranged on top of and insulated from the metal one layer. The contact extends through the poly layer, and connects a metal one line to a diffusion line. A poly line further extends in a second direction to bend around the contact such that a predetermined distance separates the poly lines from the contact.

Abstract: A semiconductor device includes conductive features that are each defined within any one gate level channel that is uniquely associated with and defined along one of a number of parallel gate electrode tracks. The conductive features form gate electrodes of first and second PMOS transistor devices, and first and second NMOS transistor devices. The gate electrodes of the first PMOS and first NMOS transistor devices extend along a first gate electrode track. The gate electrodes of the second PMOS and second NMOS transistor devices extend along a second gate electrode track. A first set of interconnected conductors electrically connect the gate electrodes of the first PMOS and second NMOS transistor devices. A second set of interconnected conductors electrically connect the gate electrodes of the second PMOS and first NMOS transistor devices. The first and second sets of interconnected conductors traverse across each other within different levels of the semiconductor device.

Abstract: Some embodiments include cross-point memory structures. The structures may include a line of first electrode material extending along a first horizontal direction, a multi-sided container of access device materials over the first electrode material, a memory element material within the multi-sided container, and a line of second electrode material over the memory element material and extending along a second horizontal direction that is orthogonal to the first horizontal direction. Some embodiments include methods of forming memory arrays. The methods may include forming a memory cell stack over a first electrode material, and then patterning the first electrode material and the memory cell stack into a first set of spaced lines extending along a first horizontal direction. Spaced lines of second electrode material may be formed over the first set of spaced lines, and may extend along a second horizontal direction that is orthogonal to the first horizontal direction.

Abstract: In one embodiment of the present invention, a method for connecting a plurality of bit lines to sense circuitry comprises providing a plurality of bit lines extending from a memory array in a first metal layer. The plurality of bit lines are separated from each other by an average spacing x in a first region of the first metal layer. The method further comprises elevating a portion of the plurality of bit lines into a second metal layer overlying the first metal layer. The elevated bit lines are separated from each other by an average spacing y in the second metal layer, with y>x. The method further comprises extending a portion of the plurality of bit lines into a second region of the first metal layer. The extended bit lines are separated from each other by an average spacing z in the second region of the first metal layer, with z>x. The method further comprises connecting a bit line in the second metal layer and a bit line in the first metal layer to the sense circuitry.

Abstract: CMOS inverters are included in a standard cell. Power supply lines are electrically connected to CMOS inverters, and include lower layer interconnects and upper layer interconnect. Lower layer interconnects extend along a boundary of standard cells adjacent to each other and on the boundary. Upper layer interconnects are positioned more inside in standard cell than lower layer interconnects, as viewed from a plane. CMOS inverters are electrically connected through upper layer interconnects to lower layer interconnects. Thus, a semiconductor device is obtained that can achieve both higher speeds and higher integration.

Abstract: A first impurity diffusion layer in a memory cell portion and a second impurity diffusion layer in a peripheral circuit portion are provided in a surface of a semiconductor substrate and having upper faces substantially flush with each other. First and second insulating films are formed to cover the upper faces of the impurity diffusion layers, and having substantially uniform film thicknesses. A first metal plug is formed in the insulating films, and connected to the first impurity diffusion layer. A second metal plug is formed in the first insulating film, to have a lower height than the first metal plug, and is connected to the second impurity diffusion layer. A first metal interconnection is connected to an upper end portion of the first metal plug, and having an upper face embedded in and flush with the second insulating film. A second metal interconnection is connected to an upper end portion of the second metal plug, and having an upper face embedded in and flush with the second insulating film.

Abstract: A semiconductor device includes an insulating film formed on a substrate; an interconnect layer including a plurality of interconnects formed in the insulating film; and a pad formed on the insulating film. In a region containing at least a part of a section below the pad, a narrow spacing region is formed, where a spacing between the adjacent interconnects is shorter than that in a section outside the region containing at least a part of the section below the pad.

Abstract: An object of the invention is to provide a display device which can be manufactured with usability of a material improved and with a manufacturing step simplified and to provide a manufacturing technique thereof. One feature of a light emitting display device of the present invention is to comprise a gate electrode formed over a substrate having an insulating surface with a substance having a photocatalytic function therebetween, a gate insulating layer formed over the gate electrode, a semiconductor layer and a first electrode formed over the gate insulating layer, a wiring layer formed over the semiconductor layer, a partition wall covering an edge portion of the first electrode and the wiring layer, an electroluminescent layer over the first electrode, and a second electrode over the electroluminescent layer, wherein the wiring layer covers the edge portion of the first electrode.

Abstract: A rectangular-shaped interlevel connection structure is defined to electrically connect a first structure in a first chip level with a second structure in a second chip level. The rectangular-shaped interlevel connection structure is defined by an as-drawn cross-section having at least one dimension larger than a corresponding dimension of either the first structure, the second structure, or both the first and second structures. A dimension of the rectangular-shaped interlevel connection structure can exceed a normal maximum size in one direction in exchange for a reduced size in another direction. The rectangular-shaped interlevel connection structure can be placed in accordance with a gridpoint of a virtual grid defined by two perpendicular sets of virtual lines. Also, the first and/or second structures can be spatially oriented and/or placed in accordance with one or both of the two perpendicular sets of virtual lines.

Abstract: Example embodiments relate to a three-dimensional semiconductor memory device including an electrode structure on a substrate, the electrode structure including at least one conductive pattern on a lower electrode, and a semiconductor pattern extending through the electrode structure to the substrate. A vertical insulating layer may be between the semiconductor pattern and the electrode structure, and a lower insulating layer may be between the lower electrode and the substrate. The lower insulating layer may be between a bottom surface of the vertical insulating layer and a top surface of the substrate. Example embodiments related to methods for fabricating the foregoing three-dimensional semiconductor memory device.

Abstract: A technique which reduces the influence of external noise such as crosstalk noise in a semiconductor device to prevent a circuit from malfunctioning. A true signal wire and a bar signal wire which are susceptible to noise and part of an input signal line to a level shifter circuit, and shield wires for shielding these signal wires are laid on an I/O cell. Such I/O cells are placed side by side to complete a true signal wire connection and a bar signal wire connection. These wires are arranged in a way to pass over a plurality of I/O cells and are parallel to each other or multilayered.

Abstract: A semiconductor die has rows of bond pads along the edges of a major surface. The corners of the die are designated as keep out areas, with design layout rules prohibiting a probe-able bond pad from being placed in the keep out areas so that a minimum distance may be maintained between distal ends of adjacent rows of bond pads (i.e., bond pads along adjacent edges). The bond pads of each row have IO pad areas that are aligned with each other and IO probe areas that are aligned with each other. A generally L-shaped bond pad includes a first, vertical part that extends inwardly from an edge of the semiconductor die and a second, horizontal part connected to the vertical part. The L-shaped bond pad may be placed between a last bond pad in a row and a corner keep out area, and the second part of the L-shaped bond pad extends into the corner keep out area.

Abstract: A structure for reducing electromigration cracking and extrusion effects in semiconductor devices includes a first metal line formed in a first dielectric layer; a cap layer formed over the first metal line and first dielectric layer; a second dielectric layer formed over the cap layer; and a void formed in the second dielectric layer, stopping on the cap layer, wherein the void is located in a manner so as to isolate structural damage due to electromigration effects of the first metal line, the effects including one or more of extrusions of metal material from the first metal line and cracks from delamination of the cap layer with respect to the first dielectric layer.

Abstract: In a high frequency amplifying MOSFET having a drain offset region, the size is reduced and the on-resistance is decreased by providing conductor plugs 13 (P1) for leading out electrodes on a source region 10, a drain region 9 and leach-through layers 3 (4), to which a first layer wirings 11a, 11d (M1) are connected and, further, backing second layer wirings 12a to 12d are connected on the conductor plugs 13 (P1) to the first layer wirings 11s, 11d (M1).

Abstract: A design structure is provided for interconnect structures containing various capping materials for electrical fuses and other related applications. The structure includes a first interconnect structure having a first interfacial structure and a second interconnect structure adjacent to the first structure. The second interconnect structure has second interfacial structure different from the first interfacial structure.

Abstract: A semiconductor device wherein destruction of a sealing ring caused by cracking of an interlayer dielectric film is difficult to occur, as well as a method for manufacturing the semiconductor device, are provided. A first laminate comprises first interlayer dielectric films having a first mechanical strength. A second laminate comprises second interlayer dielectric films having a mechanical strength higher than the first mechanical strength. A first region includes first metallic layers and vias provided within the first laminate. A second region includes second metallic layers and vias provided within the second laminate. When seen in plan, the second region overlaps at least a part of the first region, is not coupled with the first region by vias, and sandwiches the second interlayer dielectric film between it and the first region.

Abstract: A semiconductor memory device comprises a semiconductor substrate; a cell array block formed on the semiconductor substrate and including plural stacked cell array layers each comprising a plurality of first lines, a plurality of second lines crossing the plurality of first lines, and memory cells connected at intersections of the first and second lines between both lines; and a plurality of contact plugs extending in the stack direction of the cell array layers to connect between the first lines, between the second lines, between the first or second line and the semiconductor substrate, or between the first or second line and another metal line, in the cell array layers. The first or second line in a certain one of the cell array layers has a contact connector making contact with both sides of the contact plug.

Abstract: A semiconductor memory device includes first and second memory cells each including a variable resistance element and a diode and having a pillar shape, and an insulating layer provided between the first memory cell and the second memory cell and including a void. A central portion of the diode has a smaller width than widths of upper and lower portions of the diode.

Abstract: A finFET structure is made by forming a fin (14), followed by a gate stack of gate dielectric (16), metal gate layer (18), polysilicon layer (20) and silicon-germanium layer (22). The gate stack is then patterned, and source and drain implants formed in the fin (14) away from the gate. The silicon germanium layer (22) is selectively etched away, a metal deposited over the gate, and silicidation carried out to convert the full thickness of the polysilicon layer (20) at the top of the fin. A region of unreacted polysilicon (38) may be left at the base of the fin and across the substrate.

Abstract: The image sensor includes a substrate; a wiring structure formed on a front side of the substrate and including a plurality of wiring layers and a plurality of insulating films; a first well formed within the substrate and having a first conductivity type; and a first metal wiring layer directly contacting a backside of the substrate and configured to apply a first well bias to the first well.

Abstract: Some embodiments include cross-point memory structures. The structures may include a line of first electrode material extending along a first horizontal direction, a multi-sided container of access device materials over the first electrode material, a memory element material within the multi-sided container, and a line of second electrode material over the memory element material and extending along a second horizontal direction that is orthogonal to the first horizontal direction. Some embodiments include methods of forming memory arrays. The methods may include forming a memory cell stack over a first electrode material, and then patterning the first electrode material and the memory cell stack into a first set of spaced lines extending along a first horizontal direction. Spaced lines of second electrode material may be formed over the first set of spaced lines, and may extend along a second horizontal direction that is orthogonal to the first horizontal direction.

Abstract: Briefly, in accordance with one or more embodiments, multilayer memory device, comprising a lower deck and an upper deck disposed on the lower deck, the decks comprising one or more memory cells coupled via one or more contacts. An isolation layer is disposed between the upper deck, and one or more contacts are formed between the upper deck and the lower deck to couple one or more of the contact lines of the upper deck with one or more contact lines of the lower deck.

Abstract: A multi-chip device which includes a plurality of integrated circuit die disposed one over another. Each integrated circuit die includes one or a plurality of bond pads. One or a plurality of conductors are disposed to electrically couple the bond pads of vertically adjacent integrated circuit die. Each conductor is designed, calculated, specified and/or predetermined to have a length so as to behave as a segment in a multi-drop transmission line. The multi-drop transmission line may be terminated at one end or utilized in a flow-through approach. In one embodiment, an integrated circuit die may be horizontally offset with respect to a vertically adjacent integrated circuit die to expose the periphery region. In another embodiment, each integrated circuit die may be stacked and aligned in a vertical column. In this embodiment, a spacer such as a thermally conductive spacer is disposed between each integrated circuit die in the stack.

Abstract: A semiconductor device is the semiconductor device which includes more than one field effect transistor having a gate electrode to which an electrical interconnect wire is connected and a gate insulation film with a thickness of 6.0 nm or less and which comprises a first transistor group made up of a plurality of field effect transistors that are the same in thickness of gate insulation film, a second transistor group made up of a plurality of field effect transistors that are the same in thickness of gate insulation film with the thickness of gate insulation film being less than the thickness of the gate insulation film of the first transistor group, and a semiconductor substrate on which the first and second transistor groups are mounted together in a mixed manner, wherein an antenna ratio which is a ratio of the area of a wire to the gate area of a gate electrode is such that the maximum value of the second transistor group is greater than the maximum value of the first transistor group.