Abstract: Some embodiments relate to an image sensor pixel comprising a transfer gate formed on a first surface of a semiconductor substrate, a floating diffusion formed in the first surface of the semiconductor substrate, and a buried-well vertically pinned photodiode having a charge accumulation/storage region disposed substantially beneath the transfer gate. The transfer gate is spaced away from the floating diffusion such that an intervening semiconductor region provides a potential barrier to charge flow from beneath the transfer gate to the floating diffusion. The transfer gate is operable to control a vertical pump gate to selectively transfer charge from the charge accumulation/storage region to the floating diffusion by pumping charge from the buried charge accumulation/storage region underlying the transfer gate, over the potential barrier, and out to the floating diffusion, such that full charge transfer can be achieved without overlapping the edge of the transfer gate with the floating diffusion.

Abstract: A minute transistor is provided. A transistor with low parasitic capacitance is provided. A transistor having high frequency characteristics is provided. A semiconductor device including the transistor is provided. The semiconductor device includes an oxide semiconductor; a second insulator; a first conductor and a first insulator that are embedded in the second insulator; a second conductor; a third conductor; and a third insulator covering the oxide semiconductor. The oxide semiconductor includes a region where an angle formed between a plane that is parallel to a bottom surface of the oxide semiconductor and the side surface of the oxide semiconductor is greater than or equal to 30° and less than or equal to 60°.

Abstract: A method for manufacturing an image sensor includes, for each of a plurality of photosensitive pixels of the image sensor, forming a trench in a semiconductor substrate of the image sensor, and depositing temporary transfer gate material in and above the trench. The method further includes, after the step of depositing temporary transfer gate material, high-temperature annealing at least a portion of the semiconductor substrate. In addition, the method includes, after the step of high-temperature annealing, (a) removing the temporary transfer gate material, thereby reopening the trench, (b) depositing a passivation lining, having a high-k dielectric, in the reopened trench, and (c) depositing metal on the high-k dielectric passivation lining to form a metal vertical transfer gate in the trench and extending above the trench.

Abstract: An optical sensor assembly is provided in which a dark mirror coating is used to suppress stray light in the form of both unwanted reflections from non-optically active regions of the sensor assembly surface and unwanted transmission of light into the surface region of the sensor assembly. The sensor assembly includes an image sensor positioned in a substrate adjacent to substrate surface areas that are not optically active. A dark mirror coating covering those surface areas significantly reduces reflections from non-optically active surface regions and improves image sensor performance in terms of signal-to-noise ratio and reduction in the appearance of “ghost” images, in turn enhancing the accuracy and precision of the sensor. The dark mirror coating may in the alternative, or in addition, be positioned underneath an optical filter, depending on the structure, material, and requirements of a particular sensor assembly.

Abstract: An image sensor includes a first voltage source that supplies a first voltage and a plurality of pixels supplied with the first voltage. The pixel includes a photoelectric conversion unit that photoelectrically converts incident light, an accumulation unit to which an electric charge resulting from photoelectric conversion by the photoelectric conversion unit is transferred and accumulated, a transfer unit that transfers the electric charge from the photoelectric conversion unit to the accumulation unit; a second voltage source that supplies a second voltage, and a supply unit that supplies the transfer unit with a transfer signal based on either the first voltage supplied by the first voltage source or the second voltage supplied by the second voltage source.

Abstract: A light receiving element according to an embodiment of the present disclosure includes a plurality of pixels, a photoelectric conversion layer common to the plurality of pixels, a first electrode layer provided on side of a light incident surface of the photoelectric conversion layer, and a light-shielding section embedded between the plurality of pixels adjacent to each other of the first electrode layer.

Abstract: Aspects of the present disclosure relate to systems and methods for structured light (SL) depth systems. A depth finding system includes one or more processors and a memory, coupled to the one or more processors, includes instructions that, when executed by the one or more processors, cause the system to capture a plurality of frames based on transmitted pulses of light, where each of the frames is captured by scanning a sensor array after a respective one of the pulses has been transmitted, and generate an image depicting reflections of the transmitted light by combining the plurality of frames, where each of the frames provides a different portion of the image.

Abstract: To reduce the influence of noise in the imaging device configured with the plurality of semiconductor chips. A first semiconductor chip includes a signal input transistor in which an input signal which is a signal corresponding to incident light is input to a control terminal, a reference input transistor which forms a differential pair along with the signal input transistor and in which a reference signal is input to a control terminal, a first signal line which delivers a change in a current flowing in one of the signal input transistor and the reference input transistor as a result of comparison between the input signal and the reference signal when the current is changed in accordance with a difference between the input signal and the reference signal, and a first pad which is electrically connected to the first signal line.

Abstract: A display panel includes a plurality of scan lines and connection lines. The plurality of scan lines are spaced from each other. The connection lines are connected to end portions of the plurality of scan lines. The connection lines are formed of intrinsic silicon. By having the connection lines that are formed of intrinsic silicon connected with the end portions of all the scan lines, due to intrinsic silicon being almost electrically non-conductive, this does not affect stage by stage activation of the scan lines and provides a way of power consumption by large resistivity of intrinsic silicon for preventing static electricity on end portions of the scan lines thereby overcoming the issue of static electricity being easily caused on the end portions of the scan lines and thus enhancing product quality.

Abstract: A CMOS imaging system with increased charge storage of pixels yet decreased physical size, kTC noise and active area. A storage node is connected to the transfer gate and provides a storage node for a pixel, allowing for kTC noise reduction prior to readout. The pixel may be operated with the shutter gate on during the integration period to increase the amount of time for charge storage by a pixel.

Abstract: An imaging device for improving the determining speed of the comparator and reducing power consumption. The comparator includes a differential input circuit that operates with a first power supply voltage, the differential input circuit that outputs a signal when an input signal is higher than a reference signal in voltage, a positive feedback circuit that operates with a second power supply voltage lower than the first power supply voltage and accelerates transition speed when a compared result signal indicating a compared result between the input signal and the reference signal in voltage, is inverted, based on the output signal of the differential input circuit, and a voltage conversion circuit that converts the output signal of the differential input circuit into a signal corresponding to the second power supply voltage.

Abstract: The present technology relates to a solid-state imaging apparatus and an electronic apparatus that makes it possible to improve coloration and improve image quality. The solid-state imaging apparatus is formed so that, in a pixel array unit in which combinations of a first pixel corresponding to a color component of a plurality of color components and a second pixel having higher sensitivity to incident light as compared with the first pixel are two-dimensionally arrayed, a first electrical barrier formed between a first photoelectric conversion unit and a first unnecessary electric charge drain unit in the first pixel, and a second electrical barrier formed between a second photoelectric conversion unit and a second unnecessary electric charge drain unit in the second pixel have different heights, respectively. The present technology can be applied to, for example, a CMOS image sensor.

Abstract: An image sensor with a pinned photodiode includes a photodiode formed in a substrate by implanting dopants of a first type through one or more dielectric layers formed over the substrate. A pinning layer for the photodiode may be formed by implanting dopants of a second type through the same one or more dielectric layers. The pinning layer may be formed over a photodiode region of the substrate. The concentration of dopants of the second type may have a maximum value in dielectric layers over the photodiode that exceeds the concentration of dopants of the second type in the substrate below. The photodiode and pinning layer may both be formed by implanting ions of the first and second type respectively through a dielectric layer formed after etching away a portion of another dielectric layer, having a different thickness, and having different optical transmission properties than the another dielectric layer.

Abstract: Various embodiments of the present technology may comprise methods and apparatus for a CCD image sensor. The image sensor may comprise a center channel disposed along a horizontal center line of the pixel array for collecting and transferring charge. The center channel is electrically coupled to a lateral overflow drain. In various embodiments, the image sensor may comprise a light shield under a gap between neighboring microlenses, such as a gap along the center line, to block light, such as to maintain a uniform, spatial sampling pattern across the device. In various embodiments, the image sensor may comprise a barrier region disposed between the center channel and the lateral overflow drain, for example to prevent charge from the lateral overflow drain being injected back into the center channel and adjacent pixels.

Abstract: A solid-state image pickup device 1 according to the present invention includes a semiconductor substrate 2 on which a pixel 20 composed of a photodiode 3 and a transistor is formed. The transistor comprising the pixel 20 is formed on the surface of the semiconductor substrate, a pn junction portion formed between high concentration regions of the photodiode 3 is provided within the semiconductor substrate 2 and a part of the pn junction portion of the photodiode 3 is extended to a lower portion of the transistor formed on the surface of the semiconductor substrate 2. According to the present invention, there is provided a solid-state image pickup device in which a pixel size can be microminiaturized without lowering a saturated electric charge amount (Qs) and sensitivity.

Abstract: Deep trench isolation (DTI) structures and methods of forming the same are provided. A method includes forming a plurality of photosensitive regions in a substrate. A recess is formed in the substrate, the substrate comprising a first semiconductor material, the recess being interposed between adjacent photosensitive regions. The recess is enlarged by removing a damaged layer of the substrate along sidewalls of the recess, thereby forming an enlarged recess. An epitaxial region is formed on sidewalls and a bottom of the enlarged recess, at least a portion of the epitaxial region comprising a second semiconductor material, the second semiconductor material being different from the first semiconductor material. A dielectric region is formed on the epitaxial region, the epitaxial region extending along a sidewall of the dielectric region.

Abstract: A display device includes: a pixel array unit with pixel circuits disposed in matrix form, the pixel circuit including a driving transistor, an electro-optic element, a storage capacitor, and a sampling transistor, with the electro-optic element emitting light by generating a driving current based on information stored in the storage capacitor at the driving transistor to be applied to the electro-optic element; and a control unit, of which the output stage includes a buffer transistor, to output a pulse signal for driving the pixel array unit from the buffer transistor; wherein the pixel array unit and the control unit are formed with long laser beam irradiation to be scanned in the vertical direction or horizontal direction; and wherein with the control unit, the size of the buffer transistor is equal to or greater than the pixel pitch in the scanning direction of the laser beam.

Abstract: A nonvolatile memory cell includes a semiconductor substrate, a first OD region, a second OD region for forming an erase gate region, and a trench isolation region separating the first OD region from the second OD region. A select transistor is disposed on the first OD region. A floating gate transistor is serially connected to the select transistor and is disposed on the first OD region. The floating gate transistor includes a floating gate overlying the first OD region. A floating gate extension continuously extends from the floating gate to the second OD region. A shallow junction diffusion region is situated directly under the floating gate extension within the second OD region.

Abstract: A junction field-effect transistor (JFET) with a gate region that includes two separate sub-regions having material of different conductivity types and/or a Schottky junction that substantially suppresses gate current when the gate junction is forward-biased, as well as complementary circuits that incorporate such JFET devices.

Abstract: A CMOS imaging system with increased charge storage of pixels yet decreased physical size, kTC noise and active area. A storage node is connected to the transfer gate and provides a storage node for a pixel, allowing for kTC noise reduction prior to readout. The pixel may be operated with the shutter gate on during the integration period to increase the amount of time for charge storage by a pixel.

Abstract: An object of the present invention is to reduce capacitance of a charge accumulation part (floating diffusion) of each pixel unit. In an imaging device, in addition to a plurality of first switching transistors for coupling a plurality of coupling wires extending in the column direction, a second switching transistor is provided between each of the coupling wires and a floating diffusion in each pixel unit. Preferably, the gate of the first switching transistor and the gate of the second switching transistor are electrically coupled to each other.

Abstract: A solid-state image pickup device 1 according to the present invention includes a semiconductor substrate 2 on which a pixel 20 composed of a photodiode 3 and a transistor is formed. The transistor comprising the pixel 20 is formed on the surface of the semiconductor substrate, a pn junction portion formed between high concentration regions of the photodiode 3 is provided within the semiconductor substrate 2 and a part of the pn junction portion of the photodiode 3 is extended to a lower portion of the transistor formed on the surface of the semiconductor substrate 2. According to the present invention, there is provided a solid-state image pickup device in which a pixel size can be microminiaturized without lowering a saturated electric charge amount (Qs) and sensitivity.

Abstract: The present disclosure relates to a solid-state image capturing element, a manufacturing method therefor, and an electronic device, which are capable of controlling a thickness of a depletion layer. The solid-state image capturing element includes pixels each in which a photoelectric conversion film configured to perform photoelectric conversion on incident light and a fixed charge film configured to have a predetermined fixed charge are stacked on a semiconductor substrate. The technology of the present disclosure can be applied to, for example, back surface irradiation type solid-state image capturing elements, image capturing devices such as digital still cameras or video cameras, mobile terminal devices having an image capturing function, and electronic devices using a solid-state image capturing element as an image capturing unit.

Abstract: An image sensor may include: a substrate including a photoelectric conversion element; a first interlayer dielectric layer formed over the photoelectric conversion element; a channel layer including a first region and a second region, the first region being formed in an opening passing through the first interlayer dielectric layer, with a portion of the first region contacting the photoelectric conversion element, and the second region being formed over the first interlayer dielectric layer; a transfer transistor formed over the first region of the channel layer, the transfer transistor including a transfer gate which gapfills the opening; and a reset transistor including a reset gate formed over the second region of the channel layer.

Abstract: In various example embodiments, the inventive subject matter is an image sensor and methods of formation of image sensors. In an embodiment, the image sensor comprises a semiconductor substrate and a plurality of pixel regions. Each of the pixel regions includes an optically sensitive material over the substrate with the optically sensitive material positioned to receive light. A pixel circuit for each pixel region is also included in the sensor. Each pixel circuit comprises a charge store formed on the semiconductor substrate and a read out circuit. A non-metallic contact region is between the charge store and the optically sensitive material of the respective pixel region, the charge store being in electrical communication with the optically sensitive material of the respective pixel region through the non-metallic contact region.

Abstract: Apparatus, systems, and methods are described to assist in reducing dark current in an active pixel sensor. In various embodiments, a potential barrier arrangement is configured to block the flow of charge carriers generated outside a photosensitive region. In various embodiments, a potential well-potential barrier arrangement is formed to direct charge carriers away from the photosensitive region during an integration time.

Abstract: An image sensor comprises a first semiconductor substrate on which a plurality of photoelectric conversion elements are arranged, a second semiconductor substrate on which a plurality of storage devices each for storing pixel signals are arranged; and a plurality of connection units configured to electrically connect the photodiodes and the storage devices, wherein the plurality of storage devices are arranged in correspondence with the plurality of photoelectric conversion elements.

Abstract: A solid-state imaging device according to the present disclosure includes pixels arranged two-dimensionally, each of the pixels including: a metal electrode; a photoelectric conversion layer that is on the metal electrode and converts light into an electrical signal; a transparent electrode on the photoelectric conversion layer; an electric charge accumulation region that is electrically connected to the metal electrode and accumulates electric charges from the photoelectric conversion layer; an amplifier transistor that applies a signal voltage according to an amount of the electric charges in the electric charge accumulation region; and a reset transistor that resets electrical potential of the electric charge accumulation region, in which the reset transistor includes a gate oxide film thicker than a gate oxide film of the amplifier transistor.

Abstract: In an embodiment, a fluid ejection device includes a thin-film layer formed over a substrate. A primer layer is formed over the thin-film layer, and a chamber layer is formed over the primer layer that defines a fluidic channel leading to a firing chamber. The fluid ejection device includes a slot that extends through the substrate and into the chamber layer through an ink feed hole in the thin-film layer. The fluid ejection device also includes a particle tolerant extension of the primer layer that protrudes into the slot. In some implementations, the particle tolerant primer layer extension extends across a full width of the slot.

Abstract: A circuit board element includes a glass substrate, a first dielectric layer, and a first patterned metal layer. The glass substrate has an edge. The first dielectric layer is disposed on the glass substrate and has a central region and an edge region. The edge region is in contact with the edge of the glass substrate, and the thickness of the central region is greater than the thickness of the edge region. The first patterned metal layer is disposed on the glass substrate and in the central region of the first dielectric layer.

Abstract: An image sensor may include an array of image sensor pixels. Each image sensor pixel may have signal storage capabilities implemented through a write-back supply line and a control transistor for the supply line. Each image sensor pixel may output pixel values over column lines to switching circuitry. The switching circuitry may route the pixel values to signal processing circuitry. The signal processing circuitry may perform analog and/or digital processing operations utilizing analog circuits or pinned diode devices for image signal processing on the pixel values to output processed pixel values. The processing circuitry may send the processed pixel values back to the array. This allows the array to act as memory circuitry to support processing operations on processing circuitry in close proximity to the array. Configured this way, signal processing can be performed in close proximity to the array without having to move pixel signals to peripheral processing circuitry.

Abstract: A method of clocking an image sensor which eliminates well bounce effects caused by global current flow in large image sensors during frame readout and line transfer is described. During charge transfer operations in which voltages are applied to VCCD gate contacts that are adjacent to the photodiodes, a compensating voltage may be applied to the lightshield that is associated with, and at least partially formed over the photodiode. Depending on polarity, the compensating lightshield pulse allows holes to locally flow from under the VCCD gates to the photodiode P+ pinning region or vice-versa, and in such a manner to eliminate the global flow of hole current. Lightshields may also be biased during electronic shuttering operations.

Abstract: A solid-state imaging device according to the present disclosure includes pixels arranged two-dimensionally, each of the pixels including: a metal electrode; a photoelectric conversion layer that is on the metal electrode and converts light into an electrical signal; a transparent electrode on the photoelectric conversion layer; an electric charge accumulation region that is electrically connected to the metal electrode and accumulates electric charges from the photoelectric conversion layer; an amplifier transistor that applies a signal voltage according to an amount of the electric charges in the electric charge accumulation region; and a reset transistor that resets electrical potential of the electric charge accumulation region, in which the reset transistor includes a gate oxide film thicker than a gate oxide film of the amplifier transistor.

Abstract: Provided are an image sensor and a method of manufacturing method of manufacturing the image sensor. The image sensor includes a substrate, photoelectric transducers and switching elements formed in layers on the substrate in this order. Each of the photoelectric transducers includes a hydrogenated amorphous silicon layer. Each of the switching elements includes an amorphous oxide semiconductor layer. The image sensor further includes a blocking layer arranged between the hydrogenated amorphous silicon layers of the photoelectric transducers and the amorphous oxide semiconductor layers of the switching elements, where the blocking layer suppresses penetration of hydrogen separated from the hydrogenated amorphous silicon layers.

Abstract: Deep trench isolation (DTI) structures and methods of forming the same are provided. A method includes forming a plurality of photosensitive regions in a substrate. A recess is formed in the substrate, the substrate comprising a first semiconductor material, the recess being interposed between adjacent photosensitive regions. The recess is enlarged by removing a damaged layer of the substrate along sidewalls of the recess, thereby forming an enlarged recess. An epitaxial region is formed on sidewalls and a bottom of the enlarged recess, at least a portion of the epitaxial region comprising a second semiconductor material, the second semiconductor material being different from the first semiconductor material. A dielectric region is formed on the epitaxial region, the epitaxial region extending along a sidewall of the dielectric region.

Abstract: A solid-state image pickup device 1 according to the present invention includes a semiconductor substrate 2 on which a pixel 20 composed of a photodiode 3 and a transistor is formed. The transistor comprising the pixel 20 is formed on the surface of the semiconductor substrate, a pn junction portion formed between high concentration regions of the photodiode 3 is provided within the semiconductor substrate 2 and a part of the pn junction portion of the photodiode 3 is extended to a lower portion of the transistor formed on the surface of the semiconductor substrate 2. According to the present invention, there is provided a solid-state image pickup device in which a pixel size can be microminiaturized without lowering a saturated electric charge amount (Qs) and sensitivity.

Abstract: Semiconductor devices and methods of fabricating such devices are provided. The devices include source and drain regions on one conductivity type separated by a channel length and a gate structure. The devices also include a channel region of the one conductivity type formed in the device region between the source and drain regions and a screening region of another conductivity type formed below the channel region and between the source and drain regions. In operation, the channel region forms, in response to a bias voltage at the gate structure, a surface depletion region below the gate structure, a buried depletion region at an interface of the channel region and the screening region, and a buried channel region between the surface depletion region and the buried depletion region, where the buried depletion region is substantially located in channel region.

Abstract: A solid-state image sensor which holds a potential for a long time and includes a thin film transistor with stable electrical characteristics is provided. When the off-state current of a thin film transistor including an oxide semiconductor layer is set to 1×10?13 A or less and the thin film transistor is used as a reset transistor and a transfer transistor of the solid-state image sensor, the potential of the signal charge storage portion is kept constant, so that a dynamic range can be improved. When a silicon semiconductor which can be used for a complementary metal oxide semiconductor is used for a peripheral circuit, a high-speed semiconductor device with low power consumption can be manufactured.

Abstract: The present invention relates to a display device including a static electricity discharge circuit. The display device according to an exemplary embodiment of the present invention includes: a thin film transistor array panel including a display area including a plurality of pixels and a peripheral area around the display area; a signal wire positioned at the peripheral area; and a static electricity discharge circuit unit positioned at the peripheral area and connected to the signal wire, wherein the static electricity discharge circuit unit includes a first portion and a second portion positioned at a same layer as a portion of the signal wire and facing each other with a separation space therebetween, and a connecting member positioned at a different layer from the first portion and the second portion and electrically connecting the first portion and the second portion.

Abstract: A semiconductor device includes a thin film transistor (100), the thin film transistor (100) including: a substrate (1); a gate electrode (3) provided on the substrate (1); a gate dielectric layer (5) formed on the gate electrode (3); an island-shaped oxide semiconductor layer (7) formed on the gate dielectric layer (5); a protective layer (9) provided so as to cover an upper face (7u) and an entire side face (7e) of the oxide semiconductor layer (7), the protective layer (9) having a single opening (9p) through which the upper face (7u) of the oxide semiconductor layer (7) is only partially exposed; and a source electrode (11) and a drain electrode (13) which are in contact with the oxide semiconductor layer (7) within the single opening (9p).

Abstract: In an embodiment, a fluid ejection device includes a thin-film layer formed over a substrate. A primer layer is formed over the thin-film layer, and a chamber layer is formed over the primer layer that defines a fluidic channel leading to a firing chamber. The fluid ejection device includes a slot that extends through the substrate and into the chamber layer through an ink feed hole in the thin-film layer. The fluid ejection device also includes a particle tolerant extension of the primer layer that protrudes into the slot. In some implementations, the particle tolerant primer layer extension extends across a full width of the slot.

Abstract: Disclosed are a sensing pixel and an image sensor including the same. The sensing pixel includes a determination region, which includes one or more floating body transistors, and an integration region that is adjacent to a floating body region of one of the one or more floating body transistors, absorbs light to generate an electron-hole pair including an electron and a positive hole, and transfers the electron or the positive hole to the floating body region of the one floating body transistor.

Abstract: To provide a solid-state imaging device with short image-capturing duration. A first photodiode in a pixel in an n-th row and an m-th column is connected to a second photodiode in a pixel in an (n+1)-th row and the m-th column through a transistor. The first photodiode and the second photodiode receive light concurrently, the potential in accordance with the amount of received light is held in a pixel in the n-th row and the m-th column, and the potential in accordance with the amount of received light is held in a pixel in the (n+1)-th row and the m-th column without performing a reset operation. Then, each potential is read out. Under a large amount of light, either the first photodiode or the second photodiode is used.

Abstract: Provided is an imaging apparatus and an imaging system that can suppress high-brightness darkening phenomenon without preventing achievement of high-speed operation. The imaging apparatus includes: pixels each outputting a signal based on photoelectric conversion to each of signal lines; clip units each having a first transistor for clipping the voltage of each of the signal lines; a holding capacitor having a first electrode connected to a control electrode of the first transistor, and having a second electrode; a shift unit configured to supply, to the second electrodes, a plurality of voltages having values different from each other; and a voltage supplying unit provided separately from the shift unit and supplying a first voltage to the second electrodes.

Abstract: An object of the present invention is to provide a nonaqueous electrolytic solution capable of improving electrochemical characteristics in a broad temperature range, an energy storage device using it. A nonaqueous electrolytic solution of an electrolyte salt dissolved in a nonaqueous solvent, which comprises at least one cyclic sulfonic acid ester compound represented by the following general formula (I), and an energy storage device.

Abstract: In order to provide a photodetection semiconductor device including a light receiving element configured to reduce afterimages, a photodiode is formed by a PN junction into a circular shape so that a uniform distance from an end portion of a light receiving element to an electrode serving as a carrier outlet is realized, to thereby enable carriers to be uniformly taken out from all directions.

Abstract: A solid-state imaging device including a unit pixel including a photoelectric conversion section, an impurity-diffusion region capable of temporarily accumulating or holding electric charges generated by the photoelectric conversion section, and a reset transistor resetting the impurity-diffusion region by a voltage of a voltage-supply line, and having an impurity concentration such that at least the reset transistor side of the impurity-diffusion region becomes a depletion state; and a drive circuit changing the voltage of the voltage-supply line from a first voltage lower than a depletion potential of the reset transistor side of the impurity-diffusion region to a second voltage higher than the depletion potential while the reset transistor is on.

Abstract: An image sensor may include image sensor pixels formed on a substrate. Each pixel may have a photodiode, a floating diffusion node, and charge transfer gate. The pixel may include an n-type doped well region and a p-channel MOS source follower transistor formed within the n-well region. An n-channel MOS reset transistor may be coupled between the floating diffusion region and a bias voltage column line and may have a drain terminal that overlaps with the n-well region. If desired, the pixel may include a p-channel JFET source follower transistor formed within the floating diffusion region on the substrate and an n-channel MOSFET reset transistor coupled to the floating diffusion. The polarities of the doping in the substrate on which the pixels are formed may be reversed. The pixel may be formed without row select transistors to increase photodiode area and charge storage capacity.

Abstract: A TFT array substrate, a display panel and a display device are disclosed. The TFT array substrate includes a substrate, a display area and a peripheral area surrounding the display area. The display area and the peripheral area are arranged above the substrate. The peripheral area comprises a signal line and a shielding layer arranged above the signal line, and the shielding layer covers the signal line to shield EMI caused by a signal on the signal line. The TFT array substrate, the display panel and the display device can protect the display panel against EMI caused by the signal on the signal lines in the peripheral area, thereby improving stability and reliability of the TFT array substrate, the display panel and the display device, and enhancing sensitivity of a cellphone having the display panel.

Abstract: An image sensor pixel includes a photosensitive element, a floating diffusion region, a transfer gate, a dielectric charge trapping region, and a first metal contact. The photosensitive element is disposed in a semiconductor layer to receive electromagnetic radiation along a vertical axis. The floating diffusion region is disposed in the semiconductor layer, while the transfer gate is disposed on the semiconductor layer to control a flow of charge produced in the photosensitive element to the floating diffusion region. The dielectric charge trapping device is disposed on the semiconductor layer to receive electromagnetic radiation along the vertical axis and to trap charges in response thereto. The dielectric charge trapping device is further configured to induce charge in the photosensitive element in response to the trapped charges. The first metal contact is coupled to the dielectric charge trapping device to provide a first bias voltage to the dielectric charge trapping device.