Sensor Element And Charge Transfer Device Are Of Different Materials Or On Different Substrates (e.g., "hybrid") Patents (Class 257/226)
  • Patent number: 10186547
    Abstract: Provided are a solid-state imaging element which can be simply manufactured and can control movement of electric charges in an accumulation region with a high degree of accuracy, and a method of manufacturing the same. A solid-state imaging element (1a) includes a substrate (11) having a first conductivity type; an accumulation region (12) having a second conductivity type and provided in the substrate (11); a read-out region (13) for receiving the transferred electric charges accumulated in the accumulation region (12); and a transfer section (14) for transferring the electric charges from the accumulation region (12) to the read-out region (13). An impurity concentration modulation region 121 having a locally high concentration of an impurity having the second conductivity type, or having a locally low concentration of an impurity having the first conductivity type is formed in a part of the accumulation region (12).
    Type: Grant
    Filed: February 21, 2013
    Date of Patent: January 22, 2019
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Takeo Ushinaga
  • Patent number: 9918030
    Abstract: The present technology relates to an imaging device that can reduce the size thereof, and to an electronic apparatus. An upper substrate and a lower substrate are stacked. A pixel and a comparing unit that compares the voltage of a signal from the pixel with the ramp voltage are provided on the upper substrate, the ramp voltage varying with time. A storage unit that stores a code value obtained at a time when a comparison result from the comparing unit is inverted is provided on the lower substrate. The comparing unit is formed with a transistor that receives the voltage of the signal from the pixel at the gate, receives the ramp voltage at the source, and outputs a drain voltage. Accordingly, the imaging device can be made smaller in size. The present technology can be applied to image sensors.
    Type: Grant
    Filed: July 22, 2014
    Date of Patent: March 13, 2018
    Assignee: Sony Corporation
    Inventor: Keiji Mabuchi
  • Patent number: 9893099
    Abstract: The present disclosure relates to a photo sensor module. The thickness and size of an IC chip may be reduced by manufacturing a photo sensor based on a semiconductor substrate and improving the structure to place a UV sensor on the upper section of an active device or a passive device. The photo sensor module includes a semiconductor substrate, a field oxide layer, formed on the semiconductor substrate, and a photo sensor comprising a photo diode formed on the field oxide layer.
    Type: Grant
    Filed: September 13, 2016
    Date of Patent: February 13, 2018
    Assignee: Magnachip Semiconductor, Ltd.
    Inventors: Francois Hebert, Seong Min Choe
  • Patent number: 9721917
    Abstract: A semiconductor device is provided with a semiconductor chip. The semiconductor chip has a semiconductor substrate, an interconnect layer, an inductor and conductive pads (first pads). The interconnect layer is provided on the semiconductor substrate. The interconnect layer includes the inductor. The pads are provided on the interconnect layer. The pads are provided in a region within a circuit forming region of the semiconductor chip, which does not overlap the inductor.
    Type: Grant
    Filed: September 11, 2014
    Date of Patent: August 1, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Yasutaka Nakashiba
  • Patent number: 9620540
    Abstract: An image sensor includes a photoelectric conversion element including a first impurity region and a second impurity region, wherein the first impurity region contacts a first surface of a substrate, wherein the second impurity region has conductivity complementary to the first impurity region and is formed in the substrate and below the first impurity region; a pillar formed over the photoelectric conversion element; a transfer gate formed over the photoelectric conversion element to surround the pillar; and a channel layer formed between the transfer gate and the pillar and contacting the photoelectric conversion element, wherein the channel layer contacts the first impurity region and has the same conductivity as the second impurity region.
    Type: Grant
    Filed: February 9, 2016
    Date of Patent: April 11, 2017
    Assignee: SK Hynix Inc.
    Inventors: Yun-Hui Yang, Pyong-Su Kwag, Young-Jun Kwon, Min-Ki Na, Sung-Kun Park, Donghyun Woo, Cha-Young Lee, Ho-Ryeong Lee
  • Patent number: 9310576
    Abstract: Various embodiments include an integrated circuit having: at least one waveguide disposed in a low refractive index layer; a splitter connected to the at least one waveguide, the splitter consisting of at least two signal paths; an optical signal detector connected to an end of each of the at least two signal paths; and an electrical disconnect member connected to each optical signal detector.
    Type: Grant
    Filed: November 26, 2014
    Date of Patent: April 12, 2016
    Assignee: International Business Machines Corporation
    Inventors: John J. Ellis-Monaghan, Brendan S. Harris, Vibhor Jain, Thomas Kessler, Yves T. Ngu, Sebastian T. Ventrone
  • Patent number: 9196781
    Abstract: A photodetector is described along with corresponding materials, systems, and methods. The photodetector comprises an integrated circuit and at least two optically sensitive layers. A first optically sensitive layer is over at least a portion of the integrated circuit, and a second optically sensitive layer is over the first optically sensitive layer. Each optically sensitive layer is interposed between two electrodes. The two electrodes include a respective first electrode and a respective second electrode. The integrated circuit selectively applies a bias to the electrodes and reads signals from the optically sensitive layers. The signal is related to the number of photons received by the respective optically sensitive layer.
    Type: Grant
    Filed: October 7, 2013
    Date of Patent: November 24, 2015
    Assignee: InVisage Technologies, Inc.
    Inventors: Hui Tian, Edward Sargent
  • Patent number: 9053964
    Abstract: Example embodiments relate to semiconductor devices and/or methods of manufacturing the same. According to example embodiments, a semiconductor device may include a first heterojunction field effect transistor (HFET) on a first surface of a substrate, and a second HFET. A second surface of the substrate may be on the second HFET. The second HFET may have different properties (characteristics) than the first HFET. One of the first and second HFETs may be of an n type, while the other thereof may be of a p type. The first and second HFETs may be high-electron-mobility transistors (HEMTs). One of the first and second HFETs may have normally-on properties, while the other thereof may have normally-off properties.
    Type: Grant
    Filed: June 20, 2013
    Date of Patent: June 9, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Woo-chul Jeon, Woong-je Sung, Jai-kwang Shin, Jae-joon Oh
  • Publication number: 20150115330
    Abstract: A technology capable of simplifying a process and securing a misalignment margin when bonding two wafers to manufacture an image sensor using backside illumination photodiodes. When manufacturing an image sensor through a 3D CIS (CMOS image sensor) manufacturing process, two wafers, that is, a first wafer and a second wafer are electrically connected using the vias of one wafer and the bonding pads of the other wafer. Also, when manufacturing an image sensor through a 3D CIS manufacturing process, two wafers are electrically connected using the vias of both the two wafers.
    Type: Application
    Filed: October 31, 2014
    Publication date: April 30, 2015
    Inventors: Jae Young Park, Young Ha Lee, Jun Ho Won, Do Young Lee
  • Patent number: 9012289
    Abstract: A semiconductor device and its manufacturing method are disclosed. The semiconductor device comprises a gate, and source and drain regions on opposite sides of the gate, wherein a portion of a gate dielectric layer located above the channel region is thinner than a portion of the gate dielectric layer located at the overlap region of the drain and the gate. The thicker first thickness portion may ensure that the device can endure a higher voltage at the drain to gate region, while the thinner second thickness portion may ensure excellent performance of the device.
    Type: Grant
    Filed: September 3, 2013
    Date of Patent: April 21, 2015
    Assignee: Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Jinhua Liu
  • Patent number: 8921901
    Abstract: A stacked wafer structure includes a CIS wafer, an ISP wafer, a lamination layer, a through silicon via and a pixel device. The CIS wafer bonds to the ISP wafer through the lamination layer. The pixel device is disposed on the CIS wafer. The through silicon via penetrates either the CIS wafer or the ISP wafer to connect devices in CIS wafer to the devices in ISP wafer electrically.
    Type: Grant
    Filed: June 10, 2013
    Date of Patent: December 30, 2014
    Assignee: United Microelectronics Corp.
    Inventor: Ching-Hung Kao
  • Publication number: 20140361347
    Abstract: A stacked wafer structure includes a CIS wafer, an ISP wafer, a lamination layer, a through silicon via and a pixel device. The CIS wafer bonds to the ISP wafer through the lamination layer. The pixel device is disposed on the CIS wafer. The through silicon via penetrates either the CIS wafer or the ISP wafer to connect devices in CIS wafer to the devices in ISP wafer electrically.
    Type: Application
    Filed: June 10, 2013
    Publication date: December 11, 2014
    Inventor: Ching-Hung Kao
  • Patent number: 8907376
    Abstract: A stretchable electronic circuit that includes a stretchable base substrate having a plurality of stretchable conductors formed onto a surface thereof, with both the stretchable base substrate and conductors being bendable together about two orthogonal axes. The stretchable circuit also includes a stretchable sensor layer attached to the base substrate with a cavity formed therein which has a contact point exposing one of the plurality of stretchable conductors. The stretchable electronic circuit further includes a surface mount device (SMD) package with a conductor contact protrusion installed into the cavity, and wherein a substantially constant electrical connection is established between the conductor contact protrusion and the stretchable conductor at the contact point by tensile forces interacting between the stretchable base substrate and the stretchable sensor layer.
    Type: Grant
    Filed: November 8, 2012
    Date of Patent: December 9, 2014
    Assignee: University of Utah Research Foundation
    Inventors: Stephen Mascaro, Debra Mascaro, Jumana Abu-Khalaf, Jungwoo Park
  • Patent number: 8883524
    Abstract: Methods and apparatus for a sensor are disclosed. An oxide layer is formed on a substrate, followed by a spacer layer and a buffer layer. A photoresist layer is formed on the buffer layer over a pixel region, with an opening exposing a first part of the buffer layer. A first etching is performed to remove the first part of the buffer layer to expose a first part of the spacer layer. A second etching is performed to remove the first part of the spacer layer, the remaining buffer layer, and partially remove a second part of the spacer layer so that the result spacer layer will have an end with a shape substantially similar to a triangle, a height of the end is in a substantially same range as a length of the end.
    Type: Grant
    Filed: June 3, 2013
    Date of Patent: November 11, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Tsung Kuo, Jiech-Fun Lu, Yeur-Luen Tu, Chia-Shiung Tsai
  • Patent number: 8869591
    Abstract: A method for sensing analyte. The method includes the steps of sensing one or more parameters in reaction to the presence of one or more analytes and outputting a current therefrom in accordance with level of the sensed parameter by each of a plurality of sensors, each of the plurality of sensors being provided in one or more sensor array columns, selectively heating one or more of the sensor array columns by a heating element, and receiving an output current from one of the plurality of sensors from each of the plurality of sensor arrays by a Voltage Controlled Oscillator (VCO) arranged in a VCO array. The method further includes the steps of generating an output oscillation frequency by each VCO in accordance with the level of the received output current, and counting a number of oscillations over a predetermined time received from each of the plurality of VCOs in the VCO array by a plurality of counters arranged in a counter array.
    Type: Grant
    Filed: April 15, 2013
    Date of Patent: October 28, 2014
    Assignee: Sensorbit Systems, Inc.
    Inventors: Klaus Dimmler, Thomas Moss, III
  • Patent number: 8866238
    Abstract: Hybrid integrated components including an MEMS element and an ASIC element are described, whose capacitor system allows both signal detection with comparatively high sensitivity and sensitive activation of the micromechanical structure of the MEMS element. The hybrid integrated component includes an MEMS element having a micromechanical structure which extends over the entire thickness of the MEMS substrate. At least one structural element of this micromechanical structure is deflectable and is operationally linked to at least one capacitor system, which includes at least one movable electrode and at least one stationary electrode. Furthermore, the component includes an ASIC element having at least one electrode of the capacitor system. The MEMS element is mounted on the ASIC element, so that there is a gap between the micromechanical structure and the surface of the ASIC element.
    Type: Grant
    Filed: April 24, 2013
    Date of Patent: October 21, 2014
    Assignee: Robert Bosch GmbH
    Inventor: Johannes Classen
  • Patent number: 8842206
    Abstract: An imaging device includes: a pixel array section having an array of pixels, each of which has a photoelectric converting device and outputs an electric signal according to an input photon; a sense circuit section having a plurality of sensor circuits each of which makes binary decision on whether there is a photon input to a pixel in a predetermined period upon reception of the electric signal therefrom; and a decision result IC section which integrates decision results from the sense circuits, pixel by pixel or for each group of pixels, multiple times to generate imaged data with a gradation, the decision result IC section including a count circuit which performs a count process to integrate the decision results from the sense circuits, and a memory for storing a counting result for each pixel from the count circuit, the sense circuits sharing the count circuit for integrating the decision results.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: September 23, 2014
    Assignee: Sony Corporation
    Inventor: Toshiyuki Nishihara
  • Patent number: 8841158
    Abstract: A solid-state image pick-up device is provided which includes a semiconductor substrate main body which has an element forming layer and a gettering layer provided on an upper layer thereof; photoelectric conversion elements, each of which includes a first conductive type region, provided in the element forming layer; and a dielectric film which is provided on an upper layer of the gettering layer and which induces a second conductive type region in a surface of the gettering layer.
    Type: Grant
    Filed: October 2, 2013
    Date of Patent: September 23, 2014
    Assignee: Sony Corporation
    Inventor: Shin Iwabuchi
  • Patent number: 8816462
    Abstract: An image sensor pixel includes a photodiode region having a first polarity doping type disposed in a semiconductor layer. A pinning surface layer having a second polarity doping type is disposed over the photodiode region in the semiconductor layer. The second polarity is opposite from the first polarity. A first polarity charge layer is disposed proximate to the pinning surface layer over the photodiode region. An contact etch stop layer is disposed over the photodiode region proximate to the first polarity charge layer. The first polarity charge layer is disposed between the pinning surface layer and the contact etch stop layer such that first polarity charge layer cancels out charge having a second polarity that is induced in the contact etch stop layer. A passivation layer is also disposed over the photodiode region between the pinning surface layer and the contact etch stop layer.
    Type: Grant
    Filed: October 25, 2012
    Date of Patent: August 26, 2014
    Assignee: OmniVision Technologies, Inc.
    Inventors: Howard E. Rhodes, Dajiang Yang, Gang Chen, Duli Mao, Vincent Venezia
  • Patent number: 8785982
    Abstract: A unit pixel of a depth sensor including a light-intensity output circuit configured to output a pixel signal according to a control signal, the pixel signal corresponding to a first electric charge and a second electric charge, a first light-intensity extraction circuit configured to generate the first electric charge and transmit the first electric charge to the light-intensity output circuit, the first electric charge varying according to an amount of light reflected from a target object and a second light-intensity extraction circuit configured to generate the second electric charge and transmit the second electric charge to the light-intensity output circuit, the second electric charge varying according to the amount of reflected light. The light-intensity output circuit includes a first floating diffusion node. Accordingly, it is possible to minimize waste of a space, thereby manufacturing a small-sized pixel.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: July 22, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Woo Joo Kim, Hyoung Soo Ko, Yoon Dong Park, Jung Bin Yun
  • Patent number: 8766326
    Abstract: A field-effect transistor or a single electron transistor is used as sensors for detecting a detection target such as a biological compound. A substrate has a first side and a second side, the second side being opposed to the first side. A source electrode is disposed on the first side of the substrate and a drain electrode disposed on the first side of the substrate, and a channel forms a current path between the source electrode and the drain electrode. An interaction-sensing gate is disposed on the second side of the substrate, the interaction-sensing gate having a specific substance that is capable of selectively interacting with the detection target. A gate for applying a gate voltage adjusts a characteristic of the transistor as the detection target changes the characteristic of the transistor when interacting with the specific substance.
    Type: Grant
    Filed: July 24, 2012
    Date of Patent: July 1, 2014
    Assignee: Japan Science and Technology Agency
    Inventors: Kazuhiko Matsumoto, Atsuhiko Kojima, Satoru Nagao, Masanori Katou, Yutaka Yamada, Kazuhiro Nagaike, Yasuo Ifuku, Hiroshi Mitani
  • Patent number: 8746036
    Abstract: A method for sensing analyte. The method includes the steps of sensing one or more parameters in reaction to the presence of one or more analytes and outputting a current therefrom in accordance with level of the sensed parameter by each of a plurality of sensors, each of the plurality of sensors being provided in one or more sensor array columns, selectively heating one or more of the sensor array columns by a heating element, and receiving an output current from one of the plurality of sensors from each of the plurality of sensor arrays by a Voltage Controlled Oscillator (VCO) arranged in a VCO array. The method further includes the steps of generating an output oscillation frequency by each VCO in accordance with the level of the received output current, and counting a number of oscillations over a predetermined time received from each of the plurality of VCOs in the VCO array by a plurality of counters arranged in a counter array.
    Type: Grant
    Filed: April 15, 2013
    Date of Patent: June 10, 2014
    Assignee: Sensorbit Systems, Inc.
    Inventors: Klaus Dimmler, Thomas Moss, III
  • Patent number: 8643064
    Abstract: A photodetector is described along with corresponding materials, systems, and methods. The photodetector comprises an integrated circuit and at least two optically sensitive layers. A first optically sensitive layer is over at least a portion of the integrated circuit, and a second optically sensitive layer is over the first optically sensitive layer. Each optically sensitive layer is interposed between two electrodes. The two electrodes include a respective first electrode and a respective second electrode. The integrated circuit selectively applies a bias to the electrodes and reads signals from the optically sensitive layers. The signal is related to the number of photons received by the respective optically sensitive layer.
    Type: Grant
    Filed: August 26, 2011
    Date of Patent: February 4, 2014
    Assignee: InVisage Technologies, Inc.
    Inventors: Hui Tian, Edward Sargent
  • Patent number: 8575661
    Abstract: A solid-state image pick-up device is provided which includes a semiconductor substrate main body which has an element forming layer and a gettering layer provided on an upper layer thereof; photoelectric conversion elements, each of which includes a first conductive type region, provided in the element forming layer; and a dielectric film which is provided on an upper layer of the gettering layer and which induces a second conductive type region in a surface of the gettering layer.
    Type: Grant
    Filed: January 28, 2010
    Date of Patent: November 5, 2013
    Assignee: Sony Corporation
    Inventor: Shin Iwabuchi
  • Patent number: 8558286
    Abstract: A photodetector is described along with corresponding materials, systems, and methods. The photodetector comprises an integrated circuit and at least two optically sensitive layers. A first optically sensitive layer is over at least a portion of the integrated circuit, and a second optically sensitive layer is over the first optically sensitive layer. Each optically sensitive layer is interposed between two electrodes. The two electrodes include a respective first electrode and a respective second electrode. The integrated circuit selectively applies a bias to the electrodes and reads signals from the optically sensitive layers. The signal is related to the number of photons received by the respective optically sensitive layer.
    Type: Grant
    Filed: August 25, 2011
    Date of Patent: October 15, 2013
    Assignee: InVisage Technologies, Inc.
    Inventors: Hui Tian, Edward Sargent
  • Patent number: 8546853
    Abstract: A photodetector is described along with corresponding materials, systems, and methods. The photodetector comprises an integrated circuit and at least two optically sensitive layers. A first optically sensitive layer is over at least a portion of the integrated circuit, and a second optically sensitive layer is over the first optically sensitive layer. Each optically sensitive layer is interposed between two electrodes. The two electrodes include a respective first electrode and a respective second electrode. The integrated circuit selectively applies a bias to the electrodes and reads signals from the optically sensitive layers. The signal is related to the number of photons received by the respective optically sensitive layer.
    Type: Grant
    Filed: August 12, 2011
    Date of Patent: October 1, 2013
    Assignee: InVisage Technologies, Inc.
    Inventors: Hui Tian, Edward Sargent
  • Patent number: 8530992
    Abstract: A photodetector is described along with corresponding materials, systems, and methods. The photodetector comprises an integrated circuit and at least two optically sensitive layers. A first optically sensitive layer is over at least a portion of the integrated circuit, and a second optically sensitive layer is over the first optically sensitive layer. Each optically sensitive layer is interposed between two electrodes. The two electrodes include a respective first electrode and a respective second electrode. The integrated circuit selectively applies a bias to the electrodes and reads signals from the optically sensitive layers. The signal is related to the number of photons received by the respective optically sensitive layer.
    Type: Grant
    Filed: August 25, 2011
    Date of Patent: September 10, 2013
    Assignee: InVisage Technologies, Inc.
    Inventors: Hui Tian, Edward Sargent
  • Patent number: 8530991
    Abstract: A photodetector is described along with corresponding materials, systems, and methods. The photodetector comprises an integrated circuit and at least two optically sensitive layers. A first optically sensitive layer is over at least a portion of the integrated circuit, and a second optically sensitive layer is over the first optically sensitive layer. Each optically sensitive layer is interposed between two electrodes. The two electrodes include a respective first electrode and a respective second electrode. The integrated circuit selectively applies a bias to the electrodes and reads signals from the optically sensitive layers. The signal is related to the number of photons received by the respective optically sensitive layer.
    Type: Grant
    Filed: August 24, 2011
    Date of Patent: September 10, 2013
    Assignee: InVisage Technologies, Inc.
    Inventors: Hui Tian, Edward Sargent
  • Patent number: 8530940
    Abstract: A photodetector is described along with corresponding materials, systems, and methods. The photodetector comprises an integrated circuit and at least two optically sensitive layers. A first optically sensitive layer is over at least a portion of the integrated circuit, and a second optically sensitive layer is over the first optically sensitive layer. Each optically sensitive layer is interposed between two electrodes. The two electrodes include a respective first electrode and a respective second electrode. The integrated circuit selectively applies a bias to the electrodes and reads signals from the optically sensitive layers. The signal is related to the number of photons received by the respective optically sensitive layer.
    Type: Grant
    Filed: August 24, 2011
    Date of Patent: September 10, 2013
    Assignee: InVisage Technologies, Inc.
    Inventors: Hui Tian, Edward Sargent
  • Patent number: 8530993
    Abstract: A photodetector is described along with corresponding materials, systems, and methods. The photodetector comprises an integrated circuit and at least two optically sensitive layers. A first optically sensitive layer is over at least a portion of the integrated circuit, and a second optically sensitive layer is over the first optically sensitive layer. Each optically sensitive layer is interposed between two electrodes. The two electrodes include a respective first electrode and a respective second electrode. The integrated circuit selectively applies a bias to the electrodes and reads signals from the optically sensitive layers. The signal is related to the number of photons received by the respective optically sensitive layer.
    Type: Grant
    Filed: August 26, 2011
    Date of Patent: September 10, 2013
    Assignee: InVisage Technologies, Inc.
    Inventors: Hui Tian, Edward Sargent
  • Patent number: 8525287
    Abstract: A photodetector is described along with corresponding materials, systems, and methods. The photodetector comprises an integrated circuit and at least two optically sensitive layers. A first optically sensitive layer is over at least a portion of the integrated circuit, and a second optically sensitive layer is over the first optically sensitive layer. Each optically sensitive layer is interposed between two electrodes. The two electrodes include a respective first electrode and a respective second electrode. The integrated circuit selectively applies a bias to the electrodes and reads signals from the optically sensitive layers. The signal is related to the number of photons received by the respective optically sensitive layer.
    Type: Grant
    Filed: August 24, 2011
    Date of Patent: September 3, 2013
    Assignee: InVisage Technologies, Inc.
    Inventors: Hui Tian, Edward Sargent
  • Patent number: 8502385
    Abstract: A power semiconductor device has the power semiconductor elements having back surfaces bonded to wiring patterns and surface electrodes, cylindrical communication parts having bottom surfaces bonded on the surface electrodes of the power semiconductor elements and/or on the wiring patterns, a transfer mold resin having concave parts which expose the upper surfaces of the communication parts and cover the insulating layer, the wiring patterns, and the power semiconductor elements. External terminals have one ends inserted in the upper surfaces of the communication parts and the other ends guided upward, and at least one external terminal has, between both end parts, a bent area which is bent in an L shape and is embedded in the concave part of the transfer mold resin.
    Type: Grant
    Filed: June 1, 2011
    Date of Patent: August 6, 2013
    Assignee: Mitsubishi Electric Corporation
    Inventors: Seiji Oka, Tetsuya Ueda
  • Patent number: 8488034
    Abstract: An imaging device includes: a pixel array section having an array of pixels each of which has a photoelectric converting device and outputs an electric signal according to an input photon; a sense circuit section having a plurality of sensor circuits each of which makes binary decision on whether there is a photon input to a pixel in a predetermined period upon reception of the electric signal therefrom; and a decision result IC section which integrates decision results from the sense circuits, pixel by pixel or for each group of pixels, multiple times to generate imaged data with a gradation, the decision result IC section including a count circuit which performs a count process to integrate the decision results from the sense circuits, and a memory for storing a counting result for each pixel from the count circuit, the plurality of sense circuits sharing the count circuit for integrating the decision results.
    Type: Grant
    Filed: July 29, 2010
    Date of Patent: July 16, 2013
    Assignee: Sony Corporation
    Inventor: Toshiyuki Nishihara
  • Patent number: 8471261
    Abstract: A solid-state image pickup device 1 is back surface incident type and includes a semiconductor substrate 10, a semiconductor layer 20 and a light receiving unit 30. The solid-state image pickup device 1 photoelectrically converts light incident on the back surface S2 of the semiconductor substrate 10 into signal electrical charges to image an object. The semiconductor substrate 10 has a resistivity ?1. A semiconductor layer 20 is provided on the surface S1 of the semiconductor substrate 10. The semiconductor layer 20 has a resistivity ?2. Where, ?2>?1. A light receiving unit 30 is formed in the semiconductor layer 20. The light receiving unit 30 receives signal charges produced by the photoelectric conversion.
    Type: Grant
    Filed: July 9, 2007
    Date of Patent: June 25, 2013
    Assignee: Renesas Electronics Corporation
    Inventor: Yasutaka Nakashiba
  • Patent number: 8466521
    Abstract: A hydrogen ion-sensitive field effect transistor and a manufacturing method thereof are provided. The hydrogen ion-sensitive field effect transistor includes a semiconductor substrate, an insulating layer, a transistor gate, and a sensing film. A gate area is defined on the semiconductor substrate having a source area and a drain area. The insulating layer is formed within the gate area on the semiconductor substrate. The transistor gate is deposited within the gate area and includes a first gate layer. Further, the first gate layer is an aluminum layer, and a sensing window is defined thereon. The sensing film is an alumina film formed within the sensing window by oxidizing the first gate layer. Thus, the sensing film is formed without any film deposition process, and consequently the manufacturing method is simplified.
    Type: Grant
    Filed: March 16, 2010
    Date of Patent: June 18, 2013
    Assignee: National Chip Implementation Center National Applied Research Laboratories
    Inventors: Chin-Long Wey, Chin-Fong Chiu, Ying-Zong Juang, Hann-Huei Tsai, Chen-Fu Lin
  • Patent number: 8389379
    Abstract: A method of making a complex microelectronic structure by assembling two substrates through two respective linking surfaces, the structure being designed to be dissociated at a separation zone. Prior to assembly, in producing a state difference in the tangential stresses between the two surfaces to be assembled, the state difference is selected so as to produce in the assembled structure a predetermined stress state at the time of dissociation.
    Type: Grant
    Filed: December 1, 2009
    Date of Patent: March 5, 2013
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Franck Fournel, Hubert Moriceau, Christelle Lagahe
  • Patent number: 8384134
    Abstract: A MEMS device is disclosed. The MEMS device comprises a MEMS substrate and a CMOS substrate having a front surface, a back surface and one or more metallization layers. The front surface being bonded to the MEMS substrate. The MEMS device includes one or more conductive features on the back surface of the CMOS substrate and electrical connections between the one or more metallization layers and the one or more conductive features.
    Type: Grant
    Filed: April 25, 2012
    Date of Patent: February 26, 2013
    Assignee: Invensense, Inc.
    Inventors: Michael J. Daneman, Steven S. Nasiri, Martin Lim
  • Patent number: 8294476
    Abstract: A method for measuring values from a sensor cell having the basic structure of an MOS silicone transistor having and including a polymer material therein. The method includes the steps of expelling an analyte from the polymer material, determining a silicon current signature before analyte accumulation in a sensitive response region, introducing analyte into the polymer material, determining the silicon current signature immediately after analyte introduction, determining the organic current signature immediately after analyte introduction, allowing analyte accumulation in the polymer material, determining the silicon current signature after analyte accumulation, determining the organic current signature after analyte accumulation, and determining the silicon current signature after analyte accumulation in sensitive response region.
    Type: Grant
    Filed: June 15, 2010
    Date of Patent: October 23, 2012
    Assignee: Sensorbit Systems, Inc.
    Inventors: Klaus Dimmler, Thomas Moss, III
  • Patent number: 8269260
    Abstract: A photodetector is described along with corresponding materials, systems, and methods. The photodetector comprises an integrated circuit and at least two optically sensitive layers. A first optically sensitive layer is over at least a portion of the integrated circuit, and a second optically sensitive layer is over the first optically sensitive layer. Each optically sensitive layer is interposed between two electrodes. The two electrodes include a respective first electrode and a respective second electrode. The integrated circuit selectively applies a bias to the electrodes and reads signals from the optically sensitive layers. The signal is related to the number of photons received by the respective optically sensitive layer.
    Type: Grant
    Filed: August 22, 2011
    Date of Patent: September 18, 2012
    Assignee: InVisage Technologies, Inc.
    Inventors: Hui Tian, Edward Sargent
  • Patent number: 8217431
    Abstract: A solid-state image pickup device for preventing crosstalk between adjacent pixels by providing an overflow barrier at the deep potion of a substrate. A partial P type region is provided at the predetermined position of a lower layer region of the vertical transfer register and a channel stop region. This P type region adjusts potential in the lower layer region of the vertical transfer register and the channel stop region. Accordingly, since the potential in the lower layer region of the vertical transfer register and the channel stop region at both sides of the lower layer region is low, electric charges photoelectrically-converted by the sensor region are blocked by this potential barrier and cannot be diffused easily.
    Type: Grant
    Filed: April 9, 2009
    Date of Patent: July 10, 2012
    Assignee: Sony Corporation
    Inventors: Kazushi Wada, Kouichi Harada, Shuji Otsuka, Mitsuru Sato
  • Patent number: 8183650
    Abstract: A micro electromechanical system (MEMS) spring element is disposed on a substrate, and includes a fixing portion and a moveable portion. The fixing portion is fixed on the substrate, and includes an insulating layer, a plurality of metal-fixing layers and a plurality of supporting-fixing layers. The insulating layer is disposed on the substrate. The metal-fixing layers are disposed above the insulating layer. The supporting-fixing layers are connected between the metal-fixing layers. The moveable portion has a first end and a second end. The first end is connected with the fixing portion, and the second end is suspended above the substrate. The moveable portion includes a plurality of metal layers and at least a supporting layer. The supporting layer is connected between the adjacent metal layers, and a hollow region is formed between the supporting layer and the adjacent metal layers.
    Type: Grant
    Filed: April 8, 2010
    Date of Patent: May 22, 2012
    Assignee: PixArt Imaging Inc.
    Inventors: Chuan-Wei Wang, Sheng-Ta Lee, Hsin-Hui Hsu
  • Patent number: 8115242
    Abstract: A multicolor CMOS pixel sensor formed in a p-type semiconductor region includes a first detector formed from an n-type region of semiconductor material located near the surface of the p-type region. A first pinned p-type region is formed at the surface of the p-type region over the first detector, and has a surface portion extending past an edge of the pinned p-type region. A second detector is formed from an n-type region located in the p-type semiconductor region below the first detector. A second-detector n-type deep contact plug is in contact with the second detector and extends to the surface of the p-type semiconductor region. A second pinned p-type region is formed at the surface of the p-type semiconductor region over the top of the second-detector n-type deep contact plug. A surface portion of the second-detector deep contact plug extends past an edge of the second pinned p-type region.
    Type: Grant
    Filed: February 7, 2007
    Date of Patent: February 14, 2012
    Assignee: Foveon, Inc.
    Inventor: Richard B. Merrill
  • Patent number: 8093672
    Abstract: Provided is a manufacturing method of a solid-state imaging device, which is able to realize a solid-state imaging device whose reflection prevention coating is even and that does not have image noise in case of adopting a spincoating method in applying a material of the reflection prevention coating onto microlenses of the solid-state imaging device. In the solid-state imaging device 1 according to the present invention, a barrier wall pattern 7 is formed, as a step alleviating structure, in dicing areas 5X formed between adjacent imaging areas 9. The barrier wall pattern 7 has a rectangular sectional form. With use of the barrier wall pattern 7 in the spincoating method, reflection prevention coating 8 is coated onto the microlenses 6 more evenly than in conventional cases.
    Type: Grant
    Filed: September 20, 2006
    Date of Patent: January 10, 2012
    Assignee: Panasonic Corporation
    Inventors: Tomoki Masuda, Toshihiro Higuchi, Yasuo Takeuchi, Tomoko Komatsu
  • Patent number: 8085998
    Abstract: A finger sensor may include a finger sensing integrated circuit (IC) having a finger sensing area and at least one bond pad adjacent thereto, and a flexible circuit coupled to the IC finger sensor. More particularly, the flexible circuit may include a flexible layer, and at least one conductive trace carried thereby and coupled to the at least one bond pad. The sensor may also include at least one Electrostatic Discharge (ESD) electrode carried by the flexible layer. The ESD electrode may be positioned adjacent a beveled edge, for example, of an IC carrier and thereby exposed through a small gap between an adjacent portion of a frame.
    Type: Grant
    Filed: October 18, 2006
    Date of Patent: December 27, 2011
    Assignee: Authentec, Inc.
    Inventors: Dale R. Setlak, Matthew M. Salatino, Philip J. Spletter, Yang Rao
  • Patent number: 8072006
    Abstract: A high quality imager is constructed using a silicon-on-insulator (SOI) process with sensors fabricated in the SOI substrate and isolated by the buried oxide (BOX) from associated readout circuitry in the SOI layer. Handle windows are opened in the SOI device layer for fabrication of the sensors in the handle layer substrate and then closed prior to processing in the device layer. By keeping the buried oxide layer intact, the described technique allows for independent processing of sensors and readout circuitry so that each is optimized with regard to thermal and dopant properties without concern for degradation of the other. The process is compatible with the fabrication of readout circuitry using transistors having independent double-gates, which offer simultaneous advantages in scalability, low power and low noise. Photodiode sensors are shown with allowance for many other types of sensors. The process easily accommodates hardening against radiation.
    Type: Grant
    Filed: December 21, 2005
    Date of Patent: December 6, 2011
    Assignee: American Semiconductor, Inc.
    Inventors: Douglas R. Hackler, Sr., Richard A. Hayhurst, Stephen A. Parke
  • Patent number: 8053855
    Abstract: A CMOS image sensor for improving light sensitivity and peripheral brightness ratio, and a method for fabricating the same. The CMOS image sensor includes a substrate on which a light sensor and device isolating insulation films are formed, in which the top of the substrate is coated with a plurality of metal layers and oxide films; a plurality of reflective layers formed inside the metal layers, each being spaced apart; a color filter embedded in a groove formed by etching the oxide films inside the reflective layers by a predetermined thickness; a plurality of protrusions formed on both sides of the top of the color filter, each arranged at a predetermined distance from one another; a flat layer formed on the top of the protrusions and the oxide films; and a micro-lens formed on the top of the flat layer. The reflective layer disposed at the top of the photodiode is made of a material having a high reflectance and low absorptivity.
    Type: Grant
    Filed: May 16, 2005
    Date of Patent: November 8, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung-ho Nam, Jin-hwan Kim, Gee-young Sung
  • Patent number: 8004021
    Abstract: Microfabricated devices for operation in a fluid that include a substrate that has a first and second surface and a first electrode material layer located over the first surface of the substrate. The devices have a piezoelectric material layer located over the first electrode material layer and a second electrode material layer located over the piezoelectric material layer. The devices also include a layer of isolation material located over the second electrode material layer that at least one of chemically or electrically isolates a portion of the second electrode material layer from a fluid. Some devices include a layer of conductive material located over the layer of isolation material.
    Type: Grant
    Filed: April 17, 2007
    Date of Patent: August 23, 2011
    Assignee: BioScale, Inc.
    Inventors: Michael F. Miller, Shivalik Bakshi
  • Patent number: 7977131
    Abstract: The present invention provides a method of manufacturing a nano-array electrode with a controlled nano-structure by filling a compound having an electron-accepting structure or an electron donating structure into the fine pores of an anodic-oxide porous alumina film obtained by anodically oxidizing aluminum in electrolyte. The spaces defined between the nano-arrays formed of the compound by removing the alumina film are filled with a compound having an electron-donating structure if the nano-arrays have an electron-accepting structure and a compound having an electron-accepting structure if the nano-arrays have an electron-donating structure. A high-performance, high-efficiency photoelectric converting device comprising a nano-array electrode manufactured by the method is also disclosed.
    Type: Grant
    Filed: December 21, 2009
    Date of Patent: July 12, 2011
    Assignee: Nippon Oil Corporation
    Inventors: Tsuyoshi Asano, Takaya Kubo, Yoshinori Nishikitani
  • Publication number: 20110084316
    Abstract: A pickup device according to the present invention includes a photoelectric conversion portion, a charge holding portion configured to include a first semiconductor region, and a transfer portion configured to include a transfer gate electrode that controls a potential between the charge holding portion and a sense node. A second semiconductor region is disposed on a surface of a semiconductor region between the control electrode and the transfer gate electrode. A third semiconductor region is disposed below the second semiconductor region. An impurity concentration of the third semiconductor region is higher than the impurity concentration of the first semiconductor region.
    Type: Application
    Filed: October 6, 2010
    Publication date: April 14, 2011
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Yuichiro Yamashita, Masahiro Kobayashi, Yusuke Onuki
  • Patent number: 7910964
    Abstract: A part of a semiconductor layer directly under a light-receiving gate electrode functions as a charge generation region, and electrons generated in the charge generation region are injected into a part of a surface buried region directly above the charge generation region. The surface buried region directly under a first transfer gate electrode functions as a first transfer channel, and the surface buried region directly under a second transfer gate electrode functions as a second transfer channel. Signal charges are alternately transferred to an n-type first floating drain region and a second floating drain region through the first and second floating transfer channels.
    Type: Grant
    Filed: August 30, 2006
    Date of Patent: March 22, 2011
    Assignees: National University Corporation Shizuoka University, Sharp Kabushiki Kaisha
    Inventors: Shoji Kawahito, Mitsuru Homma