Abstract: A solid state imaging device in which ? characteristic is obtained and enlargement of dynamic range is provided. The solid state imaging device includes a vertical overflow function and has a feature in which potential of a semiconductor substrate is changed from a high potential to a low potential in a stepwise manner during a period from an exposure start to an exposure end.

Abstract: A multicolor CMOS pixel sensor formed in a p-type semiconductor region includes a first detector formed from an n-type region of semiconductor material located near the surface of the p-type region. A first pinned p-type region is formed at the surface of the p-type region over the first detector, and has a surface portion extending past an edge of the pinned p-type region. A second detector is formed from an n-type region located in the p-type semiconductor region below the first detector. A second-detector n-type deep contact plug is in contact with the second detector and extends to the surface of the p-type semiconductor region. A second pinned p-type region is formed at the surface of the p-type semiconductor region over the top of the second-detector n-type deep contact plug. A surface portion of the second-detector deep contact plug extends past an edge of the second pinned p-type region.

Abstract: A pixel array in an image sensor includes multiple pixels. The pixel array includes vertical shift registers for shifting charge out of the pixel array. The vertical shift registers can be interspersed between the pixels, such as in an interline image sensor, or the photosensitive areas in the pixels can operate as vertical shift registers. The pixels are divided into blocks of pixels. One or more electrodes are disposed over each pixel. Conductive strips are disposed over the electrodes. Contacts are used to connect selected electrodes to respective conductive strips. The contacts in at least one block of pixels are positioned according to one contact pattern while the contacts in one or more other blocks are positioned according to a different contact pattern. The different contact patterns reduce or eliminate visible patterns in the contact locations.

Abstract: A photoelectric conversion device including a pixel region having a photoelectric converter, and a transfer MOS transistor for transferring charges in the photoelectric converter to a floating diffusion, comprises a first insulating film continuously arranged to cover the photoelectric converter, and a first side surface and a first region of an upper surface of a gate electrode of the transfer MOS transistor while not arranged on a second region of the upper surface, the first insulating film being configured to function as an antireflection film, a contact plug connected with the floating diffusion, and a second insulating film continuously arranged to cover a periphery of the contact plug on the floating diffusion, and the second side surface and the second region while not arranged on the first region, the second insulating film being configured to function as an etching stopper in forming the contact plug.

Abstract: A CMOS image sensor for improving light sensitivity and peripheral brightness ratio, and a method for fabricating the same. The CMOS image sensor includes a substrate on which a light sensor and device isolating insulation films are formed, in which the top of the substrate is coated with a plurality of metal layers and oxide films; a plurality of reflective layers formed inside the metal layers, each being spaced apart; a color filter embedded in a groove formed by etching the oxide films inside the reflective layers by a predetermined thickness; a plurality of protrusions formed on both sides of the top of the color filter, each arranged at a predetermined distance from one another; a flat layer formed on the top of the protrusions and the oxide films; and a micro-lens formed on the top of the flat layer. The reflective layer disposed at the top of the photodiode is made of a material having a high reflectance and low absorptivity.

Abstract: A monolithic sensor for detecting infrared and visible light according to an example includes a semiconductor substrate and a semiconductor layer coupled to the semiconductor substrate. The semiconductor layer includes a device surface opposite the semiconductor substrate. A visible light photodiode is formed at the device surface. An infrared photodiode is also formed at the device surface and in proximity to the visible light photodiode. A textured region is coupled to the infrared photodiode and positioned to interact with electromagnetic radiation.

Abstract: An insulated gate silicon carbide semiconductor device is provided having small on-resistance in a structure obtained by combining the SIT and MOSFET structures having normally-off operation. The device includes an n? semiconductor layer on an SiC n+ substrate, a p-type base region and highly doped p-region both buried in the layer, a trench from the semiconductor layer surface to the p-base region, an n+ first source region in the surface of a p-type base region at the bottom of the trench, a p-type channel region in the surface of the sidewall of the trench, one end of which contacts the first source region, a gate electrode contacting the trench-side surface of the channel region via a gate insulating film, and a source electrode contacting the trench-side surface of the gate electrode via an interlayer insulating film and contacting the exposed first source region and p-base region at the bottom of the trench.

Abstract: Each pixel of a solid state imaging device comprises a first semiconductor layer formed on a substrate, having a first-conductive type; a second semiconductor layer formed thereon, having a second-conductivity type; a third semiconductor layer formed in the upper side of the second semiconductor layer, having the first-conductivity type; a fourth semiconductor layer formed in the outer side of the third semiconductor layer, having the second-conductivity type; a gate conductor layer formed on the lower side of the second semiconductor layer via an insulating film; and a fifth semiconductor layer formed on the top surfaces of the second semiconductor layer and third semiconductor layer, having the second-conductivity type, wherein the fifth semiconductor layer and fourth semiconductor layer are connected to each other, and at least the third semiconductor layer, upper region of the second semiconductor layer, fourth semiconductor layer, and fifth semiconductor layer are formed in an island.

Abstract: P type semiconductor well regions 8 and 9 for device separation are provided in an upper and lower two layer structure in conformity with the position of a high sensitivity type photodiode PD, and the first P type semiconductor well region 8 at the upper layer is provided in the state of being closer to the pixel side than an end portion of a LOCOS layer 1A, for limiting a dark current generated at the end portion of the LOCOS layer 1A. In addition, the second P type semiconductor well region 9 at the lower layer is formed in a narrow region receding from the photodiode PD, so that the depletion layer of the photodiode PD is prevented from being obstructed, and the depletion is secured in a sufficiently broad region, whereby enhancement of the sensitivity of the photodiode PD can be achieved.

Abstract: A method for fabricating a back-illuminated semiconductor imaging device on an ultra-thin semiconductor-on-insulator wafer (UTSOI) is disclosed. The UTSOI wafer includes a mechanical substrate, an insulator layer, and a seed layer. At least one dopant is applied to the semiconductor substrate. A first portion of an epitaxial layer is grown on the seed layer. A predefined concentration of carbon impurities is introduced into the first portion of the epitaxial layer. A remaining portion of the epitaxial layer is grown. During the epitaxial growth process, the at least one dopant diffuses into the epitaxial layer such that, at completion of the growing of the epitaxial layer, there exists a net dopant concentration profile which has an initial maximum value at an interface between the seed layer and the insulator layer and which decreases monotonically with increasing distance from the interface within at least a portion of at least one of the semiconductor substrate and the epitaxial layer.

Abstract: A solid state imaging device in which ? characteristic is obtained and enlargement of dynamic range is provided. The solid state imaging device of the present invention includes a vertical overflow function and has a feature in which potential of a semiconductor substrate is changed from a high potential to a low potential in a stepwise manner during a period from an exposure start to an exposure end.

Abstract: A solid-state image-capturing device which has built in an image-capturing area including a light receiving element provided on a semiconductor substrate, a substrate bias circuit, and a clamp circuit for receiving output of the substrate bias circuit and applying the output of the substrate bias circuit to the semiconductor substrate in accordance with a substrate pulse, comprises a substrate bias control circuit for controlling so as to reduce an electric current of the clamp circuit during a predetermined period.

Abstract: A part of a semiconductor layer directly under a light-receiving gate electrode functions as a charge generation region, and electrons generated in the charge generation region are injected into a part of a surface buried region directly above the charge generation region. The surface buried region directly under a first transfer gate electrode functions as a first transfer channel, and the surface buried region directly under a second transfer gate electrode functions as a second transfer channel. Signal charges are alternately transferred to an n-type first floating drain region and a second floating drain region through the first and second floating transfer channels.

Abstract: A CMOS image sensor with a many million pixel count. Applicants have developed techniques for combining its continuous layer photodiode CMOS sensor technology with CMOS integrated circuit lithography stitching techniques to provide digital cameras with an almost unlimited number of pixels. A preferred CMOS stitching technique exploits the precise alignment accuracy of CMOS stepper processes by using specialized mask sets to repeatedly produce a single pixel array pattern many times on a single silicon wafer with no pixel array discontinuities. The single array patterns are stitched together lithographically to form a pixel array of many million pixels. A continuous multilayer photodiode layer is deposited over the top of the many million pixel array to provide a many million pixel sensor with a fill factor of 100 percent or substantially 100 percent.

Abstract: A method for producing a solid-state imaging device, which including: a photoelectric conversion section; a charge transfer section having a charge transfer electrode; and an antireflection film covering a light-receiving region in the photoelectric conversion section, wherein forming the antireflection film includes: forming a sidewall on a lateral wall of the charge transfer electrode after forming the charge transfer electrode; forming an antireflection film on a substrate surface where the sidewall is formed; forming a resist on the antireflection film; melting and flattening the resist to expose the antireflection film on the charge transfer electrode; removing the antireflection film by using the resist as the mask; removing the sidewall; covering the charge transfer electrode with an insulating film; and forming a light-shielding film that reaches a level lower than the top surface of the antireflection film, and that surrounds the periphery of the antireflection film.

Abstract: A back irradiating type solid state imaging device comprises: a first semiconductor substrate; a plurality of photoelectric converting devices that receives a light incident from a back side of the first semiconductor substrate and are formed in a two-dimensional array on a surface side of the first semiconductor substrate; a CCD type signal reading section that are formed on the surface side of the first semiconductor substrate and reads detection signals of the photoelectric converting devices; and a MOS type signal reading section that are formed on the surface side of the first semiconductor substrate and reads detection signals of the photoelectric converting devices.

Abstract: A lateral power semiconductor device has a substrate and an isolation layer formed over the substrate for reducing minority carrier storage in the substrate. A well region is formed over the isolation layer. A source region, drain region, and channel region are formed in the well. A first region is formed on a surface of the lateral power semiconductor device adjacent to the source region. The lateral power semiconductor device has a body diode between the first region and drain region. The isolation layer confines the minority carrier charge from the body diode to a depth of less than 20 ?m from the surface of the lateral power semiconductor device. In one embodiment, the isolation layer is a buried oxide layer and the substrate is an n-type or p-type handle wafer. Alternatively, the isolation layer is an epitaxial layer and the substrate is made with N+ or P+ semiconductor material.

Abstract: An imaging device includes a first electrode for generating an electric field storing signal charges, a charge multiplication section for multiplying the stored signal charges, a second electrode for generating the electric field in the charge multiplication section, a voltage conversion portion for converting the signal charges into a voltage, a third electrode for transferring the signal charges to the voltage conversion portion, provided between the first electrode and the voltage conversion portion, wherein the second electrode is provided on a side opposite to the third electrode and the voltage conversion portion with respect to the first electrode.

Abstract: The present invention relates to a technology for reducing dark current noise by discharging electrons accumulated on a surface of an image sensor photodiode. In an N-type or P-type photodiode, a channel is formed between the photodiode and a power voltage terminal, so that electrons (or holes) accumulated on a surface of the photodiode are discharged to the power voltage terminal through the channel.

Abstract: A CMOS integrated circuit has NMOS and PMOS transistors therein and an insulating layer extending on the NMOS transistors. The insulating layer is provided to impart a relatively large tensile stress to the NMOS transistors. In particular, the insulating layer is formed to have a sufficiently high internal stress characteristic that imparts a tensile stress in a range from about 2 gigapascals (2 GPa) to about 4 gigapascals (4 GPa) in the channel regions of the NMOS transistors.

Abstract: An image sensor includes (a) a plurality of pixels, wherein each pixel comprises: (i) at least one photosensor; (ii) at least one transfer gate connecting the photosensor to a floating diffusion; (iii) an output transistor connected to the floating diffusion; (iv) a first reset transistor connected between the floating diffusion and a summing node; (v) a second reset transistor connected to the summing node; and (b) a first summing transistor connecting together the summing nodes of two or more pixels.

Abstract: A solid-state imaging apparatus is provided. The solid-state imaging apparatus includes a solid-state imaging device, an ?-ray shielding layer formed so as to cover at least an imaging area of the solid-state imaging device and a cover glass provided above the ?-ray shielding layer.

Abstract: A solid state imaging apparatus comprises: a semiconductor substrate; a photoelectric converting portion on the semiconductor substrate; a light shielding film in a region excluding a light receiving surface of the photoelectric converting portion; and a P-type impurity layer between a lower surface of the light shielding film and the semiconductor substrate.

Abstract: Optical structures having an array of protuberances between two layers having different refractive indices are provided. The array of protuberances has vertical and lateral dimensions less than the wavelength range of lights detectable by a photodiode of a CMOS image sensor. The array of protuberances provides high transmission of light with little reflection. The array of protuberances may be provided over a photodiode, in a back-end-of-line interconnect structure, over a lens for a photodiode, on a backside of a photodiode, or on a window of a chip package.

Abstract: A pixel for an imager is disclosed that includes at least one electron multiplication (EM) gain stage configured in a loop and electrically coupled to a charge collection region and a charge readout region, the charge collection region being configured to generate a charge packet, the EM gain stage being configured to amplify the charge packet by impact ionization and to circulate the charge packet a predetermined number of times in one direction around the loop, the charge readout region being configured to receive the amplified charge packet and convert the amplified charge to a measurable signal. The at least one EM gain stage, the charge collection region, and the charge readout region can be formed monolithically in an integrated circuit. The pixel can be manufactured using a CMOS process. The pixel can further include a second EM gain stage formed in the integrated circuit to increase the amount of amplification around the loop.

Abstract: A solid state imaging device in which ? characteristic is obtained and enlargement of dynamic range is provided. The solid state imaging device of the present invention includes a vertical overflow function and has a feature in which potential of a semiconductor substrate is changed from a high potential to a low potential in a stepwise manner during a period from an exposure start to an exposure end.

Abstract: P type semiconductor well regions 8 and 9 for device separation are provided in an upper and lower two layer structure in conformity with the position of a high sensitivity type photodiode PD, and the first P type semiconductor well region 8 at the upper layer is provided in the state of being closer to the pixel side than an end portion of a LOCOS layer 1A, for limiting a dark current generated at the end portion of the LOCOS layer 1A. In addition, the second P type semiconductor well region 9 at the lower layer is formed in a narrow region receding from the photodiode PD, so that the depletion layer of the photodiode PD is prevented from being obstructed, and the depletion is secured in a sufficiently broad region, whereby enhancement of the sensitivity of the photodiode PD can be achieved.

Abstract: An HCCD includes a channel 21 that transfers electric charges in an X direction, a channel 25 that transfers the electric charges in a Z1 direction, a channel 23 that transfers the electric charges in a Z2 direction, and a channel 22 that connects the channels 23, 25 to the channel 21. The following relation is satisfied in impurity concentration of the channels: channel 21 channel 22 channel 23, 25. A fixed DC voltage is applied to branch electrodes 12a, 12b above the channel 22. The channel 22 has protrusion portions 19 that protrude inward from an outer circumference, which connects T1 and T2, and an outer circumference, which connects T3 and T4. The protrusion portions 19 causes charges below the transfer electrode 11b to move near the center of the channel 22 in a Y direction. Thereby, the travel distance of the charges in the channel 22 is reduced.

Abstract: The attenuation of an RF signal on a metal trace in a semiconductor die is substantially reduced by utilizing a number of RF blocking structures that lie on the surface of the substrate directly below the metal trace that carries the RF signal. The RF blocking structures include an isolation ring, and one or more doped regions that are formed inside the isolation ring.

Abstract: In a case when a structure of forming a p+ layer on a substrate rear surface side is employed in order to prevent dark current generation from the silicon boundary surface, various problems occur. According to this invention, an insulation film 39 is provided on a rear surface on a silicon substrate 31 and a transparent electrode 40 is further provided thereon, and by applying a negative voltage with respect to the potential of the silicon substrate 31 from a voltage supply source 41 to the insulation film 39 through the transparent electrode 40, positive holes are accumulated on a silicon boundary surface of the substrate rear surface side and a structure equivalent to a state in which a positive hole accumulation layer exists on aforesaid silicon boundary surface is to be created. Thus, various problems in the related art can be avoided.

Abstract: A CMOS active pixel sensor (APS) cell structure includes at least one transfer gate device and method of operation. A first transfer gate device comprises a diodic or split transfer gate conductor structure having a first doped region of first conductivity type material and a second doped region of a second conductivity type material. A photosensing device is formed adjacent the first doped region for collecting charge carriers in response to light incident thereto, and, a diffusion region of a second conductivity type material is formed at or below the substrate surface adjacent the second doped region of the transfer gate device for receiving charges transferred from the photosensing device while preventing spillback of charges to the photosensing device upon timed voltage bias to the diodic or split transfer gate conductor structure.

Abstract: A pixel sensor structure, method of manufacture and method of operating. Disclosed is a buffer pixel cell comprising a barrier region for preventing stray charge carriers from arriving at a dark current correction pixel cell. The buffer pixel cell is located in the vicinity of the dark current correction pixel cell and the buffer pixel cell resembles an active pixel cell. Thus, an environment surrounding the dark current correction pixel cell is similar to the environment surrounding an active pixel cell.

Abstract: An imager includes a two-dimensional array of photosensors, each photosensor having a center point. A non-telecentric lens is positioned over the two-dimensional array of photosensors, and a two-dimensional array of microlenses is positioned over the two-dimensional array of photosensors. Each microlens is associated with a corresponding photosensor, and each microlens has a center point. A color filter array is positioned over the two-dimensional array of photosensors. The color filter array includes a plurality of color filter areas. Each color filter area is associated with a corresponding photosensor and has a center point. A layer of transmissive apertures is further positioned over the two-dimensional array of photosensors. Each aperture is associated with a corresponding photosensor and having a center point. The microlens is positioned over the corresponding photosensor such that the center point of the microlens is offset from the center point of the corresponding photosensor.

Abstract: An image sensor having a plurality of pixels; each pixel includes one or more photosensitive elements that collect charge in response to incident light; one or more transfer mechanisms that respectively transfer the charge from the one or more photosensitive elements; a charge-to-voltage conversion region having a capacitance, and the charge-to-voltage region receives the charge from the one or more photosensitive elements; a first reset transistor connected to the charge-to-voltage conversion region; a second reset transistor connected to the first reset transistor, which in combination with the first reset transistor, selectively sets the capacitance of the charge-to-voltage conversion regions from a plurality of capacitances.

Abstract: A solid-state imaging device including: a plurality of photodiode parts (1); a plurality of vertical charge transfer parts (2) each of which reads out a signal charge and transfers the signal charge in a vertical direction; and a plurality of shade films (5) that have conductivity, which supplies a transfer pulse via the shade film (5), is used. The vertical charge transfer parts (2) respectively have transfer channels (13) and transfer electrodes (3). The shade film (5) is formed above the corresponding vertical charge transfer part (2) via an insulation layer (21) that insulates the shade film (5) from the transfer electrodes (3). The insulation layer (21) has a thick part (8) in a part of the insulation layer (21) where the shade film (5) is overlapped on a side of the photodiode part (1) that is a subject to be read out by the vertical charge transfer part (2).

Abstract: An electrode structure having at least two oxide layers that more reliably switch and operate without the use of additional devices and a non-volatile memory device having the same are provided. The electrode structure may include a lower electrode, a first oxide layer formed on the lower electrode, a second oxide layer formed on the first oxide layer and an upper electrode formed on the second oxide layer wherein at least one of the first and second oxide layers may be formed of a resistance-varying material. The first oxide layer may be formed of an oxide having a variable oxidation state.

Abstract: A solid state imaging apparatus comprises: a semiconductor substrate; a photoelectric converting portion on the semiconductor substrate; a light shielding film in a region excluding a light receiving surface of the photoelectric converting portion; and a P-type impurity layer between a lower surface of the light shielding film and the semiconductor substrate.

Abstract: According to one exemplary embodiment, a method includes a step of forming a number of trenches in a dielectric layer, where the dielectric layer is situated over a wafer. The method further includes forming a metal layer over the dielectric layer and in the trenches such that the metal layer has a dome-shaped profile over the wafer. The method further includes performing a planarizing process to form a number of interconnect lines, where each of the interconnect lines is situated in one of the trenches. The dome-shaped profile of the metal layer causes the interconnect lines to have a reduced thickness variation across the wafer after performing the planarizing process. The interconnect lines are situated in an interconnect metal layer, where the dome-shaped profile of the metal layer causes the interconnect metal layer to have increased sheet resistivity uniformity across the wafer after performing the planarizing process.

Abstract: An image sensor and fabricating method thereof are provided. A gate electrode is formed on a semiconductor substrate with a photodiode on one side and a low-concentration drain on the other side. A silicide blocking pattern covers the photodiode, the gate electrode, and part of the low-concentration drain, such that an aperture exposes a portion of the low-concentration drain. A high-concentration drain is formed in the substrate under the aperture.

Abstract: A photo sensor includes a first substrate, a switching element and a second substrate. The switching element is disposed at the first substrate and defined by a control electrode, and first and second current electrodes. The switching element includes a channel disposed between the first and second current electrodes. The channel has a first length to receive an incident external light. The second substrate includes a light receiving unit that is disposed corresponding to the channel. The light receiving unit has a second length longer than the first length and shorter than a third length of the control electrode.

Abstract: At least a p-type and n-type semiconductor device deposited upon a semiconductor wafer containing metal or metal alloy gates. More particularly, a complementary metal-oxide-semiconductor (CMOS) device is formed on a semiconductor wafer having n-type and p-type metal gates.

Abstract: Semiconductor detector includes semiconductor substrate (HK), source region (S), drain region (D), external gate region (G) and inner gate region (IG) for collecting free charge carriers generated in semiconductor substrate, wherein inner gate region is arranged in semiconductor substrate at least partially under external gate region to control conduction channel (K) from below as a function of the accumulated charge carriers, as well as with clear contact (CL) for the removal of the accumulated charge carriers from inner gate region, as well as with drain-clear region (DCG) that can be selectively controlled as an auxiliary clear contact or as a drain. Barrier contact (B) is arranged in a lateral direction between external gate region and drain-clear region to build up a controllable potential barrier between inner gate region and clear contact that prevents the charge carriers accumulated in inner gate region from being removed by suction from clear contact.

Abstract: A plurality of optical sensors (4) are arranged in a surface region of a semiconductor substrate (6) in a matrix pattern, and electric charge generated by the optical sensors (4) is transferred by first and second transfer electrodes (12 and 14) embedded under the optical sensors (4). The semiconductor substrate (6) is constructed by laminating a support substrate (16) composed of silicon, a buffer layer (18), and a thin silicon layer (20) composed of single-crystal silicon. p? regions (26) (overflow barrier) and n-type regions (28) which function as transfer paths are formed under the optical sensors (4). The first and the second transfer electrodes (12 and 14) are disposed between the buffer layer (18) and the n-type regions (28), and an insulating film (30) is interposed between the n-type regions (28) and the first and the second transfer electrodes (12 and 14). In this structure, the light-receiving area is large since the transfer electrodes are not disposed in the front region.

Abstract: A method of manufacturing a flash memory device wherein a stacked structure of an oxide and nitride or the reverse is applied to insulation spacers provided on sidewalls of gates for forming source/drain regions. After completing the source/drain regions, spacers are formed on sidewalls of the gates by using an oxide film as a contacting buffer, thus minimizing the interference between gates and reducing the stress to cells, overcoming the disturbance of threshold voltage.

Abstract: A method of forming an opening through a substrate having a first side and a second side opposite the first side includes forming spaced etch stops in the first side of the substrate, etching into the substrate from the second side toward the first side to the spaced etch stops, and etching into the substrate between the spaced etch stops from the second side. Etching into the substrate to the spaced etch stops includes forming a first portion of the opening and etching into the substrate between the spaced etch stops includes forming a second portion of the opening.

Abstract: This imaging apparatus has pixels arranged in a matrix shape on a substrate, each of which has a conversion element and the first TFT, wherein the first TFT is connected to the first gate wiring and signal wiring, and the conversion element is connected to bias wiring. The imaging apparatus has the second TFT 6 that is arranged outside a region in which the pixels are arranged. The signal wirings are mutually connected through the second TFT 6 outside a region in which the pixels are arranged. When the apparatus is driven, the second TFT is turned off.

Abstract: A microcrystalline germanium image sensor array. The array includes a number of pixel circuits fabricated in or on a substrate. Each pixel circuit comprises a charge collecting electrode for collecting electrical charges and a readout means for reading out the charges collected by the charge collecting electrode. A photodiode layer of charge generating material located above the pixel circuits convert electromagnetic radiation into electrical charges. This photodiode layer includes microcrystalline germanium and defines at least an n-layer, and i-layer and a p-layer. The sensor array also includes and a surface electrode in the form of a grid or thin transparent layer located above the layer of charge generating material. The sensor is especially useful for imaging in visible and near infrared spectral regions of the electromagnetic spectrum and provides imaging with starlight illumination.

Abstract: A complementary metal oxide semiconductor field effect transistor (CMOS-FET) image sensor. An active photosensing pixel is formed on a substrate. At least one side of the pixel has a width equal to or less than approximately 3 ?m. At least one dielectric layer is disposed on the substrate covering the pixel. A color filter is disposed on the least one dielectric layer. A microlens array is disposed on the color filter of the pixel, and the sum of the thickness of all dielectric layers and the color filter divided by the pixel width is equal to or less than approximately 1.87.

Abstract: A diode structure having high ESD stability is described. Other embodiments provide an integral power switching arrangement having an integrated low leakage diode.

Abstract: Fabrication of a light emitting device includes etching of a substrate of the light emitting device. The etch may be an aqueous etch sufficient to increase an amount of light extracted through the substrate. The etch may be a direct aqueous etch of a silicon carbide substrate. The etch may remove damage from the substrate that results from other processing of the substrate, such as damage from sawing the substrate. The etch may remove an amorphous region of silicon carbide in the substrate.