Abstract: Each unit pixel includes a photodiode, a reading selection transistor, a reading transistor, an amplifying transistor, a reset transistor, and a horizontal selection transistor, and thus a MOS image sensor of a dot-sequential reading 5-Tr type is formed. The reading selection transistor and the reading transistor are formed with a two-layer gate structure, and gate potential of the reading selection transistor and the reading transistor is set to a negative potential. Thereby, a lower layer of a gate region of the reading transistor and the reading selection transistor is controlled to a negative potential. Thus, depletion in the lower layer region is suppressed to reduce leakage current.

Abstract: In a CCD image sensor, a CCD line memory is disposed between each vertical charge transfer device and a horizontal charge transfer device to selectively transfer charges from each vertical charge transfer device to the horizontal charge transfer device. A discharge drain is disposed along the horizontal charge transfer device to selectively discharge charges from vertical charge transfer devices via the horizontal charge transfer device to the discharge drain. Therefore, image data in which the numbers respectively of the vertical and horizontal pixels are reduced can be generated.

Abstract: A solid-state image sensing device including an image sensing region in which a matrix of unit pixels, each including a photodiode in a surface portion of a semiconductor substrate, is provided; a read transistor connected between a respective photodiode and a detection node; an amplifying transistor connected to the detection node so as to amplify the signal charge output to the detection node and to output a pixel signal to a signal output line reading out the pixel signal output; a reset transistor connected to the detection node and to a discharge node; and an address transistor connected to a source of the amplifying transistor for selecting an address of the photodiode when an address signal is supplied to a gate.

Abstract: A solid-state image sensor has a readout architecture that incorporates charge multiplier cells into a horizontal register of a CCD image sensor, and includes a first CCD register adjacent to at least a second CCD register and coupled to the said first register through a charge overflow barrier. A high Dynamic Range readout system results in which the DR is not restricted by the voltage swing limitations on the charge detection node. As the charge is multiplied, the horizontal register structure increases in width and more charge multiplication gates are added per stage. A charge overflow region follows the charge multiplier. In this region the amount of charge that exceeds a certain predetermined threshold is split off into another register. A detection node that has different conversion sensitivity may terminate this register. The process of charge overflow and splitting off may continue for more than two steps.

Abstract: A programmable resistance memory element comprising an adhesion layer between the programmable resistance material and at least one of the electrodes. Preferably, the adhesion layer is a titanium rich titanium nitride composition.

Abstract: The driving device of a solid-state imaging device comprises a driving unit for driving the solid-state imaging device in either an addition driving mode in which a plurality of pixels are added and read as a single pixel or a non-addition driving mode, and a substrate bias voltage supply for applying a bias voltage to the substrate of the solid-state imaging device according to the driving mode. The substrate bias voltage is set according to the number of pixels added in the addition driving mode so that the overflow level of the charge accumulating portion may be lower in the addition driving mode than in the normal driving mode. This suppresses the input of excess charges to the horizontal transfer path even in the addition driving mode, thereby preventing the generation of horizontal streak noise.

Abstract: A charge detection system used in an image sensor consists of the vertical punch through transistor with the gate surrounding its source and connected to it. The charge detector has a large conversion gain, high dynamic range, low reset feed through, and low noise. It senses charge nondestructively, which avoids generation of kTC noise. Additional embodiments of the invention include a standard reset gate option, a resistive reset gate option, and a lateral punch through transistor reset option to minimize the reset feed through. The charge detection system can be used in all know CCD image sensor architectures as well as in most CMOS image sensor architectures.

Abstract: A drain region is formed along a horizontal charge transfer channel constituting a horizontal charge transfer element, and a barrier region for charges is formed between the horizontal charge transfer channel and drain region. A two-electrode element is formed by using the horizontal charge transfer channel, barrier region and drain region. A solid state image pickup device can be manufactured with high productivity, which device can drain charges in the horizontal charge transfer element at high speed.

Abstract: A pixel of a semiconductor-based image detector includes a photodetector, at least one switching device serially connected to the photodetector and a bypass device interposed between the photodetector and a power supply voltage. Accordingly, even though excess charges may be generated in the photodetector, the excess charges flow into the power supply through the bypass device. Blooming can thereby be reduced or suppressed.

Abstract: In an MOS type solid-state image pickup device in which unit pixels each including a photodiode, a transfer transistor for transferring the signal of the photodiode to a floating node N11, an amplifying transistor for outputting the signal of the floating node to a vertical signal line, and a reset transistor for resetting the floating node are arranged in a matrix form, a P-type MOS transistor is connected between a drain line to which the drain of the reset transistor is connected and a V shift register for selectively supplying the reset voltage to the drain line, and the potential of the floating node is set to the channel voltage of the P-type MOS transistor at the non-selection time.

Abstract: An anti-blooming charge accumulation pixel using an anti-blooming element coupled to the pixel prevents blooming by ensuring that a voltage of a charge accumulation device of the pixel is always returned to a clamping voltage following comparison events. The anti-blooming element is used to return the voltage across a photodiode to the supply voltage when both a low voltage comparison and a high voltage comparison have occurred. A control block is used to determine an input signal to the anti-blooming element based upon the result of a low voltage comparison and a high voltage comparison. The input signal can be used to drive the anti-blooming element to a desired logic level, thereby causing the voltage across the charge accumulation device to be the clamping voltage. The use of the anti-blooming element eliminates blooming to adjacent pixels, independent of an integration time of the pixel.

Abstract: The present invention provides a method of manufacturing an interdigitated semiconductor device. In one embodiment, the method comprises simultaneously forming first electrodes adjacent each other on a substrate, forming a dielectric layer between the first electrodes, and creating a second electrode between the first electrodes, the second electrode contacting the dielectric layer between the first electrodes to thereby form adjacent interdigitated electrodes. An interdigitated capacitor and a method of manufacturing an integrated circuit having an interdigitated capacitor are also disclosed.

Abstract: The solid-state imaging device according to one embodiment of the present invention includes a semiconductor substrate, a plurality of photoelectric conversion regions arrayed in the vertical direction and the horizontal direction on the surface of the substrate, and an electric charge transfer region disposed between the photoelectric conversion regions adjacent in the horizontal direction of the substrate. The substrate comprises a n-type semiconductor substrate, a first p-type impurity region formed on the n-type semiconductor substrate, a semiconductor regions formed on the first p-type impurity region, and a second p-type impurity region disposed below the electric charge transfer region. The photoelectric conversion region and the electric charge transfer region are n-type impurity regions formed on the surface portion of the semiconductor region.

Abstract: There is provided a solid-state image sensor including (a) a plurality of first charge transfer sections each for vertically transferring electric charges, formed on a surface of a semiconductor layer, (b) a second charge transfer section for horizontally transferring electric charges, formed adjacent to one ends of the first charge transfer sections, the second charge transfer section including a charge barrier region and a charge accumulating region, (c) a first potential barrier section located adjacent to the second charge transfer section, (d) an excessive charge exhausting section located adjacent to the first potential barrier section, and (e) a plurality of second potential barrier sections located in the first potential barrier section, the second potential barrier section being spaced away from adjacent ones. The solid-state image sensor makes it possible to prevent signal charges from leaking into the excessive charge exhausting section, which ensures enhancement in a charge transfer efficiency.

Abstract: An integrated memory location structure includes an isolated semiconductor layer between the source region and the drain region of a transistor, and between the channel region and the control gate of the transistor. The isolated semiconductor layer includes two potential well zones separated by a potential barrier zone under the control gate of the transistor. A write circuit biases the memory location structure to confine charge carriers selectively in one of the two potential well zones. A read circuit biases the memory location structure to measure the drain current of the transistor and determine therefrom the stored logic state imposed by the position of the charges in one of the potential well zones.

Abstract: A method of driving a solid-state imaging device to increase the dynamic range of a CCD image sensor is described. The imaging device has a plurality of light receiving members arranged in a matrix in horizontal and vertical directions. In addition, a plurality of columns of vertical CCD registers associate with the light-receiving members for storing signal charges received from a plurality of light receiving members. A row of horizontal CCD registers is disposed and connected with one end of each columns of vertical CCD registers to transfer the signal charges received from those vertical CCD registers to an output circuit member. The method comprises receiving the signal charges from an object by those light-receiving members for a time period Cs firstly in a normal fashion in BLANKING “high” period.

Abstract: A solid-state imaging device includes an imaging area including a plurality of pixels arranged in columns and rows, and peripheral circuitry for selecting at least one of the pixels. Each said pixel includes: a photoelectric transducer for creating electric charges by photoelectric conversion and storing the charges therein; means for storing the charges read out from the photoelectric transducer; a transfer electrode, provided between the photoelectric transducer and the storage means, for reading out the charges from the photoelectric transducer to the storage means; an amplifier for sensing a variation in potential in the storage means; and a reset electrode for discharging the charges, stored in the storage means, to a power supply, thereby resetting the potential in the storage means.

Abstract: An integrated circuit is provided that includes a substrate incorporating a semiconductor photodiode device having a p-n junction. The photodiode device includes at least one capacitive trench buried in the substrate and connected in parallel with the junction. In a preferred embodiment, the substrate is formed from silicon, and the capacitive trench includes an internal doped silicon region partially enveloped by an insulating wall that laterally separates the internal region from the substrate. Also provided is a method for fabricating an integrated circuit including a substrate that incorporates a semiconductor photodiode device having a p-n junction.

Abstract: A current-amplifying logarithmic mode CMOS image sensor having a first MOS transistor, a second MOS transistor, a third MOS transistor and a sensing device. The gate terminal and the first connection terminal of the first MOS transistor are tied to a high voltage terminal. The gate terminal of the second MOS transistor and the second connection terminal of the first MOS transistor are tied to a node point. The first connection terminal of the second MOS transistor is tied to the high voltage terminal. The gate terminal of the third MOS transistor is tied to a row select signal. The first connection terminal of the third MOS transistor is tied to the second connection terminal of the second MOS transistor. The second terminal of the third MOS transistor serves as a voltage output terminal. The sensing device includes a PMOS transistor and a lateral bipolar junction transistor.

Abstract: Image sensors with an enhanced QE and MTF in the NIR spectral region are fabricated on the standard substrates. This is achieved by replacing the p+ type doped layer, typically present under the thick field oxide in the inactive regions of the sensor, with an n+ type doped layer. The n+ type layer, which is biased at the Vdd potential, surrounds the entire image sensor array as a guard ring and is separated from the CCD or CMOS array pixels by a suitable potential barrier. The potential barrier prevents collected charge from escaping into the n+ layer regions. Additional embodiments include output diode and MOS transistor designs that use field plates for creating potential barriers that separate these devices from the n+ type doped field regions.

Abstract: Solid-state imaging devices and cameras using such devices are provided. The devices detect changes in light quantity, directly incident to a light-receiving portion, in real-time and then read light information at an optimum exposure level whenever estimates of the quantity of incident light are difficult to obtain and whenever the quantity of incident light suddenly changes from an estimated value. To such end, the devices include a charge-transfer portion that generates and stores signal charges in response to incident light and then transfers the signal charges, an output portion that outputs the signal charge as an electrical signal, a semiconductor region that generates an optical current in proportion to the quantity of incident light, a shading membrane having an aperture portion formed on the semiconductor region, and a read portion that reads out the optical current, generated by light incident to the semiconductor region through the aperture portion, to the exterior of the semiconductor region.

Abstract: Disclosed is a color linear image sensor having a small line-to-line distance, which comprises signal charge storage sections adjacent to light receiving sections. Signal charges are read by signal charge reading sections from the signal charge storage sections to signal charge transfer sections, and thereby residual images are prevented from being generated. Each of the signal charge reading sections is electrically connected with a portion of the signal charge transfer section which is adjacent to the signal charge reading section, and driving pulses are made common (&phgr;1 (TG)). Alternatively, each of the signal charge storage sections is electrically connected with a portion of the signal charge transfer section which is not adjacent to the signal charge reading section, and driving pulses are made common ((&phgr;2 (ST)). Accordingly, the number of wiring lines (pulse lines) arranged between the light receiving sections of respective colors is reduced by one.

Abstract: An NMOS transistor circuit has a surge protection circuit connected in parallel with the NMOS transistor. A resistor is connected between a back gate of the NMOS transistor and ground. As a result, an input impedance higher than the input impedance of the surge protection circuit is applied to a semiconductor terminal at the electrode pad side of the NMOS transistor.

Abstract: In an image sensing array, the structure of the image sensor pixel is based on a vertical punch through transistor with a junction gate surrounding its source and connected to it, the junction gate being further surrounded by an MOS gate. The new pixel has a large conversion gain, high dynamic range, blooming protection, and low dark current. It senses charge nondestructively with a complete charge removal, which avoids generation of kTC noise. The pixel fabrication is compatible with CMOS processing that includes two metal layers. The array also includes the pixel reset through column sense lines, polysilicon field plate in the image-sensing area for improved pixel isolation, denser pixel packing, and either n-channel or p-channel addressing transistor.

Abstract: A source region and drain region are formed in a surface region of a first semiconductor region. Moreover, a second semiconductor region connected to the drain region is formed in the surface region of the first semiconductor region. A third semiconductor region is formed in the first semiconductor region under the second semiconductor region, connected to the second semiconductor region, and accumulates signal charges in accordance with an incident light. A fourth semiconductor region is formed in the surface region of the first semiconductor region between the drain region and source region. Moreover, these source region, drain region, second semiconductor region, and third semiconductor region constitute a pixel, and different voltages are supplied to the drain region in an accumulation period of the signal charges in the pixel, signal readout period, and discharge period of the signal charges.

Abstract: An image sensor having an anti-blooming structure, where the image sensor comprises a substrate of a first conductivity type; a dielectric having a first thin portion and a second thick portion; a buried channel of the second conductivity type within the substrate substantially spanning the first thin portion; and a lateral overflow drain region of the second conductivity type disposed substantially in its entirety spanning a portion of the second thick portion for collecting excess photogenerated charges for preventing blooming.

Abstract: A high-concentration light-receiving N-layer 32 is formed by ion implantation in a region near a substrate surface, and a low-concentration N-type epitaxial layer 25 is formed by epitaxial growth in a deeper region. The depletion layer of a photodiode is thus expanded to a deep portion of the substrate by the low-concentration N-type region 25, by which a photoelectric conversion effect on incident light of a long wavelength is increased to improve sensitivity. In the above stage, a deepest potential portion is formed on the substrate surface side. Therefore, a depletion voltage can be prevented from rising. Further, an intermediate-concentration N-type epitaxial layer 23 and a high-concentration N-type epitaxial layer 22 are formed in a stack of two layers by epitaxial growth in a region deeper than a region in which a first P-type layer 24, or a barrier region is formed, by which a shutter voltage can be prevented from rising.

Abstract: A solid state image sensor is provided with a primary first-conductivity-type semiconductive region which serves as a charge storage region of a photo-sensing area and a secondary first-conductivity-type semiconductive region for enlarging a charge collecting region of the photo-sensing area.

Abstract: A structure of a new active pixel sensor cell formed in a semiconductor substrate is disclosed. An n-type region is formed in the substrate extending to the surface. Two p+ regions are formed in the n-type region, both extending to the surface and covering almost all the active area of the new active pixel sensor cell. The p+ region forming the p+ node of the photodiode has a substantially larger surface area than the p+ region forming the p+ node of the output diode. Isolation regions are formed over those portions of the new active pixel cell periphery that will not be adjacent to other new active pixel sensor cells. A polysilicon floating gate is disposed over a dielectric layer formed over the surface. The floating gate overlaps portions of both p+ regions and the floating gate is connected to photodiode p+ region by a conducting region passing through the dielectric layer.

Abstract: There is provided a solid state imaging device using a MOS image sensor of a threshold voltage modulation system employed in a video camera, an electronic camera, an image input camera, a scanner, a facsimile, or the like. In configuration, in the solid state imaging device that comprises a photo diode formed in a second semiconductor layer 15a of opposite conductivity type in a first semiconductor layer 12 and 32 of one conductivity type, and a light signal detecting insulated gate field effect transistor formed in a fourth semiconductor layer 15b of opposite conductivity type in a third semiconductor layer 12 of one conductivity type adjacently to the photo diode, a carrier pocket 25 is provided in the fourth semiconductor layer 15b, and a portion of the first semiconductor layer 12, 32 under the second semiconductor layer 15a is thicker than a portion of the third semiconductor layer 12 under the fourth semiconductor layer 15b in a depth direction.

Abstract: A barrier area is located adjacent a horizontal transfer area and spaced from a field insulating area. The barrier area includes an insulating layer and a conductor extending from the horizontal transfer layer over the surface of a semiconductor substrate, a barrier layer of a second conductivity type formed under the surface of the semiconductor substrate and adjacent a first impurity layer of a first conductivity type of the horizontal transfer area, and a second impurity layer extending from the horizontal transfer area and formed under the barrier layer. A discharge area is located between the barrier area and the field insulating area.

Abstract: An image sensor includes a plurality of unit pixels for sensing a light beam to generate an image data. Each unit pixel includes a light sensing element for sensing a light beam incident thereto and generating photoelectric charges, a transferring unit for transferring the photoelectric charges to a sensing node, a first resetting unit for making a fully depleted region within the light sensing element and resetting the sensing node by providing a power supply voltage to the sensing node, and a second resetting unit for transferring excess charges generated in the light sensing element to a power line when the sensing node is reset.

Abstract: A select gate transistor has a select gate electrode composed of a first-level conductive layer and a second-level conductive layer. The first-level conductive layer has a plurality of contact areas. The second-level conductive layer has its portions removed that are located above the contact areas. Two adjacent select gate electrodes that are adjacent to each other in the column direction are arranged such that the contact areas of one select gate electrode are not opposed to the contact areas of the other select gate electrode. One select gate electrode has its first- and second-level conductive layers removed in their portions that are opposed to the contact areas of the other select gate electrode.

Abstract: A back thinned CCD has at least first and second parallel n− signal channel segments and a p++ channel stop region between the signal channels.

Abstract: There is provided a method for fabricating a CMOS image sensor having enhanced reliability and light sensitivity, which comprises the steps of providing a substrate including photosensitive elements and metal wire; forming a first protecting film for protecting the elements over the substrate, covering the metal wire; forming a flattened spin-on-glass film on the first protecting film; forming a second protecting film for protecting the elements on the spin-on-glass film; forming color filter patterns on the second protecting film; forming a photoresist film for flattening on the color filter patterns and the second protecting film; and forming microlenses on the photoresist film. By using the flattened SOG film and a photoresist for flattening and pad opening, the present invention can accomplish the thickness uniformity of the color filter corresponding to each unit pixel, the wire-bonding pad devoid of the residuals of the color filter materials and the figure uniformity of the microlenses.

Abstract: A solid-state image sensing device includes photoelectric conversion portions, vertical charge transfer portions, a horizontal charge transfer portion, an unwanted charge removing portion, and a potential barrier portion. The photoelectric conversion portions are arranged on an n-type semiconductor substrate. The vertical charge transfer portions are respectively arranged adjacent to the photoelectric conversion portions, and have a first p-type well layer and a first n-type semiconductor region. The horizontal charge transfer portion is arranged adjacent to one end side of the vertical charge transfer portions, and has a second p-type well layer and a second n-type semiconductor region. The unwanted charge removing portion is arranged adjacent to the horizontal charge transfer portion to remove an unwanted charge overflowing from the horizontal charge transfer portion. The unwanted charge removing portion has a third p-type well layer and a third n-type semiconductor region.

Abstract: The image sensing device includes an image sensing area 22 having an antiblooming drain structure; and a frame memory area 24 coupled to the image sensing area 22 for storing charge from the image sensing area, wherein during charge integration, the antiblooming drain is biased at a first level, and during charge transfer to memory, the antiblooming drain is biased at a second level such that the image sensing area 22 will have a higher charge capacity than during the charge integration.

Abstract: P-type ion implantation is done in N well 15, so as to form a charge drain control layer 17 and form a photodiode N well 16 and OFD drain 5, the result being that, even if there is variation in the potential of the photodiode N well 16 making up the photodiode, because the variation in the potential of the charge drain control layer 17 is in the same direction as the potential of the photodiode N well 16, so that variation does not occur in the maximum amount of electrical charge that can be accumulated, the result being that there is no variation in the signal in the saturation condition.

Abstract: A photoelectric conversion device comprises a semiconductor substrate, a same-dopant-type semiconductor layer, a photodiode having a charge-accumulation region, a JFET (which has a gate region, a source region, a channel region, and a drain region, the drain region electrically connected to the substrate 100), a transfer gate for transferring a charge from the photodiode to the gate region, and a reset drain having a charge-drain region for draining excess charges generated by the photodiode, the reset drain also controlling the electric potential of the gate region. Two overflow-control regions are included, one at the boundary between the charge-accumulation region and the charge-drain region within the device, one at the boundary between the charge-accumulation region and the charge-drain region of an adjacent device.

Abstract: A solid state image sensing device comprises a cell area, located at a semiconductor substrate, including photoelectric conversion portions and charge transfer portions and a peripheral circuit area formed around the cell area located at the semiconductor substrate. The peripheral circuit area includes a first p.sup.+ -type semiconductor region and an insulating film with a relatively large thickness formed on the first p.sup.+ -type semiconductor region. The cell area further includes a second p.sup.+ -type semiconductor region and an insulating film with a relatively small thickness formed on the second p.sup.+ -type semiconductor region. The majority of the insulating film with the relatively large thickness is formed by means of a CVD process.

Abstract: A self aligned, lateral-overflow drain antiblooming structure that is insensitive to drain bias voltages and therefore has improved insensitivity to process variations. The length of the antiblooming barrier regions are easily adjusted and determined by photolithography. The self aligned, lateral-overflow drain (LOD) antiblooming structure results in a design that saves space, and hence, improves overall sensor performance. In this structure, an antiblooming potential barrier is provided that is smaller (in volts) than the barriers that separate the pixels from one another so that excess charge will flow preferentially into the LOD as opposed to the adjacent pixels.

Abstract: A method for manufacturing a light receiving portion for a solid state image pickup device includes the steps of forming a well of a second impurity type on a substrate of a first impurity type, forming a channel stop within an upper surface of the well, forming a vertical CCD portion within the upper surface of the well, forming a gate insulating layer on the upper surface of the well, channel stop and the vertical CCD portion, forming a charge carrying gate electrode above the vertical CCD portion, forming a light receiving photo diode by ion-implanting impurities of the first impurity type, forming a first impurity layer on the light receiving photo diode by ion-implanting impurities of the second impurity type into a surface of the light receiving photo diode, removing a portion of the gate insulating layer above the light receiving photo diode, depositing an insulating layer containing impurities of the first impurity type on the gate insulating layer, the charge carrying gate electrode and the first imp

Abstract: A solid state imaging device of the present invention includes a photoelectric convert part, a vertical charge transfer part, a horizontal charge transfer part, an unnecessary charge expelling region. A channel region of the horizontal charge transfer part and the unnecessary charge expelling region have an identical impurity profile. The channel region of the horizontal charge transfer part is applied to a first voltage to be depleted and the unnecessary charge expelling region is applied to a second voltage to be in non-depleted state.

Abstract: An active pixel sensor architecture comprising a semiconductor substrate having a plurality of pixels formed, thereon, incorporating microlens and lightshields into the pixel architecture. Each of the pixels further comprising: a photodetector region upon which incident light will form photoelectrons to be collected as a signal charge; a device for transferring the signal charge from the photodetector region to a charge storage region that is covered by a light shield; a sense node that is an input to an amplifier; the sense node being operatively connected to the signal storage region. The pixel architecture facilitates symmetrical design of pixels which allows for incorporation of light shield and microlens technology into the design.

Abstract: A monolithic three dimensional charged coupled device (3D-CCD) which utilizes the entire bulk of the semiconductor for charge generation, storage, and transfer. The 3D-CCD provides a vast improvement of current CCD architectures that use only the surface of the semiconductor substrate. The 3D-CCD is capable of developing a strong E-field throughout the depth of the semiconductor by using deep (buried) parallel (bulk) electrodes in the substrate material. Using backside illumination, the 3D-CCD architecture enables a single device to image photon energies from the visible, to the ultra-violet and soft x-ray, and out to higher energy x-rays of 30 keV and beyond. The buried or bulk electrodes are electrically connected to the surface electrodes, and an E-field parallel to the surface is established with the pixel in which the bulk electrodes are located. This E-field attracts charge to the bulk electrodes independent of depth and confines it within the pixel in which it is generated.

Abstract: It is an object of the present invention to provide a solid-state image sensing device with a vertical shutter structure allowing the size of the solid-state image sensing device with ease. An electric-charge exhausting unit is provided on the same side of a sensor array comprising a plurality of sensor units arranged to form a straight line as an electric-charge transferring unit wherein the electric-charge exhausting unit comprising an electric-charge exhaust drain having a shape resembling an island and an electric-charge exhausting gate with a bent shape surrounding the electric-charge exhaust drain is provided in such a way that the electric-charge exhausting unit is in contact with a first region of a read gate, and only one electric-charge exhausting unit is provided for each pair of sensor units adjacent to each other.

Abstract: In the solid-state image pickup device of the present invention, a two-layer structure of the second diffusion layer of the first conductive type and the third diffusion layer of the first conductive type that has a higher density is uniformly formed as an isolation area along a transfer channel between each photodiode string and each vertical CCD register. Therefore, a constant effective width for the transfer channel is provided and a preferable transfer efficiency is achieved. Further, the occurrence of a punch-through between the photodiode and the vertical CCD register can be prevented, isolation between the photodiode and the vertical CCD register can be ensured, and the reading of electric charges from the photodiode to the vertical CCD register can be performed at a lower voltage.

Abstract: A pixelated image sensor having comprising a partially pinned photodiode which is formed a semiconductor of a first conductivity type formed on a surface of the sensor with at least one photodiode formed, within the semiconductor near the surface, the photodiode being formed from a second conductivity type opposite the first conductivity type; a pinning layer formed on the surface over at least a portion of the photodiode creating a pinned photodiode region, the pinning layer being formed from the first conductivity type; and an unpinned region formed near the surface in an area outside the portion used to form the pinning layer, the unpinned region is formed as a floating region that is employed as a capacitor. The partially pinned photodiode is useful in expanding the fill factor of photodetectors employing photodiode technology.

Abstract: A solid-state imaging device of a vertical overflow drain system according to the present invention includes a first conductive type semiconductor substrate, a second conductive type semiconductor well region formed on the first conductive type semiconductor substrate, and a first conductive type, second conductive type or intrinsic high-resistance semiconductor region formed on the second conductive semiconductor well region and having a lower concentration as compared with the second conductive semiconductor well region and a width enough for infrared ray to be sufficiently absorbed. A light receiving portion is formed on a surface of the first conductive type, second conductive type or intrinsic high-resistance semiconductor region.

Abstract: In an active pixel sensor having a plurality of pixels, each of the pixels having a photodetector for accumulating charge from incident light, a transfer gate for removing charge from the photodetector, a floating diffusion that acts as a sense node to an amplifier input, and a drain the improvement comprising the provision of a reset mechanism for each pixel by application of a potential adjacent the floating diffusion such that the area between the floating diffusion and the drain becomes depleted.