Abstract: A semiconductor device and a method of inspecting the same are described. The semiconductor device does not need voltage adjustment of an external driver circuit, since it contains a voltage generator to inspect and memorize the best value of voltage by controlling from outside. The voltage generator has a plurality of capacitors whose electrodes of one side are connected to a common node, a potential changing circuit to change the potential to which the other electrodes of these capacitors are connected respectively, and a buffer amplifier whose input power is the voltage generated in the common node. The output power of the buffer amplifier is connected to a semiconductor integrated circuit. The potential changing circuit is provided to change the potential to which the electrode of each capacitor is connected to a source potential or to a ground potential depending on the connection of the fuse connected between the source and each of the capacitors.

Abstract: In charge-coupled imaging devices it is generally necessary to provide zones (12) in the matrix with a contact. These zones may form part, for example, of a mechanism for draining charge, for example as a protection against overexposure. In the case of imaging devices with a horizontal readout register on one side of the matrix, these contacts can be provided on the opposite side. However, it is often desirable or even necessary, as in the case of imaging devices with four-quadrant readout, to provide such contacts on the same side as the horizontal readout register. To this end, a dummy line (14'-17') is provided in accordance with the invention between the matrix and the horizontal readout register (6), said dummy line having an electrode structure which leaves room for contact windows (22) to the zones (12).

Abstract: A CCD pixel 10 has an antiblooming structure including a lateral overflow drain 36 of one conductivity. The drain 36 is mounted on one side by a heavy dope channel stop region. The rest of drain 36 is bounded by a heavily doped container region 38 that is formed in the same opening that is used to form LOD 36.

Abstract: A solid-stage imaging device has a region in which there is disposed an unwanted charge drain section 106 for receiving unwanted charges drained from vertical charge transfer sections 102 and a horizontal charge transfer section 103. A P-type well layer 302 is not disposed in the region, and a voltage is applied to an N.sup.-- -type semiconductor substrate 301 in a direction opposite to a voltage applied to the P-type well layer 302 for draining unwanted charges to the N.sup.-- -type semiconductor substrate 301. The unwanted charge drain section can be fabricated without an increase in the number of fabrication steps for manufacturing the solid-state imaging device.

Abstract: A solid-state image pick-up device 20 having a photoreceiving section 3 disposed on the obverse surface of a substrate 2 and performing photoelectric conversion. A readout gate 5 is disposed at one end of the photoreceiving section 3. A channel stop 8 is disposed at the other end of the photoreceiving section 3. A vertical transfer register 7 is provided for each of the readout gate 5 and the channel stop 8 at the end opposite to the photoreceiving section 3. A transfer electrode 10 is located in a position substantially right above the vertical transfer register 7. A light-shielding film 21 is disposed in such a manner that the transfer electrode 10 can be covered and that the portion right above the photoreceiving section 3 can be at least partially opened. The width W.sub.3 of the readout gate 5 is formed greater than the width W.sub.4 of the channel stop 8. The width W.sub.5 of the projecting portion 21b of the light-shielding film 21 adjacent to the readout gate 5 is formed smaller than the width W.sub.

Abstract: By introducing an n-type drain implant substantially below the surface of the p-type substrate of a full frame image sensor, then enclosing the drain on the bottom and the sides with a deep p-type implant, and accumulating the surface with a shallow p-type implant, with all implantations performed through the same mask aperture, the blooming control, channel stop, and dark current suppression features of the imager are compressed, increasing the fill factor, facilitating pixel miniaturization, and therefore enabling high resolution imaging applications.

Abstract: An amplifying type photoelectric converting device is disclosed. The device includes: a semiconductor substrate of a first conductive type; a well portion of a second conductive type for accumulating signal charges generated by photoelectric conversion; a semiconductor region of the first conductive type provided in a region in the well portion; a first gate region including a first electrode; and a second gate region being adjacent to the first gate region and including a second electrode. An active element is formed between the semiconductor region and the semiconductor substrate, and a change in an operational characteristic of the active element which is generated by the signal charges is used as an output signal.

Abstract: Disclosed is a solid state image device which has a plurality of photosensitive units which are disposed in parallel with each other and each of which includes a row of a plurality of photosensitive devices each of which includes a first N(or P)-type impurity region which is selectively formed on the surface of a P(or N)-type semiconductor region at the surface of a semiconductor substrate, a CCD register for executing electronic scanning which is disposed in parallel to the row of photosensitive devices, and a read-out gate in which a signal charge is transferred from the photosensitive device to the CCD register, wherein a transparent Schottky electrode is formed on the first N(or P)-type impurity region except a portion adjacent to the read-out gate region, the Schottky electrode is electrically connected to a P.sup.+ (or N.sup.

Abstract: A solid-state CCD image pick-up device includes optoelectric transducing elements corresponding to pixels vertically and horizontally arrayed in a matrix forming column linear arrays defining a column direction and at least one vertical charge transfer path associated with a corresponding adjacent column linear array. Pixel signals are vertically transferred from the column linear arrays to the vertical charge transfer paths such that gate signals occurring at predetermined times are applied to gate electrodes of the vertical charge transfer paths to permit the pixel signals to be scan read by a horizontal charge transfer path. Switching elements are provided for transfer gate electrodes and a drive circuit sequentially generates drive signals for groups of gate electrodes during periods in which the switching elements are rendered conductive to allow a full frame scan read to be performed by supplying a predetermined number of timing signals to the gate electrodes.

Abstract: It is an object of the present invention to provide a solid-state image sensing device with a vertical shutter structure allowing the size of the solid-state image sensing device with ease.An electric-charge exhausting unit is provided on the same side of a sensor array comprising a plurality of sensor units arranged to form a straight line as an electric-charge transferring unit wherein the electric-charge exhausting unit comprising an electric-charge exhaust drain having a shape resembling an island and an electric-charge exhausting gate with a bent shape surrounding the electric-charge exhaust drain is provided in such a way that the electric-charge exhausting unit is in contact with a first region of a read gate, and only one electric-charge exhausting unit is provided for each pair of sensor units adjacent to each other.

Abstract: A method and apparatus for reducing bloom in output of a charge coupled device (CCD) image sensor is disclosed. The method includes the step of toggling at least two phases of said CCD after exposure of said CCD. The method and apparatus are particularly useful when a flash of light occurs during the exposure.

Abstract: A linear solid state imaging device including a substrate (21), a first well (22) of a predetermined junction depth, a second well (23) of a deeper junction than the first well (22), a trapezoid type photodiode area (24) linearly arranged in the first well (22) in which except for one side of the parallel sides of the trapezoid area, the other sides are surrounded by a channel stop area (31), a pair of HCCD areas (25) in the second well in areas of both sides of the photodiode (24) and connected to the output amplifier, a shift gate (28) formed in the substrate between the areas for the photodiode (24) and the HCCD and for transferring the accumulated charges in the photodiode area to the HCCD area, a shift gate channel area (26) formed, in the first well underneath the shift gate (28) and having a six-sided shape one side of which is in contact with the photodiode area (24), another side of which has a V-shaped depression and the other sides are surrounded by a channel stop area (31), a potential barrier for

Abstract: The invention relates to a charge coupled device with a buried channel in which charge is detected by a MOST (MOS transistor) incorporated in the channel and having a surface channel of the conductivity type opposed to that of the charge coupled device. The source zone is situated in the centre of the CCD channel and is formed simultaneously with the channel bounding zone. The gate electrode comprises two portions situated on either side of the source zone, which portions, seen at the surface, do not overlap the source and drain zones. Below the gate electrode, a zone is formed of the same conductivity type as but with a higher doping than the CCD channel, which zone forms a charge storage region for the charge packet to be read out during the reading-out process. The source and drain zones are connected to the MOST channel region by means of extensions. The detector can be manufactured in a self-aligned manner, has a high charge storage capacity, a good noise behaviour, and a high speed.

Abstract: A charge-coupled device type solid state image pickup in which the overflow drain is formed at a high concentration on each photo-sensitive well. A high-concentration impurity layer is formed in the top layer of a PNPN structure to act as a drain against overflow. The structure enables overflow and electronic shutter operation even under low voltage conditions and may be realized on a chip.

Abstract: A self aligned, lateral-overflow drain antiblooming structure that is insensitive to drain bias voltages and therefore has improved insensitivity to process variations. The length of the antiblooming barrier regions are easily adjusted and determined by photolithography. The self aligned, lateral-overflow drain (LOD) antiblooming structure results in a design that saves space, and hence, improves overall sensor performance. In this structure, an antiblooming potential barrier is provided that is smaller (in volts) than the barriers that separate the pixels from one another so that excess charge will flow preferentially into the LOD as opposed to the adjacent pixels.

Abstract: The present invention is directed to providing a charge-coupled device which can provide accurate signal detection while providing high speed electronic exposure control or shuttering. Exemplary embodiments can maintain charge transfer efficiency at a relatively high level even if a pixel array of the charge-coupled device is clocked rapidly (i.e., exposure control or shuttering speed is increased) for a given pixel pitch.

Abstract: In a linear sensor, a charge transfer part is disposed between a one-dimensional array of photodetectors and an overflow drain and includes a CCD having four or more transfer gates for each photodetector for transferring signal charges from the photodetector array in a direction of the photodetector array, transfer gates controlling charge transfer from the photodetectors to the CCD, and shutter gates for controlling charge transfer from the charge transfer part to the overflow drain. Each transfer gate is disposed between each photodetector and a prescribed one of the four or more transfer gates, and each shutter gate is disposed between the prescribed transfer gate and the overflow drain. The four or more CCD transfer gates are controlled by four or more phase driving clocks.

Abstract: A device and a method for interrupting the continuity of a conductor and linking a pair of conductors are disclosed. The device is a three-terminal fuse having first and second terminals initially connected by a conductor and a third terminal separated from the conductor at a breakpoint of the conductor by an insulator. By applying a voltage across the third terminal or control terminal and the conductor, a transient conductive link is formed between the conductor and the control terminal. If sufficient current is provided through the transient link, heating of the link causes the metal of the conductor to melt and boil away, thus interrupting the continuity of the conductor.

Abstract: The process tracking bias generator for antiblooming structures includes a lateral overflow antiblooming drain and bias circuitry coupled to the antiblooming drain for automatically adjusting a bias for the antiblooming drain independent of process variations.

Abstract: A CCD solid state imaging device has an overflow mechanism to discharge excess electric charges at the sensor section. An overflow level can be stabilized without adjustment. The CCD solid state imaging device includes an overflow barrier region for determining an amount of electric charges handled by a sensor section, and an overflow drain region for discharging excess electric charges at the sensor section adjacent to the sensor section. An intermediate region having the same potential as that of the sensor portion is provided between the overflow barrier region and the overflow drain region. Also, a CCD solid state imaging device includes linear sensors provided in a plurality of lines and vertical transfer registers provided at end of the linear sensors in the charge transfer direction of the horizontal transfer registers. When signal charges are overflowed in a part of the horizontal transfer register, signals of all pixels can be avoided from being destroyed.

Abstract: The lateral overflow drain for virtual phase devices includes: a semiconductor region 72 of a first conductivity type; a drain region 24 of the first conductivity type formed in the semiconductor region 72; a threshold adjust region 22 formed in the semiconductor region 72 and surrounding the drain region 24; an electrode 20 overlying and connected to the drain region 24, the electrode 20 overlying and separated from at least a portion of the threshold adjust region 22; and virtual gates 30 and 32 of the second conductivity type in the semiconductor region 72 spaced apart from the drain region 24 and partially surrounding the drain region 24.

Abstract: It is known to reduce the leakage current or dark current in charge-coupled devices with buried channels such as, for example, charge-coupled imaging devices by bringing the surface to the inverted state. In such a device, however, it is not possible to empty the channel completely locally in usual manner in that the charge is drained off through the substrate by means of a voltage pulse applied to the gates (charge reset). To be able to carry out charge reset nevertheless, the voltage pulse is applied between the substrate and the intermediate zone interposed between the substrate and the CCD channel. Since this voltage pulse is active over the entire range of the device, the device also prevents charge from being removed in locations where this is not desired when the pulse is applied.

Abstract: A charge-transfer device contains a high-resistance p-well layer formed in the surface of an n-type semiconductor substrate. In the surface of the well layer, a charge-transfer n-channel layer, a charge storage n-channel layer, a charge release n-channel layer, and a charge release n-type drain are formed continuously. An output gate electrode is provided above the junction of the transfer channel layer and the storage channel layer, with an insulating film interposed therebetween. Provided above the release channel layer is a reset gate electrode with an insulating film interposed therebetween. In the surface of the storage channel layer, a charge-sensing p-channel layer of a charge-sensing transistor is formed. The charge-sensing channel layer is arranged so as to be in contact with neither the transfer channel layer nor the release channel layer.

Abstract: The present invention is directed toward an image sensor array comprising a plurality of pixels. Each pixel includes a photodiode and a CCD channel region. An overflow drain region is provided adjacent the CCD channel region for extraction of excess charges. An insulated gate read-out transfer electrode is further provided above the CCD channel region and a portion of the substrate between the CCD channel region and the photodiode. Three different potentials are applied to the read-out transfer electrode for respectively storing charge in the photodiode, extracting excess charge from the photodiode while allowing signal charge to remain in the photodiode, and reading out signal charge from the photodiode.

Abstract: A frame interline transfer CCD imager is so adapted that signal charges from the photosensor are read into a vertical transfer unit and are transferred at a high transfer rate from the vertical transfer unit to a storage section. The charges from each photosensor are drained during the high transfer rate transfer so that the photosensors are unable to store the signal charges to prevent the occurrence of blooming.

Abstract: A solid-state image sensing device includes a semiconductive substrate, an array of photosensitive cells on the substrate, and a transfer section electrically coupled with the array on the substrate, for transferring electrical carriers read from the cells along a predetermined direction. During an image sensing operation, a packet of charge carriers photoelectrically generated in the cells are prevented from continuously staying therein, by forcing the carriers to move into the transfer section, thus causing these carriers to be stored in the transfer section.

Abstract: A solid state imaging device of the present invention includes: a semiconductor substrate of one conductive type; a well layer made of a semiconductor of the other conductive type formed on the semiconductor substrate; a photodetecting portion made of a semiconductor of one conductive type formed in an upper portion of the well layer; a high concentration semiconductor layer made of the other conductive type formed in an upper portion of the photodetecting portion; a first region of one conductive type formed in an upper portion of the semiconductor substrate, being in contact with the well layer and positioned at least below the photodetecting portion, having higher concentration than the semiconductor substrate; and a second region of the other conductive type formed in a lower portion of the well layer, being in contact with the semiconductor substrate and positioned on the first region.

Abstract: An image sensing device with electronic shutter having a semiconductor substrate of a first conductivity type and a buried channel layer of a second conductivity type disposed on the substrate. Virtual phase electrodes in the buried channel layer having the first conductivity type form virtual gate potential areas in the substrate below the virtual phase electrodes. An insulating layer is formed on the substrate. Conductive electrodes disposed on the insulating layer and located over portions of the substrate between the virtual phase electrodes form clocked gate potential areas in the substrate below the conductive electrodes. The virtual gate potential areas and the clocked gate potential areas form charge transfer columns along which charge can be transferred to an end of the charge transfer column.

Abstract: There is provided a solid state imaging device having high-sensitivity, low-noise characteristics by reducing electrostatic capacity relating to interconnection. The solid state imaging device includes a photoelectric conversion section, a transfer section, a floating diffusion layer for receiving signal charges from the transfer section, and an output transistor having a gate electrode connected to the floating diffusion layer via an interconnection. A source and a drain of the output transistor are provided commonly within a flat p-type well of relatively thin concentration in which the photoelectric conversion section, the transfer section, and the floating diffusion layer are also provided.

Abstract: Solid-state image sensors, in general, comprise a photodetector for detecting radiation from the image and converting the radiation to charge carriers, and transfer means for carrying the charge carriers to an output circuit. One type of solid-state image sensor uses a CCD as both the photodetector and the transfer means. The solid-state image sensor generally includes a plurality of the CCD's arranged in spaced parallel relation to form an array. The image sensor of this disclosure utilizes only one antiblooming lateral overflow barrier. The excess signal charge of phase 1 flows into the preceding phase 2 and is saved. This eliminates the overflow barrier of phase 1 so that blooming protection is via the overflow barrier of the preceding phase 2. This results in an image sensor with blooming protection and increased charge capacity.

Abstract: A CCD image sensor comprising: a semiconductor substrate of a first conductivity type connected to a ground; an impurity region of a second conductivity type formed in the surface of the semiconductor substrate of the first conductivity type, to serve as a blooming prevention layer; an impurity region of the first conductivity type formed in the surface of the semiconductor substrate, so that it encloses the impurity region of the second conductivity type serving as a blooming prevention layer, to serve as a potential barrier layer; an impurity region of the second conductivity type formed in the surface of the semiconductor substrate of the first conductivity type so that it encloses the impurity region of the first conductivity type serving as a potential barrier layer, to serve as a light receiving region; an insulation film which is formed on the surface of the semiconductor substrate of the first conductivity type and has contact holes at both edges of the impurity region of the second conductivity type,

Abstract: The present invention is directed to a solid state imaging deice in which a light sensing region (3), a vertical register (4) and a channel stopper region (5) are formed within a well region (2) on an N-type silicon substrate (1). A positive electric charge storage region (6) is formed on the surface of the light sensing region (3) and a well region (7) is formed beneath the vertical register (4), respectively. Further, a transfer electrode (9) is selectively formed on the vertical register (4) through a gate insulating layer (8) and an Al light-intercepting layer (11) is formed on the transfer electrode (9) through an interlevel insulator (10). A surface protecting layer (12) is formed on the whole surface including the Al light-intercepting layer (11). In this solid state imaging device, a tapered portion (11a) is formed on the Al light-intercepting layer 11 corresponding to a peripheral edge portion of the light sensing region 3.

Abstract: A method and apparatus for reducing bloom in an output of a charge coupled device (CCD) image sensor is disclosed. The method includes the step of toggling at least two phases of said CCD after exposure of said CCD. The method and apparatus are particularly useful when a flash of light occurs during the exposure.

Abstract: The present invention relates to a charge coupled device CCD X-ray imager for reducing split events during integration. The imager includes a semiconductor material having a photosensitive region for receiving X-ray radiation energy and for generating electrical charges corresponding to the received X-ray radiation, and having a plurality of permanent barriers formed therein to divide the semiconductor material into a plurality of columns. Barrier electrodes are coupled to the semiconductor material for establishing in said semiconductor material a plurality of temporary barriers having a sufficient potential gradient to substantially reduce the occurrence of split events. Collection site electrodes are coupled to the semiconductor material for effecting the collection of the generated electrical charges. The temporary barriers are erected in the columns to form an array of potential wells.

Abstract: In a linear sensor, a charge transfer part is disposed between a one-dimensional array of photodetectors and an overflow drain and includes a CCD having four or more transfer gates for each photodetector for transferring signal charges from the photodetector array in a direction of the photodetector array, transfer gates controlling charge transfer from the photodetectors to the CCD, and shutter gates for controlling charge transfer from the charge transfer part to the overflow drain. Each transfer gate is disposed between each photodetector and a prescribed one of the four or more transfer gates, and each shutter gate is disposed between the prescribed transfer gate and the overflow drain. The four or more CCD transfer gates are controlled by four or more phase driving clocks.

Abstract: In CCD's, the major part of the dark current is caused by surface states. This dark current is disturbing, especially in image sensors, because the sensitivity of the camera is limited thereby. When according to the invention the integrating gates are varied periodically, the subjacent surface parts of the - buried - channel being brought periodically into inversion and into depletion, while maintaining the charge-containing capacity, a considerable reduction of the dark current can be obtained. In image sensors, voltage variation preferably occurs during the fly-back time.

Abstract: An image sensor having improved antiblooming characteristics includes a plurality of photodetectors in a substrate at a surface thereof and arranged in an array of columns and rows. A CCD shift register extends along each column of the photodetectors. A separate overflow drain is adjacent each photodetector and an overflow barrier extends between each photodetector and its adjacent drain. Each photodetector has an active region of one conductivity type which is divided into first and second portions. The first portion of the active region has a higher concentration of the impurities of the one conductivity type than the second portion so as to have a lower potential during operation thereof. Thus, the charge carriers generated in the first portion will flow into the second portion where they are stored. This reduces the capacitance of the photodetector to increase it antiblooming characteristics while maintaining the sensitivity of the photodetector.

Abstract: In a solid state image sensor, such as a CCD image sensor having lateral antiblooming protection, the level of which is controlled by an overflow gate voltage forming a barrier, the storage of electrons in the photodiode junction region of the sensor is eliminated by removing the barrier and allowing the charge to flow from the sensor's photodiode junctions into the overflow region. The charge flow is then detected as a function of the instantaneous light impinging on the photodiodes. The physical connections of the overflow gates are selected to form zones. Since the charge flow now represent the instantaneous light intensity, higher frequency components are detected than that limited by the sensor sampling rate. An amplifier is connected to sense the charge flow from each zone. With the range of light intensity being large the amplifier is provided with a logarithmic feed back element. This element provides compression of a signal representing the sensed charge flow.

Abstract: A virtual phase image sensor has majority carriers supplied to a virtual gate 24 by a conductor 32 overlying the image sensor, the virtual gate 24 and the conductor 32 each in contact with a conductive channel stop region 30.

Abstract: A solid state image sensing device has a plurality of photo sensing elements arranged in a two-dimensional fashion at pixel units pixel unit in the horizontal and vertical directions. Each of the plurality of photo sensing elements is formed of a vertical selection transistor whose gate electrode is connected to a horizontal selection line and whose source electrode is connected to a vertical signal line. A photoelectric conversion element is provided under a channel region of the vertical selection transistor. A high concentration impurity is buried in lower portions of the source electrode and the channel region. When a voltage is applied to the source electrode, a signal charge which is subjected to a photoelectric conversion by the photoelectric conversion element is reset. Reset noise, Vth irregularity, smear component and the surface dark current can be reduced and blooming is suppressed.

Abstract: A frame transfer image sensor having a lateral overflow drain and a structure for controlling the charge transfer to the drain during charge collection to improve exposure latitude.

Abstract: An exploiting or readout circuit for a linear or matrix type photodetector array is of the multiplex type, such as a charge-coupled device (CCD). The exploiting circuit has a number of input stages corresponding to the number of photodetectors or similar photosites, and the gains of the input stages are established as a function of the fields of view of their associated photodetectors. In one embodiment the input stages each comprise a storage device formed of a first and a second storage electrode separated by a dividing electrode, the storage electrodes having respective surface areas selected in a relation that varies as a function of solid angle field of view of the respective photodetector. In another embodiment the input stage can include an OpAmp with a negative feedback capacitor whose value is selected as a function of the viewing solid angle of the respective photodetector.

Abstract: The impurity density of a photoelectric transducer n-layer (7) and the impurity density of a p-layer (6) of an impurity region in which the electric transducer (7) and a transfer channel (9) are formed, are each distributed to have its maximum value in a more interior part from the surface of a semiconductor substrate (5). Alternatively, i) a thin, high-density p-layer (34) and ii) a thick, low-density p-layer (33) of an impurity region in which the electric transducer (7) and the transfer channel (9) are formed may be formed. Each minimum potential in these two p-layers (33, 34) is made to have a different dependence on the voltage applied to an n-type semiconductor substrate (5). The thick, low-density p-layer (33) is formed in such a way that it comes into contact with part of the photoelectric transducer n-layer (7) at its bottom portion.

Abstract: The present invention is directed to an image sensor which comprises a body of a semiconductor material having therein a plurality of photodetectors arranged in a line and a CCD shift register extending along the line of photodetectors adjacent to but spaced from an edge of the photodetectors. The CCD shift register includes a channel region and a plurality of first and second gate electrodes extending over and insulated from the channel region. One of each of the first and second gate electrodes extends across a portion of the edge of each photodetector. Each of the first electrodes has an arm extending along the entire edge of its respective photodetector between the photodetector and the second gate electrode. A separate transfer region is in the body between the edge of each photodetector and its respective first electrode and extends along the entire edge of the photodetector. A transfer gate is over and insulated from the transfer regions.

Abstract: A wide dynamic range photodetector comprising a photosensitive region for generating signal electrons in response to being illuminated, a collection region for storing the signal electrons generated within the photosensitive region, a shift register for receiving and outputing the signal electrons from the collection region, and a transfer gate intermediate the photosensitive region and the collection region for alternately facilitating transfer of the signal electrons from the photosensitive region for storage in the collection region, and isolating the photosensitive region from the collection region while the signal electrons are being output via the shift register.

Abstract: A one-dimensional time-delay integration solid-state imager includes a plurality of light-to-electricity conversion parts which store signal charges generated in response to incident light, a vertical CCD corresponding to a series of the light-to-electricity conversion parts for transferring stored signal charges, and a gate for controlling transfer of signal charges stored at the light-to-electricity conversion parts to the vertical CCD. The signal charges corresponding to the same observed image moving on the plurality of light-to-electricity conversion parts are added to enhance the signal-to-noise ratio, and a background signal charge removing region for removing background signal charges is provided at the vertical CCD for removing background charges during the transfer of signal charges.

Abstract: Described is a new high performance CCD image sensor technology which can be used to build a versatile image sensor family with the sensors that have high resolution and high pixel density. The described sensor architectures are based on a new charge super sweep concept which was developed to overcome such common problems as blooming and the image smear. The charge super sweep takes place in very narrow vertical channels located between the photosites similar to the Interline Transfer CCD devices. The difference here is that the charge is never stored in these regions for any significant length of time and is swept out using a new resistive gate traveling wave sweeping technique. The charge super sweep approach also allows the fast charge transfer of several lines of data from the photosites located anywhere in the array into the buffer storage during a single horizontal blanking interval.