Abstract: Provided is a display substrate, the display substrate is provided with a display area and a peripheral area around the display area, and includes: a source/drain layer, a planarization layer and an anode layer which are laminated in sequence, wherein in the peripheral area, the source/drain layer includes at least one pair of first signal lines including a signal line of a gate circuit and the anode layer includes a common power line provided with vent holes; and overlapping areas between two first signal lines in any pair of the first signal lines and a projection pattern of the vent hole are equal, the projection pattern of the vent hole being a pattern of an orthographic projection of the vent hole in the common power line onto the source/drain layer. A display panel and a display device are also provided.

Abstract: An integrated circuit (IC) includes a second metal level located between first and third metal levels, a dielectric layer located over the metal levels, and first, second and third vias within the dielectric layer. The first via traverses the first dielectric layer from a surface of the dielectric layer to the first metal level and has a first diameter. The second via traverses the dielectric layer from the surface to the second metal level and has the first diameter. The third via traverses the dielectric layer from the surface to the third metal level and has a second diameter greater than the first diameter. In some implementations the first, second and third metal levels implement a capacitor.

Abstract: Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device includes a semiconductor substrate. A gate dielectric is disposed over the semiconductor substrate. A first source/drain region and a second source/drain region are disposed in the semiconductor substrate and on opposite sides of the gate dielectric. A gate electrode is disposed over the gate dielectric. A first dishing prevention structure is embedded in the gate electrode, where a perimeter of the first dishing prevention structure is disposed within a perimeter of the gate electrode.

Abstract: An electronic device includes: a first insulation layer and a first conductive pillar. The first insulation layer has a first surface and a second surface opposite to the first surface, and the first conductive pillar comprises a first portion and a second portion. The first portion of the first conductive pillar is surrounded by the first insulation layer. The second portion of the first conductive pillar is disposed on the first surface of the first insulation layer. A height of the second portion of the first conductive pillar is equal to or greater than 10% of a height of the first portion of the conductive pillar.

Abstract: Some embodiments of the present disclosure are directed to an image sensor pixel that is configured for gateless reset of a floating diffusion. Some embodiments are directed to an image sensor comprising a plurality of pixels, at least one pixel comprising a floating diffusion formed in a semiconductor substrate; a transfer gate configured to selectively cause transfer of photocharge stored in the pixel to the floating diffusion; and a reset drain formed in the semiconductor substrate and spaced away from the floating diffusion by an intervening semiconductor region having a dopant type opposite to the dopant type of the reset drain and the floating diffusion, wherein the reset drain is configured to selectively reset the electrostatic potential of the floating diffusion in response to a voltage pulse applied to the reset drain.

Abstract: Vertical Group III-N devices and their methods of fabrication are described. In an example, a semiconductor structure includes a doped buffer layer above a substrate, and a group III-nitride (III-N) semiconductor material disposed on the doped buffer layer, the group III-N semiconductor material having a sloped sidewall and a planar uppermost surface. A drain region is disposed adjacent to the doped buffer layer. An insulator layer is disposed on the drain region. A polarization charge inducing layer is disposed on and conformal with the group III-N semiconductor material, the polarization charge inducing layer having a first portion disposed on the sloped sidewall of the group III-N semiconductor material and a second portion disposed on the planar uppermost surface of the group III-N semiconductor material. A gate structure is disposed on the first portion of the polarization charge inducing layer.

Abstract: An array substrate includes a first substrate, a thin film transistor disposed on the first substrate, a first electrode located on the first substrate, a protective layer located on the first electrode, and a second electrode located on the protective layer, wherein the protective layer includes a first layer and a second layer, the first layer has a first resistance value, the second layer has a second resistance value, the first layer is located between the first electrode and the second layer, and the second resistance value is less than the first resistance value.

Abstract: According to one embodiment, a semiconductor device includes first and second semiconductor layers, first, second, and third electrodes, and first and second insulating portions. The first semiconductor layer includes first, second, and third semiconductor regions. The second semiconductor layer includes first to sixth partial regions. The first electrode is electrically connected to the first partial region. The second electrode is electrically connected to the second partial region. A position of the third electrode is between positions of the first and second electrodes in a second direction. A first direction crosses the second direction from the first to second semiconductor regions. The first insulating portion is provided between the third semiconductor region and the third electrode and between the third partial region and the third electrode in the first direction. The fourth partial region is between the second insulating portion and the second semiconductor region in the first direction.

Abstract: An integrated circuit (IC) includes a substrate having a semiconductor surface layer, at least one capacitor above the semiconductor surface layer including a bottom plate, a capacitor dielectric over the bottom plate, and a top plate over the capacitor dielectric, functional circuitry in the semiconductor surface layer includes a core region having transistors configured together with the capacitor for realizing at least one circuit function. Electrically conductive metal filled contacts are through the dielectric layer that contact the top plate, the bottom plate, and the core region, including a first filled contact hole having a first depth and a first width that reach the top capacitor plate, and second filled contact hole having a second depth and a second width that reach the core region. The second depth is deeper than the first depth, and the first width is at least ten (10) % larger than the second width.

Abstract: A semiconductor structure includes a substrate, at least one first gate structure, at least one first spacer, at least one source drain structure, and a conductive plug. The first gate structure is present on the substrate. The first spacer is present on at least one sidewall of the first gate structure. The source drain structure is present adjacent to the first spacer. The conductive plug is electrically connected to the source drain structure while leaving a gap between the conductive plug and the spacer.

Abstract: The present invention provides a TFT that has a channel length particularly longer than that of an existing one, specifically, several tens to several hundreds times longer than that of the existing one, and thereby allowing turning to an on-state at a gate voltage particularly higher than the existing one and driving, and allowing having a low channel conductance gd. According to the present invention, not only the simple dispersion of on-current but also the normalized dispersion thereof can be reduced, and other than the reduction of the dispersion between the individual TFTs, the dispersion of the OLEDs themselves and the dispersion due to the deterioration of the OLED can be reduced.

Abstract: A capacitor structure may include a lower conducting layer (e.g., poly 1 layer) and an upper conducting layer (e.g., overlying poly 2 layer), which define an anode and cathode, and a dielectric layer (e.g., an ONO layer stack) located between the upper conducting layer and the lower conducting layer, wherein a portion of the dielectric layer (e.g., at least the nitride layer of the ONO layer stack) extends beyond a lateral edge of the upper conducting layer. A method forming such capacitor structure may utilize a spacer adjacent the lateral edge of the upper conducting layer and over the first portion of the dielectric layer, performing an etch to remove a first portion of the dielectric layer but protect a second portion located below the spacer and extending laterally beyond an edge of the upper conducting layer.

Abstract: A radio frequency (RF) chip capacitor circuit and structure are provided. The circuit and structure include a plurality of capacitors connected in series. Each capacitor of the plurality includes a first plate formed from a first metal layer and a second plate formed from a second metal layer. A first two adjacent capacitors of the plurality include first plates formed in a first contiguous portion of the first metal layer or second plates formed in a second contiguous portion of the second metal layer. Each capacitor of the plurality may include a dielectric layer disposed between the first plate and the second plate.

Abstract: The present description relates to n-channel gallium nitride transistors which include a recessed gate electrode, wherein the polarization layer between the gate electrode and the gallium nitride layer is less than about 1 nm. In additional embodiments, the n-channel gallium nitride transistors may have an asymmetric configuration, wherein a gate-to drain length is greater than a gate-to-source length. In further embodiment, the n-channel gallium nitride transistors may be utilized in wireless power/charging devices for improved efficiencies, longer transmission distances, and smaller form factors, when compared with wireless power/charging devices using silicon-based transistors.

Abstract: An anisotropic electrically conductive film has a structure wherein the electrically conductive particles are disposed on or near the surface of an electrically insulating adhesive base layer, or a structure wherein an electrically insulating adhesive base layer and an electrically insulating adhesive cover layer are laminated together and the electrically conductive particles are disposed near the interface therebetween. Electrically conductive particle groups configured from two or more electrically conductive particles are disposed in a lattice point region of a planar lattice pattern. A preferred lattice point region is a circle centered on a lattice point. A radius of the circle is not less than two times and not more than seven times the average particle diameter of the electrically conductive particles.

Abstract: A high electron mobility transistor (HEMT) device with a highly resistive layer co-doped with carbon (C) and a donor-type impurity and a method for making the HEMT device is disclosed. In one embodiment, the HEMT device includes a substrate, the highly resistive layer co-doped with C and the donor-type impurity formed above the substrate, a channel layer formed above the highly resistive layer, and a barrier layer formed above the channel layer. In one embodiment, the highly resistive layer comprises gallium nitride (GaN). In one embodiment, the donor-type impurity is silicon (Si). In another embodiment, the donor-type impurity is oxygen (O).

Abstract: A semiconductor device includes a wire pattern spaced apart from a substrate and extended in a first direction, a gate electrode disposed around a circumference of the wire pattern and extended in a second direction that is different from the first direction, a source disposed on a first side of the gate electrode, a drain disposed on a second side of the gate electrode, the source and the drain connected to the wire pattern and a gate spacer disposed on first and second sidewalls of the gate electrode, on the source and on the drain.

Abstract: Embodiments of the invention provide a semiconductor fabrication method and a structure for strained transistors. A method comprises forming a stressor layer over a MOS transistor. The stressor layer is selectively etched over the gate electrode, thereby affecting strain conditions within the MOSFET channel region. An NMOS transistor may have a tensile stressor layer, and a PMOS transistor may have compressive stressor layer.

Abstract: The ultraviolet sensor device comprises a semiconductor substrate, a dielectric layer above the substrate, a surface of the dielectric layer that is provided for the incidence of ultraviolet radiation, a floating gate electrode in the dielectric layer and an electrically conductive control gate electrode near the floating gate electrode. The control gate electrode is insulated from the floating gate electrode. A sensor layer is formed by an electrically conductive further layer that is electrically conductively connected to the floating gate electrode. The control gate electrode is arranged outside a region that is located between the sensor layer and the surface provided for the incidence of ultraviolet radiation. The sensor layer is discharged by incident UV radiation and can be charged or discharged electrically by charging or discharging the floating gate electrode.

Abstract: An electronic circuit includes a transistor arrangement with a plurality of transistor devices, each including a control node and a load path between a first load node and a second load node, and having the load paths connected in parallel. The electronic circuit further includes a drive circuit coupled to the control node of each of the plurality of transistor devices, and configured to receive an input signal. Each of the plurality of transistor devices includes a two-dimensional electron gas (2DEG) in the load path, and a field plate adjacent the 2DEG. The drive circuit is configured to receive a load signal that represents at least one load parameter of the transistor arrangement and is configured to one of activate and deactivate at least one of the plurality of transistor devices based on the load signal.

Abstract: Disclosed are test structures and methods for non-planar field effect transistors. The test structures comprise test device(s) on an insulator layer. Each device comprises semiconductor fin(s). Each fin has a first portion comprising a pseudo channel region at one end and a second portion comprising a diffusion region positioned laterally adjacent to the first portion. A gate with sidewall spacers can be adjacent to the first portion of the fin(s). A first contact can be on the insulator layer adjacent the end of the fin(s). A second contact can be on the second portion of the fin(s) such that the gate is positioned laterally between the contacts. Measurements taken when the first contact is biased against the gate are compared to measurements taken when the second contact is biased against the gate in order to assess lateral dielectric breakdown between the gate and first contact independent of gate dielectric breakdown.

Abstract: In a method, a dummy gate layer structure and a mask layer are formed on a substrate. The mask layer is patterned to form masks. Spacers are formed on sidewalls of the mask. A dummy gate mask is formed between the spacers. The dummy gate layer structure is patterned using the dummy gate mask to form dummy gate structures. The dummy gate structure is replaced with a gate structure. When the mask is formed, an initial layout of masks extending in a first direction is designed. An offset bias in a second direction is provided for a specific region of the initial layout to design a final layout having a width in the second direction varying along the first direction. The mask layer is patterned according to the final layout to form the masks having a width varying along the first direction.

Abstract: A range image sensor capable of improving its aperture ratio and yielding a range image with a favorable S/N ratio is provided. A range image sensor RS has an imaging region constituted by a plurality of one-dimensionally arranged units on a semiconductor substrate 1 and yields a range image according to a charge amount issued from the units.

Abstract: Disclosed is a semiconductor structure incorporating a contact sidewall spacer with a self-aligned airgap and a method of forming the semiconductor structure. The structure comprises a semiconductor device (e.g., a two-terminal device, such as a PN junction diode or Schottky diode, or a three-terminal device, such as a field effect transistor (FET), a bipolar junction transistor (BJT), etc.) and a dielectric layer that covers the semiconductor device. A contact extends vertically through the dielectric layer to a terminal of the semiconductor device (e.g., in the case of a FET, to a source/drain region of the FET). A contact sidewall spacer is positioned on the contact sidewall and incorporates an airgap. Since air has a lower dielectric constant than other typically used dielectric spacer or interlayer dielectric materials, the contact size can be increased for reduced parasitic resistance while minimizing corresponding increases in parasitic capacitance or the probability of shorts.

Abstract: A transistor includes a substrate, an electrically conductive material layer, and an electrically insulating material layer. At least a portion of one or more of the substrate, the electrically conductive material layer, and the electrically insulating material layer define a reentrant profile.

Abstract: A semiconductor device containing an extended drain MOS transistor with an integrated snubber formed by forming a drain drift region of the MOS transistor, forming a snubber capacitor including a capacitor dielectric layer and capacitor plate over the extended drain, and forming a snubber resistor over a gate of the MOS transistor so that the resistor is connected in series between the capacitor plate and a source of the MOS transistor.

Abstract: It is an object to provide a photoelectric conversion device with high photoelectric conversion efficiency. The photoelectric conversion device includes an electrode layer, and a light absorbing layer located on the electrode layer. The light absorbing layer is comprised of a plurality of stacked semiconductor layers containing a chalcopyrite-based compound semiconductor. The semiconductor layers contain oxygen. A molar concentration of the oxygen in surfaces and their vicinities of the semiconductor layers where the semiconductor layers are stacked on each other is higher than average molar concentrations of the oxygen in the semiconductor layers.

Abstract: Provided is a semiconductor device in which on-resistance is largely reduced. In a region (2a) of an N type epitaxial layer (2) of the semiconductor device 20, each region between neighboring trenches (3) is blocked with a depletion layer (14) formed around a trench (3) so that a current passage (12) is interrupted, while a part of the depletion layer (14) formed around the trench (3) is deleted so that the current passage (12) is opened. In a region (2b), a junction portion (8) between the N type epitaxial layer (2) and a P+ type diffusion region (7) makes a Zener diode (8).

Abstract: A millimeter-wave transistor device includes a plurality of sub-cells arranged in matrix array, each of the sub-cells having a longitudinal gate finger elongating along a reference y-axis, a source doping region disposed at one side of the longitudinal gate finger and a drain doping region at the other side of the longitudinal gate finger opposite to the source doping region; and at least three parallel connecting bars extending along a reference x-axis, electrically connecting with respective distal ends of the longitudinal gate finger of each of the sub-cells.

Abstract: A semiconductor device includes a semiconductor substrate, a source and a drain region formed on the semiconductor substrate, and a gate structure disposed on the substrate between the source and drain regions. The gate structure includes an interfacial layer formed over the substrate, a high-k dielectric formed over the interfacial layer, and a metal gate formed over the high-k dielectric that includes a first metal layer and a second metal layer, where the first metal layer is formed on a portion of the sidewalls of the gate structure and where the second metal layer is formed on another portion of the sidewalls of the gate structure.

Abstract: A field effect transistor (FET) having a source, a drain and a gate includes a first connection electrically connected to the gate near a first end of the gate, a second connection electrically connected to the gate near the first end of the gate, a third connection electrically connected to the gate near a second end of the gate, and a fourth connection electrically connected to the gate near the second end of the gate. By performing gate resistance measurements at different ambient temperatures, a thermal coefficient of gate resistance can be derived and then used to monitor the gate temperature, which is representative of the channel temperature.

Abstract: A device for storing embedded charge includes a first insulator and at least one second insulator. The first insulator has at least two outer surfaces and has a band gap of less than about 5.5 eV. The second insulator is deposited on at least each of the at least two outer surfaces of the first insulator to form at least one interface for storing charge between the first and second insulators. The second insulator has a band gap of more than about 6.0 eV.

Abstract: A semiconductor device includes: a substrate; a transistor that has a ring-shaped gate electrode formed on the substrate; a plurality of external dummy electrodes that are arranged outside the gate electrode and are formed in the same layer as the gate electrode; and at least one internal dummy electrode that is arranged inside the gate electrode and is formed in the same layer as the gate electrode.

Abstract: A semiconductor device includes a first field effect transistor (FET) located on a substrate; and a second FET located on the substrate, the second FET comprising a first buried oxide (BOX) region located underneath a channel region of the second FET, wherein the first BOX region of the second FET is configured to cause the second FET to have a higher radiation sensitivity that the first FET.

Abstract: A structure and method of fabricating the structure. The structure includes a first region of a semiconductor substrate separated from a second region of the semiconductor substrate by trench isolation formed in the substrate; a first stressed layer over the first region; a second stressed layer over second region; the first stressed layer and second stressed layer separated by a gap; and a passivation layer on the first and second stressed layers, the passivation layer extending over and sealing the gap.

Abstract: A nitride-based semiconductor light emitting device with improved characteristics of ohmic contact to an n-electrode and a method of fabricating the same are provided. The nitride-based semiconductor light emitting device includes an n-electrode, a p-electrode, an n-type compound semiconductor layer, and an active layer and a p-type compound semiconductor layer formed between the n- and p-electrodes. The n-electrode includes: a first electrode layer formed of at least one element selected from the group consisting of Pd, Pt, Ni, Co, Rh, Ir, Fe, Ru, Os, Cu, Ag, and Au; and a second electrode layer formed on the first electrode layer using a conductive material containing at least one element selected from the group consisting of Ti, V, Cr, Zr, Nb, Hf, Ta, Mo, W, Re, Ir, Al, In, Pb, Ni, Rh, Ru, Os, and Au.

Abstract: An electric fuse includes: a first interconnect and a second interconnect, formed on a semiconductor substrate; a fuse link, formed on the semiconductor substrate and provided so that an end thereof is coupled to the first interconnect, the fuse link being capable of electrically cutting the second interconnect from the first interconnect; and an electric current inflow terminal and an electric current drain terminal for cutting the fuse link, formed on the semiconductor substrate and provided in one end and another end of the first interconnect, respectively.

Abstract: Non-volatile memory (NVM) devices are disclosed. In one aspect, a NVM device may include a substrate, and a field-effect transistor (FET). The FET may include a first doped region in the substrate and a second doped region in the substrate. The first and the second doped regions may define a channel region of the substrate between them. An insulating layer may overlie the channel region. A floating gate may overlie the insulating layer. Charge of an amount that encodes a value may be stored on the floating gate. The floating gate and the first and the second doped regions may be shaped such that the floating gate defines with the first doped region a first border of a first length, and the floating gate defines with the second doped region a second border of a second length that is less than 90% of the first length.

Abstract: Atomic layer deposition is enhanced using plasma. Plasma begins prior to flowing a second precursor into a chamber. The second precursor reacts with a first precursor to deposit a layer on a substrate. The layer may include at least one element from each of the first and second precursors. The layer may be TaN, and the precursors may be TaF5 and NH3. The plasma may begin during purge gas flow between a pulse of the first precursor and a pulse of the second precursor. Thermal energy assists the reaction of the precursors to deposit the layer on the substrate. The thermal energy may be greater than generally accepted for ALD (e.g., more than 300 degrees Celsius).

Abstract: A logic switch intentionally utilizes GIDL current as its primary mechanism of operation. Voltages may be applied to a doped gate overlying and insulated from a pn junction. A first voltage initiates GIDL current, and the logic switch is bidirectionally conductive. A second voltage terminates GIDL current, but the logic switch is unidirectionally conductive. A third voltage renders the logic switch bidirectionally non-conductive. Circuits containing the logic switch are also described. These circuits include inverters, SRAM cells, voltage reference sources, and neuron logic switches. The logic switch is primarily implemented according to SOI protocols, but embodiments according to bulk protocols are described.

Abstract: A semiconductor device including: a semiconductor layer; a gate insulating layer; a gate electrode; a channel region; a source region and a drain region; a guard ring region; an offset insulating layer; a first interlayer dielectric; a first shield layer formed above the first interlayer dielectric and the guard ring region and electrically connected to the guard ring region; a second interlayer dielectric; and a second shield layer formed above the second interlayer dielectric, wherein the first shield layer is provided outside of both ends of the gate electrode in a channel width direction when viewed from the top side; and wherein the second shield layer is provided in at least part of a first region and/or at least part of a second region, the first region being a region between one edge of the gate electrode and an edge of the first shield layer opposite to the edge of the gate electrode in the channel width direction when viewed from the top side, and the second region being a region between the other e

Abstract: An electrode structure including two parallel electrical paths. A plurality of electrode layers, generally tabular in form is formed in a stack, the outermost layers providing electrical contacts, and defining a first electrical current path through the stack. Two sidewall conductor layers are formed to abut either end of the electrode layer stack, two sidewall conductor layers defining a second electrical current path. The ends of the sidewall conduction layers lie in the same planes as the electrode layer electrical contacts, such that electrode structure electrical contacts are each formed from one set of sidewall layer ends and an electrode layer electrical contact.

Abstract: Devices and methods for forming self-aligned charge storage regions are disclosed. In one embodiment, a method for manufacturing a semiconductor device comprises forming a layer of a nitride film stacked between two oxide films on a semiconductor substrate, and forming a gate electrode on the layer of the nitride film stacked between the two oxide films. In addition, the method comprises removing side portions of the nitride film such that a central portion of the nitride film below a center portion of the gate electrode remains, oxidizing the central portion of the nitride film, and forming charge storage layers in the side portions of the nitride film, where the charge storage layers are separated by the central portion of the nitride film.

Abstract: A metallization on a semiconductor substrate is disclosed in the form of a laminate comprising a plurality of layers of a “conducting” metallization for providing electrical conductivity, interspersed with a plurality of layers of another metallization. By providing many layers the thickness of each individual layer can be reduced. Reduction in thickness of each layer leads to a reduction in grain size and a consequent reduction in creep over the lifetime of a device.

Abstract: Disclosed are a semiconductor device with a metal gate and a method of manufacturing the same.

Abstract: A pixel structure having capacitor compensation includes a thin-film transistor, and the thin-film transistor includes a source electrode, a drain electrode, a semiconductor layer and a gate electrode. The gate electrode includes a bar-shaped main part, and at least a protrusion part or two indention parts. One of the characteristics of the present invention lies in layout patterns of the drain electrode and gate electrode. An overlapping area between the drain electrode and gate electrode, and the position of the overlapping area can both be kept by virtue of the arrangement of the protrusion part or the indention parts of the gate electrode, even when the alignment between the drain electrode and gate electrode is changed. Therefore, the gate-drain capacitor (Cgd) will not be changed so that the quality of the liquid crystal display will be improved accordingly.

Abstract: A semiconductor device and a method of manufacturing the same are provided. A multi-component high-k interface layer containing elements of the substrate is formed from a ultra-thin high-k dielectric material in a single-layer structure of atoms by rapid annealing in the manufacturing of a CMOS transistor by the replacement gate process, and a high-k gate dielectric layer with a higher dielectric constant and a metal gate layer are formed thereon. The EOT of the device is effectively decreased, and the diffusion of atoms in the high-k gate dielectric layer from an upper level thereof is effectively prevented by the optimized high-k interface layer at high-temperature treatment. Thus, the present invention may also avoid the growth of the interface layers and the degradation of carrier mobility.

Abstract: A semiconductor module having a current connection element designed for a high current carrying capability is disclosed. In one embodiment, the current connection element includes a plurality of metal layers which rest directly on one another.

Abstract: Disclosed herein is a field effect transistor (FET), device including a FET, and a method of making the same. In embodiments of the disclosure, a semiconductor-on-insulator (SOI) substrate is provided. The SOI substrate includes a body having a first conductivity type formed in the semiconductor layer of the SOI substrate, the body including a first body region connecting a second body region to a third body region; and a source and a drain, each having a second conductivity type, disposed on opposite sides of the first body region. A first gate electrode having a second work function is disposed above the first body region; and a second gate electrode having a first work function disposed above the second and third body regions. A first gate dielectric layer may be disposed vertically between the first body region and the first gate electrode, and a second gate dielectric layer may be disposed vertically between the second and third body regions and the second gate electrode.

Abstract: Provided is a semiconductor device in which on-resistance is largely reduced. In a region (2a) of an N type epitaxial layer (2) of the semiconductor device 20, each region between neighboring trenches (3) is blocked with a depletion layer (14) formed around a trench (3) so that a current passage (12) is interrupted, while a part of the depletion layer (14) formed around the trench (3) is deleted so that the current passage (12) is opened. In a region (2b), a junction portion (8) between the N type epitaxial layer (2) and a P+ type diffusion region (7) makes a Zener diode (8).

Abstract: Oligomers of polyarylene polyethethers (PAPE) having a mol wt Mn in the range from 1000 to about 10,000 are converted to monofunctionalized macromers, so as, in the first instance, to provide a reactive double bond (for example, a vinylbenzyl group) at only one end of the PAPE; and, in the second instance, to provide a triple bond (benzylethynyl group) at only one end of the PAPE. The macromer may be a polysulfone, a polyketone, or a copolymer containing both sulfone and ketone-containing units; or, the macromer may be monofunctionalized PPO. The synthesis of macromers with terminal double bonds is carried out with a fast and quantitative modified Williamson etherification of the PAPE with an electrophilic haloalkyl reactant ("HAR") such as chloromethylstyrene ("C1MS") in the presence of a major molar amount (more than 50 mol % based on the number of moles of OH group originally present in the oligomer) of a phase transfer catalyst such as tetrabutylammonium hydrogen sulfate ("TBAH").