Abstract: A plurality of first basic cells and a plurality of second basic cells are formed on a semiconductor substrate. A gate electrode of each of transistors in the first basic cell has a gate length of the minimum size. A gate electrode of each of transistors in the second basic cell has a second gate length larger than the first gate length. The transistors in the first basic cell are connected to each other, to construct a circuit which is operable at high speed and can be increased in integration density. The transistors in the second basic cell are connected to each other, to construct a circuit which can be reduced in power consumption and is hardly affected by process variations.

Abstract: There is disclosed a charge transfer apparatus in which with respect to a signal charge detector, a gate insulation film under an output electrode and a reset electrode is formed of one layer of a silicon oxide film. As a result, even when the device is charged up during a manufacture process, the charge injection to the gate insulation film under the output electrode and reset electrode can be prevented. Therefore, the threshold value dispersion of the output electrode or the reset electrode is suppressed, and the charge transfer apparatus with uniform characteristics can be provided. Furthermore, by forming the silicon oxide film under the output electrode and reset electrode to be thick, the capacity formed of a floating diffusion layer and the parasitic capacity of the output electrode, and the capacity formed of the floating diffusion layer and the parasitic capacity of the reset electrode are reduced.

Abstract: A solid imaging device having a high sensitivity includes a photoelectric conversion region, a light shielding film having an aperture disposed above the photoelectric conversion region, and a plurality of wiring layers and wherein a portion of one wiring layer protrudes from the edge of the aperture, when viewed from the top of the aperture, so as to shield the light incident to the peripheral area of the photoelectric conversion region for defining the light admitting region.

Abstract: A CCD solid-state image sensing device has power supply lines formed from a poly-silicon layer and a silicide layer formed on the poly-silicon layer. The silicide layer has a reduced optical reflectivity that inhibits reflections of light on a surface of the power supply line. The silicide layer is silicon combined with a refractory metal, such as tungsten, molybdenum, titanium, or the like. Further, a surface protective film is formed on the power supply lines. The surface protective film includes silicon nitride having an increased quantity of hydrogen that is supplied to an interface between a channel layer and a diffusion layer in order to promote bonding.

Abstract: A process for producing a semiconductor device comprises a step of polishing of a region of an electroconductive material serving as an electrode or a wiring line in an insulating layer formed on a semiconductor region, the region of the electroconductive material being electrically connected to the semiconductor region, wherein a region of another material is formed within the region of the electroconductive material to be polished. Also a semiconductor device having the region is provided. A process for producing an active matrix substrate comprises a step of polishing of picture element electrodes made of a metal provided on crossing portions of plural signal lines and plural scanning lines and a means for applying voltage to the picture elements, wherein a region of another material is formed within the region of the picture element electrode to be polished. An active matrix substrate has such picture element electrodes as mentioned above.

Abstract: In a charge coupled device, trap levels formed by insulating layers or floating electrodes are formed on a semiconductor layer or a semiconductor substrate. Stationary charges are trapped in some of the trap levels or floating electrodes. The charge transfer electrodes are in self-alignment with potential barrier regions.

Abstract: A manufacturing process OF a thin film transistor is provided, in which occurrence of a dry spot and occurrence of an etch residue of an ohmic contact layer (n+ a-Si:H film) due to the dry spot are prevented in photoengraving process for patterning a semiconductor layer and the ohmic contact layer into an island, without any further treatment by any other apparatus. After forming the a-Si:H film 4a which forms the semiconductor layer of the TFT and the n+ a-Si:H film 5a which forms the ohmic contact layer, a N2 gas plasma discharge is continuously performed using the same plasma CVD apparatus, thereby forming a very thin silicon nitride film 6 having a hydrophilic property on a surface layer of the n+ a-Si:H film 5a.

Abstract: A MOSFET has a buried shield plate under the gate and over the drain with the gate being formed on the periphery of the buried shield plate as a self-aligned structure with minimal or no overlap of the gate over the shield plate. Methods of fabricating the MOSFET are disclosed.

Abstract: In a CCD type solid state image pickup device including a semiconductor substrate having photo/electro conversion portions and a first insulating layer formed on the semiconductor substrate, a plurality of charge transfer electrodes are formed on the first insulating layer and are a double structure formed by a first conductive layer and a second conductive layer having a lower resistance value than the first conductive layer. A second insulating layer is interposed between two adjacent ones of the charge transfer electrodes.

Abstract: A capacitor structure (100) including first and second capacitor plates (102, 106) insulatingly spaced from each other by a capacitor dielectric (102). A first set of conductive posts (301) electrically couple to the first capacitor plate (102) and extend away from the capacitor dielectric (104). A first conductive structure (302) comprising a material with lower resistivity than the first capacitor plate (102) is electrically coupled to the first set of conductive posts (301). In a preferred embodiment, a second set of conductive posts (501) are electrically coupled to the second capacitor plate (106) and extend away from the capacitor dielectric (102). A second conductive structure (503) is electrically coupled to the second set of conductive posts (501).

Abstract: In one aspect, the invention provides a method of forming an integrated circuitry memory device. In one preferred implementation, a conductive layer is formed over both memory array areas and peripheral circuitry areas. A refractory metal layer is formed over the conductive layer to provide conductive structure in both areas. According to a preferred aspect of this implementation, the conductive layer which is formed over the memory array provides an electrical contact for a capacitor container to be formed. According to another preferred aspect of this implementation, the conductive layer formed over the peripheral circuitry area constitutes a conductive line which includes at least some of the silicide. In another preferred implementation, the invention provides a method of forming a capacitor container over a substrate. According to a preferred aspect of this implementation, a conductive layer is elevationally interposed between an upper insulating layer and a lower conductive layer over the substrate.

Abstract: A method of forming a field effect transistor relative to a semiconductor substrate, where the transistor has a gate which defines a resultant lateral expense of semiconductive material therebeneath for provision of a transistor channel region, includes a) providing a conductive gate layer over a semiconductor substrate; b) patterning the conductive gate layer into a first gate block, the first gate block having a first lateral expanse which is greater than the resultant lateral expanse; c) providing an insulating dielectric layer over the first gate block; d) providing a patterned layer of photoresist over the first gate block and the insulating dielectric layer, the patterned photoresist comprising a photoresist block positioned over and within the first lateral expanse of the first gate block; e) with the patterned photoresist in place, etching the insulating dielectric layer selectively relative to the first gate block; f) after etching the insulating dielectric layer and with the patterned photoresist in

Abstract: The solid state imaging device of the present invention comprises a light-shielding layer 13 provided with an opening in a photodiode portion and formed through a ground adhesion layer made of one of titanium nitride and titanium on the substrate 1.

Abstract: A solid state image sensor includes a photodiode, a vertical charge coupled device positioned to a side of the photodiode for transmitting charges generated in the photodiode, a first polygate extending in a horizontal direction and partly overlapping the vertical charge coupled device, and a second polygate extending in a horizontal direction, partly overlapping the vertical charge coupled device and having a second polygate extension, wherein the second polygate extension extends for substantially an entire length of the side of the photodiode.

Abstract: An improved split gate flash memory cell is disclosed whose floating gate is formed to have a reentrant angle such that its width increases with increased distance from the substrate so as to minimize the possibility of defects in the poly oxide layer overlaying the floating gate. The split gate flash memory is fabricated using a process comprising the steps of: (a) forming a floating gate with an overlaying poly oxide layer on a substrate, wherein the floating gate is etched to have a reentrant angle such that its width generally increases with a distance from the substrate; (b) forming a CVD nitride spacer on the floating gate using a CVD nitride deposition, then anisotropic etching the CVD nitride to form a nitride spacer adjacent to the floating gate; (c) forming a control gate on the floating gate wherein the control gate and the floating gate are separated by the poly oxide and the nitride spacer; and (d) forming a source and drain in the substrate using a source and drain implantation.

Abstract: A dipping in potential well due to direct contact between transfer electrodes and metal wiring causes a drop in transfer efficiency through a CCD register. In order to eliminate or at least reduce the potential dipping, an N.sup.- -type impurity layer that functions as a CCD channel is formed with N.sup.-- -type impurity regions that have impurity concentration lower than that of the N.sup.- -type impurity layer. The N.sup.- -type impurity regions are located below transfer electrodes in alignment with contact apertures.

Abstract: A solid state image pick-up device is disclosed in which potential wells formed between adjacent ones of charge transfer electrodes of a vertical charge transfer portion thereof, formed between adjacent ones of charge transfer electrodes of a horizontal charge transfer portion and formed in a connecting region between the vertical and horizontal charge transfer portions are uniformalized. Impurity densities of regions between the charge transfer electrodes of the vertical charge transfer portion thereof, between the charge transfer electrodes of the horizontal charge transfer portion and in a connecting region between the vertical and horizontal charge transfer portions are set independently from each other on the basis of the inter-electrode distances and amplitudes and potentials of driving pulses supplied these electrodes such that these potential wells become equal to each other.

Abstract: An electronic device includes one or more semiconductor chips interconnected to a next level substrate in a flip chip mode using flexible conductive adhesive having a low modulus of elasticity. The flexible conductive adhesive is applied as conductive bumps on the contact pads of the substrate or on the contact pads of the semiconductor chips and is a flexible thermoplastic or thermosetting resin filled with electrically-conductive particles. Other electronic devices, such as packaged components including resistors, capacitors and the like, are bonded with the same flexible conductive adhesive bump approach as is employed for the semiconductor chips. The contact pads of both the chip and the next level substrate are preferably passivated with a metallic coating, preferably a precious metal, prior to interconnection to inhibit oxidation of the pads.

Abstract: A solid-state image sensor and a fabricating method thereof in which poly gates in a horizontal charge coupled device (hereinafter referred to as HCCD) are made to have different lengths to omit a barrier ion implanting process step, thus simplifying the entire process and maximizing the charge-transferring efficiency are disclosed, the solid-state image sensor having an HCCD and VCCDs including a well region of a second conductivity type formed in a semiconductor substrate of a first conductivity type; a HCCD of the first conductivity type formed on the well region of the second conductivity type; and a plurality of polygate electrodes having sequentially different lengths repeatedly formed on the semiconductor substrate.

Abstract: The invention relates to a charge-coupled device. Such devices comprise at least one insulated conducting gate (3) connecting two semiconductor zones. According to the invention, each insulated conducting gate (3) has a width progressively increasing from the first semiconductor zone (1) to the second semiconductor zone (2). The width of each gate (3) is sufficiently narrow for the potential well created by the application of a voltage V to the gate to have a depth increasing progressively from the first zone (1) to the second zone (2), thus enabling the charges to be driven away. The invention applies to any type of charge-coupled device and particularly to photodiodes.

Abstract: a pixel is formed in a substrate having a first conductivity type, the pixel being coupled to a register for output. The pixel includes a pixel channel of a second conductivity type formed in the substrate, a transfer gate electrode, a storage gate electrode and a photodiode. The pixel channel includes a transfer portion at a first end of the pixel channel proximal to the register, a diode portion at a second end distal to the register and a storage portion between the transfer portion and the diode portion. The transfer gate electrode is insulatively spaced over the transfer portion, and the storage gate electrode is insulatively spaced over the storage portion. The diode is formed within the diode portion using the storage gate electrode as a mask.

Abstract: A first conductive layer and a second conductive layer are formed apart from each other on a surface of a semiconductor substrate. A first contact hole for exposing a surface of first conductive layer is formed in an interlayer insulating film. A first interconnection layer is buried in first contact hole so as to be in contact with first conductive layer. The position of the surface of first interconnection layer is the same as or lower than the surface of interlayer insulating film. The surface of first interconnection layer is covered with an insulating film. A second contact hole for exposing a surface of second conductive layer is provided in interlayer insulating film. A second conductive layer is connected to second conductive layer through second contact hole.

Abstract: A transistor having a source/drain metal silicide in close proximity to the channel region may be formed according to the following process. A masking structure is formed upon a semiconductor substrate, and a metal is deposited self-aligned to sidewall surfaces of the masking structure. The metal is then annealed to form a metal silicide. Following formation of lightly doped drain impurity areas self-aligned to the sidewall surfaces of the masking structure, spacers may be formed adjacent the sidewall surfaces and source and drain impurity areas may be formed self-aligned to sidewall surfaces of the spacers. Fill structures are then formed adjacent the spacers and the masking structure is removed to form an opening between the spacers. A gate dielectric is formed upon the exposed upper surface of the semiconductor substrate within the opening, and a gate conductor is formed within the opening.

Abstract: A semiconductor pressure sensor utilizing electrostatic capacitance has a plurality of pressure sensing electrostatic capacitances and a reference electrostatic capacitance formed on one side of a silicon chip. As a movable electrode, the pressure sensing electrostatic capacitances each have a diaphragm, which may have a displacement portion composed of a central area thereof, and a peripheral portion which is more deformable than the central portion.

Abstract: A highly integrated semiconductor device is made using a high precision manufacturing process having a comparatively small number of process steps. The device is substantially free of misalignment between structures formed with respect to openings formed in the middle of layers. An interlayer insulating film with an opening is formed on a first conductor, and a second conductor is deposited on the resultant structure. Part of the second conductor enters the opening, thereby producing a depression in the second conductor, which has a sharp-angled bottom situated at the horizontal center of the opening. A film made of, for example, a nitride is deposited on the second conductor to fill the depression. Thereafter, this film is removed such that part of it remains in the depression. Using the remaining film as a mask, the second conductor is removed to the same level as the interlayer insulting film.

Abstract: In a charge coupled device, trap levels formed by insulating layers or floating electrodes are formed on a semiconductor layer or a semiconductor substrate. Stationary charges are trapped in some of the trap levels or floating electrodes. The charge transfer electrodes are in self-alignment with potential barrier regions.

Abstract: A first silicon oxide film, silicon nitride film, and polycrystalline silicon film are formed on the entire surface of a semiconductor substrate. Then, the polycrystalline silicon film is etched to form a first transfer electrode and then, the surface of the first transfer electrode is thermally oxidized to form a second silicon oxide film. Thereafter, a polycrystalline silicon film and a third silicon oxide film are formed on the entire surface and patterned to form a second transfer electrode. A fourth silicon oxide film is formed on the entire surface, and is etched back. Thereafter, the side wall surfaces of the third silicon oxide film and the second transfer electrode are covered with a fourth silicon oxide film. Thereafter, a light shielding film is selectively formed on them.

Abstract: A CCD sensor includes a readout register formed in substrate, the readout register including a channel, a bus structure and a connection structure. The bus structure includes plural spaced element sets, each element set including a first clock conductor. The first clock conductor of a first element set is a dual function conductor. The connection structure isolates the dual function conductor while coupling together the first clock conductor of each other set of the element sets. Alternatively, the sensor includes vertical and readout registers formed in a well in a substrate. The vertical register includes a vertical channel, a vertical bus structure and a vertical connection structure, and the readout register includes a readout channel, a readout bus structure and a readout connection structure. The readout bus structure includes plural spaced readout element sets, each readout element set including a first readout clock conductor.

Abstract: A monolithic three dimensional charged coupled device (3D-CCD) which utilizes the entire bulk of the semiconductor for charge generation, storage, and transfer. The 3D-CCD provides a vast improvement of current CCD architectures that use only the surface of the semiconductor substrate. The 3D-CCD is capable of developing a strong E-field throughout the depth of the semiconductor by using deep (buried) parallel (bulk) electrodes in the substrate material. Using backside illumination, the 3D-CCD architecture enables a single device to image photon energies from the visible, to the ultra-violet and soft x-ray, and out to higher energy x-rays of 30 keV and beyond. The buried or bulk electrodes are electrically connected to the surface electrodes, and an E-field parallel to the surface is established with the pixel in which the bulk electrodes are located. This E-field attracts charge to the bulk electrodes independent of depth and confines it within the pixel in which it is generated.

Abstract: A method for fabricating a solid-state image sensor includes the steps of forming a well of a first conductivity type in a substrate of a second conductivity type, forming a plurality of photoelectric conversion regions in the well, forming a plurality of charge coupled devices in the photoelectric conversion regions, forming a gate insulating layer over the substrate, forming a polysilicon layer over the gate insulating layer, forming a cap insulating layer over the polysilicon layer, forming a first optical shielding metal layer over the cap insulating layer, forming a first insulating layer over the first optical shielding metal layer, patterning the polysilicon layer, cap insulating layer, the first optical shielding metal layer, and the first insulating layer to form polygates, forming sidewall spacers on sides of the cap insulating layer and the polygate, forming a second optical shielding metal layer on sides of the first optical shielding metal layer and the sidewall spacers, and removing the first in

Abstract: The present invention is directed to an improved CCD utilizing a potential gradient along the lengths of the various channels of the CCD during charge transfer to cause generated electrical charge to migrate along the length of the channel to a summing well. The potential gradient is formed by biasing the opposing ends of the electrodes overlying the lengths of the various channels with different voltages.

Abstract: A solid state image pickup device includes a semiconductor substrate, a CCD channel region in the semiconductor substrate, a plurality of polygates over the CCD channel regions, and a photoelectric conversion region having a portion above an uppermost surface of the semiconductor substrate.

Abstract: A semiconductor device comprises a semiconductor substrate, and a plurality of semiconductor elements provided on the semiconductor substrate. Each of the semiconductor elements includes a gate dielectric film formed on the semiconductor substrate, a gate electrode formed on the semiconductor substrate with the gate dielectric film interposed therebetween, and having a pair of side surfaces, and source/drain regions formed in a surface of the semiconductor substrate along the pair of the side surfaces. The gate electrode contains a plurality of crystal grains, and the number of the crystal grains is substantially equal to the number of crystal grains contained in any other gate electrode of all the semiconductor elements.

Abstract: A field effect transistor relative to a semiconductor substrate, where the transistor has a gate which defines a resultant lateral expanse of semiconductive material therebeneath for provision of a transistor channel region, includes a) providing a conductive gate layer over a semiconductor substrate; b) patterning the conductive gate layer into a first gate block, the first gate block having a first lateral expanse which is greater than the resultant lateral expanse; c) providing an insulating dielectric layer over the first gate block; d) providing a patterned layer of photoresist over the first gate block and the insulating dielectric layer, the patterned photoresist comprising a photoresist block positioned over and within the first lateral expanse of the first gate block; e) with the patterned photoresist in place, etching the insulating dielectric layer selectively relative to the first gate block; f) after etching the insulating dielectric layer and with the patterned photoresist in place, etching the

Abstract: A CCD shift register includes a continuous buried channel over a length of the shift register, a plurality of conductor segments, a plurality of narrow bus segments, and a plurality of wide busses. Each conductor segment includes a plurality of sets of conductors, and each set of conductors includes plurality of conductors, each conductor in a set corresponding to a respective clock signal of a plurality of clock signals. Each conductor of each set extends across the buried channel. A first narrow bus segment of the plurality of narrow bus segments includes a plurality of narrow busses that are disposed parallel to and offset from the buried channel, each narrow bus corresponding to a respective clock signal of the plurality of clock signals, and each narrow bus is coupled to a respective conductor of each set of a first conductor segment.

Abstract: A control structure for stage selection in a CCD sensor includes a well formed in a substrate and a channel formed in the well, the channel defining a channel direction. A bus structure is disposed over the channel and oriented transversely to the channel direction, the bus structure including a plurality of uniformly spaced register element sets. The plurality of uniformly spaced register element sets includes a first register element set and a plurality of remaining register element sets. The first register element set includes a first clock signal conductor and at least one other clock signal conductor. Each set of the plurality of remaining register element sets includes a first clock signal conductor and at least one other clock signal conductor.

Abstract: An active type photoelectric conversion device includes a pixel having a photoelectric conversion area and a gate area which are formed in a surface portion of a semiconductor substrate of a first conductivity type.

Abstract: In a method of manufacturing a charge coupled device, a channel layer is formed on a surface of a semiconductor substrate. Then, first layer transfer electrodes are formed in a charge transfer direction above the channel layer via a first insulating film. Subsequently, second layer transfer electrodes are formed such that each of the second layer transfer electrodes is disposed between two of the first layer transfer electrodes without any portion overlapping the first layer transfer electrodes in a plane structure. The second layer transfer electrodes may be patterned after a polysilicon film is deposited and polished or may be polished after the polysilicon film is deposited and patterned.

Abstract: In a solid-state image pickup device having photoelectric converting sections, vertical charge transfer sections, and a horizontal charge transfer section, the vertical charge transfer sections include first, second, and third vertical charge transfer electrodes The third (final) vertical charge transfer electrode, which is adjacent to the horizontal charge transfer section, is electrically connected to a shunt wire (a first shading film) via lining contacts. A second shading film is formed electrically separated from the shunt wire, for light-shielding areas between photoelectric converting sections in a vertical direction.

Abstract: A solid state image sensor includes a semiconductor substrate and a plurality of transfer lines over the substrate and receiving clock signals, at least one of the plurality of transfer lines having a transparent conductive material. A plurality of transfer electrodes are connected to the transfer lines and a plurality of photoelectric conversion regions under a surface of the substrate generate image signals. A plurality of charge transfer regions under the surface of the substrate transfer the image signals from the photoelectric conversion regions in response to the clock signals from the transfer lines.

Abstract: Support for an electrochemical deposit, comprising a substrate (120) and, on the latter, a plurality of first conductive surfaces (128) able to form electrodes, at least one second conductive surface (116) for forming a counterelectrode and means (130, 132, 133, 135) for connecting said first conductive surfaces and said second conductive surface to a voltage source.

Abstract: By incorporating an ITO electrode which is more transparent than polysilicon, and designing the pixel such that it has asymmetric gates with as much as possible of its light sensitive region covered by an ITO electrode, light sensitivity is increased. To solve the problem of impurity diffusion from the ITO electrode into the silicon below, the conventional Silicon Dioxide gate dielectric was replaced with an Oxide/Nitride/Oxide stack. Employing at least some polysilicon electrodes with ITO electrodes is desirable to allow entrance passages through which hydrogen passivation can be accomplished. The pixel architecture can be designed to increase sensitivity further by other design choices. The first of these choices is to incorporate a lenslet on each pixel such that as much as possible of the light falling on the pixel is made to pass through the portion of the pixel covered with ITO.

Abstract: A charge transfer device including a semiconductor substrate, a gate electrode provided in association with the substrate, the gate electrode having a corresponding channel region through which charge is propagated, the channel region having a predetermined potential; and means associated with the channel region for reducing charge trapping and recombination effects. In one aspect of the present invention, the reducing means includes a potential pocket defined within the channel region having a greater potential than the predetermined potential of said channel region. The potential pocket has a width dimension which is less than the corresponding width dimension of the channel region. The potential pocket is positioned in the center of the gate electrode, and is positioned so as to be aligned with a front edge of the gate electrode.

Abstract: The amplification type solid-state imaging device of this invention includes amplification type photoelectric converting elements arranged in a matrix.

Abstract: The present invention is a diamond electrode with high efficiency, a small overvoltage, and a long lifetime, which is reusable, and which can measure the temperature of the electrode. The diamond electrode is at least partially composed of a semiconducting diamond film, whose surface is chemically modified. Another embodiment of the present invention carbon is used as a bare electrode material, diamond crystals are fixed to the bare electrode material, the surface of the undoped diamond crystals are covered with semiconducting diamond film, or semiconducting diamond crystals are fixed to said bare electrode material, and the surfaces of diamond films or crystals are chemically modified. Furthermore, wires may be connected to the diamond electrode to measure the electrical resistance, and hence the temperature.

Abstract: A multidirectional charge transfer device configured in a charge storage medium. The device includes an array of charge storage regions. Each of said charge storage regions includes a plurality of first gates, each of which is arranged in a first portion of each charge storage region, a plurality of second gates, each of which is arranged in a second portion of each charge storage region, a plurality of third gates, each of which is arranged in a third portion of each charge storage region, and a plurality of fourth gates, each of which is arranged in a fourth portion of each charge storage region. The plurality of gates and charge storage regions are configured to define at least three bidirectional charge transfer paths which are noncollinear with respect to each other. The plurality of gates are sequentially biased to establish charge transfer along one of said bidirectional charge transfer paths and forming blocking potentials to charge transfer in the remaining charge transfer paths.

Abstract: A charge transfer image pickup device is disclosed. One embodiment of the device includes a plurality of photoelectric conversion elements for producing signal charges in response to light applied thereto. A vertical charge transfer part including a first region having a first well layer and for transferring the signal charges produced by the photoelectric conversion elements is provided. A horizontal charge transfer part including a second region having a second well layer and coupled to the vertical charge transfer part to receive transferred signal charges by using a terminal vertical transfer electrode of the vertical charge transfer part is also included. The first and second well layers partially overlap to form an overlap section that does not extend over the terminal vertical transfer electrode in the direction from the second region to the first region.

Abstract: Disclosed is a solid state image device which has a plurality of photosensitive units which are disposed in parallel with each other and each of which includes a row of a plurality of photosensitive devices each of which includes a first N(or P)-type impurity region which is selectively formed on the surface of a P(or N)-type semiconductor region at the surface of a semiconductor substrate, a CCD register for executing electronic scanning which is disposed in parallel to the row of photosensitive devices, and a read-out gate in which a signal charge is transferred from the photosensitive device to the CCD register, wherein a transparent Schottky electrode is formed on the first N(or P)-type impurity region except a portion adjacent to the read-out gate region, the Schottky electrode is electrically connected to a P.sup.+ (or N.sup.

Abstract: A metal-semiconductor type field effect transistor has a Y-letter shaped gate electrode standing on an active layer, and the Y-letter shaped gate electrode prevents piezoelectric charges induced beneath both ends of the wing portions thereof from undesirable merger so as to restrict variation of the threshold regardless of the orientation of the Y-letter shaped gate electrode.

Abstract: A structure for a charge coupled device (CCD) to minimize effects of masking defects of a predetermined dimensional extent includes a plurality of sets of conductors, a plurality of strapping networks and a connection matrix of via contacts. Each set of the plurality of sets of conductors includes a plurality of parallel elongate first conductors oriented in a first direction and disposed substantially in a first plane, each first conductor being comprised of a first material and characterized by a first sheet resistance per square of conductor.