Plural Gate Levels Patents (Class 257/250)
  • Patent number: 11145682
    Abstract: An array substrate which includes a display region and a peripheral region surrounding the display region, the peripheral region includes a data line lead region and a driving circuit region, and the data line lead region is between the driving circuit region and the display region; the driving circuit region includes a driving circuit, the data line lead region includes a the plurality of data line leads, and the plurality of data line leads extend from the display region and are electrically connected with the driving circuit; and the data line lead region includes peripheral data line leads, a region of the peripheral region close to the peripheral data line leads includes at least one retaining wall configured to prevent plasma from affecting the peripheral data line leads. A method for fabricating an array substrate, a display panel, and a display device are also disclosed.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: October 12, 2021
    Assignees: ORDOS YUANSHENG OPTOELECTRONICS CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Yanan Yu, Jingyi Xu, Yanwei Ren, Xin Zhao, Xiaokang Wang, Yuelin Wang, Huijie Zhang
  • Patent number: 10559573
    Abstract: A layout pattern of a static random access memory (SRAM) includes a substrate, a first pull-up transistor (PL1), a first pull-down transistor (PD1), a second (PL2), and a second pull-down transistor (PD2) on the substrate, and a first pass gate transistor (PG1A), a second pass gate transistor (PG1B), a third pass gate transistor (PG2A) and a fourth pass gate transistor (PG2B), wherein the PG1A and the PG1B comprise a first fin structure, the PG2A and the PG2B comprise a second fin structure, a first local interconnection layer disposed between the PG1A and the PG1B and disposed on the fin structures of the PL1 and the PD1, a second local interconnection layer disposed between the PG2A and the PG2B and disposed between the fin structures of the PL2 and the PD2, the first local interconnection layer and the second local interconnection layer are monolithically formed structures respectively.
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: February 11, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shu-Ru Wang, Ching-Cheng Lung, Yu-Tse Kuo, Chien-Hung Chen, Chun-Hsien Huang, Li-Ping Huang, Chun-Yen Tseng, Meng-Ping Chuang
  • Patent number: 10515970
    Abstract: A static random access memory (SRAM) cell includes first through fourth transistors being first type transistors and fifth and sixth transistors being second type transistors. Source regions of the first and second transistors are formed by a first source diffusion region, source regions of the fifth and sixth transistors are formed by second and third source diffusion regions, respectively, and source regions of the third and fourth transistors are formed by a fourth source diffusion region. The SRAM cell further includes a first data storage electrode linearly extending from a first gate line of the third and sixth transistors and electrically connecting the first gate line and the first and second source diffusion regions, and a second data storage electrode linearly extending from a second gate line of the second and fifth transistors and electrically connecting the second gate line and the third and fourth source diffusion regions.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: December 24, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Hsiu Hsu, Chong-De Lien
  • Patent number: 10032885
    Abstract: A method includes removing a top portion of a substrate after implantation of a punch through stopper into the substrate; epitaxially growing undoped material on the substrate, thereby forming a channel; filling a top portion of the channel with an intermediate implant forming a vertically bi-modal dopant distribution, with one doping concentration peak in the top portion of the channel and another doping concentration peak in the punch through stopper; and patterning fins into the channel and the punch though stopper to form a finFET structure.
    Type: Grant
    Filed: June 13, 2016
    Date of Patent: July 24, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Gauri Karve, Robert R. Robison, Reinaldo A. Vega
  • Patent number: 9985101
    Abstract: Various nanostructures, including silicon nanowires and encapsulated silicon nanoislands, and methods of making the nanostructures are provided. The methods can include providing a fin structure extending above a substrate, wherein the fin structure has at least one silicon layer and at least two silicon:germanium alloy (SiGe) layers that define sidewalls of the fin structure; and annealing the fin structure in oxygen to form a silicon nanowire assembly. The silicon nanowire assembly can include a silicon nanowire, a SiGe matrix surrounding the silicon nanowire; and a silicon oxide layer disposed on the SiGe matrix. The annealing can be, for example, at a temperature between 800° C. and 1000° C. for five minutes to sixty minutes. The silicon nanowire can have a long axis extending along the fin axis, with perpendicular first and second dimensions extending less than 50 nm along directions perpendicular to the fin axis.
    Type: Grant
    Filed: October 27, 2016
    Date of Patent: May 29, 2018
    Assignees: Varian Semiconductor Equipment Associates, Inc., University of Florida Research Foundation, Inc.
    Inventors: Christopher Hatem, Kevin S. Jones, William M. Brewer
  • Patent number: 9859417
    Abstract: A high-voltage MOS transistor includes a semiconductor substrate, a gate oxide layer on the semiconductor substrate, a gate on the gate oxide layer, a spacer covering a sidewall of the gate, a source on one side of the gate, and a drain on the other side of the gate. The gate includes at least a first discrete segment and a second discrete segment. The first discrete segment is not in direct contact with the second discrete segment. The spacer fills into a gap between the first discrete segment and the second discrete segment.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: January 2, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shih-Yin Hsiao, Kuan-Liang Liu, Ching-Chung Yang, Kai-Kuen Chang, Ping-Hung Chiang, Nien-Chung Li, Wen-Fang Lee, Chih-Chung Wang
  • Patent number: 9847404
    Abstract: This improved, fluctuation resistant FinFET, with a doped core and lightly doped epitaxial channel region between that core and the gate structure, is confined to the active-gate span because it is based on a channel structure having a limited extent. The improved structure is capable of reducing FinFET random doping fluctuations when doping is used to control threshold voltage, and the channel structure reduces fluctuations attributable to doping-related variations in effective channel length. Further, the transistor design affords better source and drain conductance when compared to prior art FinFETs. Two representative embodiments of the key structure are described in detail.
    Type: Grant
    Filed: September 11, 2013
    Date of Patent: December 19, 2017
    Assignees: SemiWise Limited, Semi Solutions LLC
    Inventors: Robert J. Strain, Asen Asenov
  • Patent number: 9754939
    Abstract: Integrated circuits including multiple gate devices with dual threshold voltages and methods for fabricating such integrated circuits are provided. An exemplary method for fabricating an integrated device includes providing a semiconductor fin structure overlying a semiconductor substrate. The semiconductor fin structure has a first sidewall, a second sidewall opposite the first sidewall, and an upper surface. The method includes forming a first gate along the first sidewall of the semiconductor fin structure with a first threshold voltage. Further, the method includes forming a second gate along the second sidewall of the semiconductor fin structure with a second threshold voltage different from the first threshold voltage.
    Type: Grant
    Filed: November 11, 2015
    Date of Patent: September 5, 2017
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Shyue Seng Tan, Kiok Boone Elgin Quek
  • Patent number: 9741721
    Abstract: Low leakage non-planar access transistors for embedded dynamic random access memory (eDRAM) and methods of fabricating low leakage non-planar access transistors for eDRAM are described. For example, a semiconductor device includes a semiconductor fin disposed above a substrate and including a narrow fin region disposed between two wide fin regions. A gate electrode stack is disposed conformal with the narrow fin region of the semiconductor fin, the gate electrode stack including a gate electrode disposed on a gate dielectric layer. The gate dielectric layer includes a lower layer and an upper layer, the lower layer composed of an oxide of the semiconductor fin. A pair of source/drain regions is included, each of the source/drain regions disposed in a corresponding one of the wide fin regions.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: August 22, 2017
    Assignee: Intel Corporation
    Inventors: Joodong Park, Gopinath Bhimarasetti, Rahul Ramaswamy, Chia-Hong Jan, Walid M. Hafez, Jeng-Ya D. Yeh, Curtis Tsai
  • Patent number: 9735275
    Abstract: A method includes removing a top portion of a substrate after implantation of a punch through stopper into the substrate; epitaxially growing undoped material on the substrate, thereby forming a channel; filling a top portion of the channel with an intermediate implant forming a vertically bi-modal dopant distribution, with one doping concentration peak in the top portion of the channel and another doping concentration peak in the punch through stopper; and patterning fins into the channel and the punch though stopper to form a finFET structure.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: August 15, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Gauri Karve, Robert R. Robison, Reinaldo A. Vega
  • Patent number: 9735255
    Abstract: A method includes providing a substrate having a fin extending from a first (e.g., top) surface of the substrate. The fin has first region (a stem region) and a second region (an active region) each having a different composition. The first region of the fin is modified to decrease a width of semiconductor material for example by etching and/or oxidizing the first region of the fin. The method then continues to provide a gate structure on the second region of the fin. FinFET devices having stem regions with decreased widths of semiconductor material are also provided.
    Type: Grant
    Filed: January 18, 2013
    Date of Patent: August 15, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jean-Pierre Colinge, Kuo-Cheng Ching, Zhiqiang Wu
  • Patent number: 9653314
    Abstract: A semiconductor device according to the present embodiment includes a plurality of wires. A plurality of wire drawing pads are provided correspondingly to the wires and electrically connecting a plurality of contacts to the wires, respectively. First space portions widen toward a first direction from the wires to the wire drawing pads and are located between adjacent ones of the wire drawing pads in a connection region between the wires and the wire drawing pads. Second space portions are provided at edge portions of the wire drawing pads. Air gaps or insulating layers are provided in the first space portions and the second space portions.
    Type: Grant
    Filed: December 17, 2014
    Date of Patent: May 16, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Satoshi Nagashima, Koichi Matsuno, Takashi Sugihara, Hiroaki Naito
  • Patent number: 9653551
    Abstract: Field effect transistors are provided. According to the field effect transistor, a source region and a drain region are provided on a substrate and a fin portion is provided to protrude from the substrate. The fin portion connects the source region and the drain region to each other. A gate electrode pattern is disposed on the fin portion and extends to cross over the fin portion. A gate dielectric layer is disposed between the fin portion and the gate electrode pattern. A semiconductor layer is disposed between the fin portion and the gate dielectric layer. The semiconductor layer and the fin portion have dopant-concentrations different from each other, respectively.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: May 16, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Changwoo Oh, Myung Gil Kang, Bomsoo Kim, Jongshik Yoon
  • Patent number: 9647062
    Abstract: Techniques for a semiconductor device are provided. Techniques are directed to forming a semiconductor device by: forming a fin structure in a substrate, forming a protective layer over an upper portion of the fin structure, the protective layer having an etch selectivity with respect to a material of the fin structure, and performing an undercut etch so as to remove a lower portion of the fin structure below the protective layer, thereby defining a nanowire structure from the fin structure.
    Type: Grant
    Filed: July 22, 2015
    Date of Patent: May 9, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chia-Yu Chen, Zuoguang Liu, Tenko Yamashita
  • Patent number: 9559181
    Abstract: The present disclosure provides a semiconductor device that includes a substrate of a first semiconductor material; a fin feature having a first portion, a second portion and a third portion stacked on the substrate; an isolation feature formed on the substrate and disposed on sides of the fin feature; semiconductor oxide features including a second semiconductor material, disposed on recessed sidewalls of the second portion, defining dented voids overlying the semiconductor oxide features and underlying the third portion; and a gate stack disposed on the fin feature and the isolation feature. The gate stack includes a gate dielectric layer extended into and filling in the dented voids. The first and third portions include the first semiconductor material having a first lattice constant. The second portion includes the second semiconductor material having a second lattice constant different from the first lattice constant.
    Type: Grant
    Filed: November 26, 2013
    Date of Patent: January 31, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng Ching, Chih-Hao Wang, Zhiqiang Wu, Carlos H. Diaz
  • Patent number: 9543441
    Abstract: At least one method, apparatus and system disclosed herein fin field effect transistor (finFET) comprising a bulbous fin head. A fin of a gate of a transistor is formed. A first recess step is performed for striping a hard mask material by a first dimension to expose a first portion of the fin. An epitaxy layer is formed upon the first portion. An oxidation process is performed upon the fin. An oxide removal process is performed upon the fin to provide a bulbous shape upon the first portion.
    Type: Grant
    Filed: March 11, 2015
    Date of Patent: January 10, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ki Young Lee, Byoung-Gi Min, Kijik Lee
  • Patent number: 9392736
    Abstract: A charge-coupled device (CCD) image sensor includes multiple vertical charge-coupled device (VCCD) shift registers and independently-controllable gate electrodes disposed over the VCCD shift registers and arranged into physically separate and distinct sections that are non-continuous across the plurality of VCCD shift registers. The CCD image sensor can be configured to operate in two or more operating modes, including a full resolution charge multiplication mode.
    Type: Grant
    Filed: July 29, 2013
    Date of Patent: July 12, 2016
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Antonio S. Ciccarelli, Eric J. Meisenzahl
  • Patent number: 9368501
    Abstract: A semiconductor memory device which includes a memory cell including two or more sub memory cells is provided. The sub memory cells each including a word line, a bit line, a first capacitor, a second capacitor, and a transistor. In the semiconductor device, the sub memory cells are stacked in the memory cell; a first gate and a second gate are formed with a semiconductor film provided therebetween in the transistor; the first gate and the second gate are connected to the word line; one of a source and a drain of the transistor is connected to the bit line; the other of the source and the drain of the transistor is connected to the first capacitor and the second capacitor; and the first gate and the second gate of the transistor in each sub memory cell overlap with each other and are connected to each other.
    Type: Grant
    Filed: December 2, 2014
    Date of Patent: June 14, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama
  • Patent number: 9368592
    Abstract: The present disclosure provides a semiconductor structure, including a substrate, a metal gate, a dielectric layer, and an etch stop layer. The metal gate is positioned on the substrate and possesses a first surface. The dielectric layer surrounds the metal gate and possesses a second surface. The etch stop layer is in contact with both the first surface and the second surface. The first surface is higher than the second surface. The present disclosure also provides a method for manufacturing a semiconductor structure, including forming a dummy gate on a substrate; forming a second etch stop layer over the dummy gate; forming a dielectric layer over the dummy gate; replacing the dummy gate with a metal gate; etching back the dielectric layer to form a second surface of the dielectric layer lower than a first surface of the metal gate; and forming a first etch stop layer over the metal gate and the dielectric layer.
    Type: Grant
    Filed: January 28, 2014
    Date of Patent: June 14, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yi-Fang Li, Chun-Sheng Wu
  • Patent number: 9269718
    Abstract: In accordance with an embodiment, a manufacturing method of a semiconductor device includes: forming memory cells and select transistors on a semiconductor substrate configured to select any memory cell, forming a first insulating nitride film, forming a contact, and selectively removing the first insulating nitride film. The first insulating nitride film is formed so as to cover the semiconductor substrate between the select transistors adjacent in the first direction, the select transistors, and the memory cells. The first insulating nitride film is selectively removed in a region other than the region in which the contact is formed and in a region above the select transistors or the memory cells.
    Type: Grant
    Filed: March 13, 2015
    Date of Patent: February 23, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Nobuhito Kuge, Hiroshi Akahori
  • Patent number: 9070570
    Abstract: Stack packages are provided. The stack package includes a substrate having first and second bond fingers and a plurality of semiconductor chips stacked on the substrate. Each of the plurality of semiconductor chips has an input bonding pad and an output bonding pad. A first interconnection electrically connects the first bond finger to the input bonding pad of a lowermost semiconductor chip of the plurality of semiconductor chips. A second interconnection electrically connects the output bonding pad of a lower semiconductor chip of the plurality of semiconductor chips to the input bonding pad of an upper semiconductor chip stacked on the lower semiconductor chip. A third interconnection electrically connects the output bonding pad of an uppermost semiconductor chip of the plurality of semiconductor chips to the second bond finger.
    Type: Grant
    Filed: November 5, 2014
    Date of Patent: June 30, 2015
    Assignee: SK Hynix Inc.
    Inventor: Ki Yong Lee
  • Patent number: 9070550
    Abstract: A semiconductor device includes a transistor formed by dividing into a first and a second areas, a source electrode pad connected with a first source region formed in the first area and a second source region formed in the second area, a drain electrode pad connected with a first drain region formed in the first area and a second drain region formed in the second area and a connection line to connect a first gate line and a second gate line, where the connection line being provided in a same layer as the first gate line formed in the first area and the second gate line formed in the second area. A wiring for connecting between nodes of another circuit can be provided over the layer having the connection line provided therein and thus the size of a circuit chip can be reduced.
    Type: Grant
    Filed: August 18, 2007
    Date of Patent: June 30, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Daisaku Kobayashi, Takayoshi Fujishiro
  • Patent number: 9018683
    Abstract: The purpose of the present invention is to improve the efficiency of conversion between terahertz electromagnetic wave energy and direct current energy via plasma waves in a terahertz electromagnetic wave conversion device with a field effect transistor structure. This invention has an HEMT structure having a substrate, an electron transit layer, an electron supply layer, a source and a drain, and includes a first and second group of gates. The gate length of each finger of the first group of gates is narrower than the gate length of each finger of the second group of gates, and each finger of each group of gates is disposed between the source and the drain on the same cycle. A first and second distance from each finger of the first group of gates to two fingers of the second group of gates adjacent to each finger are unequal lengths.
    Type: Grant
    Filed: December 3, 2010
    Date of Patent: April 28, 2015
    Assignees: Tohoku University, Centre National de la Recherche Scientifique (CNRS), Universite Montpellier 2
    Inventors: Taiichi Otsuji, Viacheslav Popov, Wojciech Knap, Yahya Moubarak Meziani, Nina Diakonova, Dominique Coquillat, Frederic Teppe, Denis Fateev, Jesus Enrique Velazquez Perez
  • Patent number: 8963214
    Abstract: A thin film transistor for an organic light emitting display device is disclosed. In one embodiment, the thin film transistor includes: a substrate, an active layer formed over the substrate, wherein the active layer is formed of an oxide semiconductor, a gate insulating layer formed over the substrate and the active layer, and source and drain electrodes formed on the gate insulating layer and electrically connected to the active layer. The transistor may further include a gate electrode formed on the gate insulating layer and formed between the source and drain electrodes, wherein the gate electrode is spaced apart from the source electrode so as to define a first offset region therebetween, and wherein the gate electrode is spaced apart from the drain electrode so as to define a second offset region therebetween.
    Type: Grant
    Filed: September 28, 2010
    Date of Patent: February 24, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventors: Roman Kondratyuk, Ki-Ju Im, Dong-Wook Park, Yeon-Gon Mo, Hye-Dong Kim
  • Patent number: 8952427
    Abstract: A range image sensor capable of improving its aperture ratio and yielding a range image with a favorable S/N ratio is provided. A range image sensor RS has an imaging region constituted by a plurality of one-dimensionally arranged units on a semiconductor substrate 1 and yields a range image according to a charge amount issued from the units.
    Type: Grant
    Filed: November 18, 2010
    Date of Patent: February 10, 2015
    Assignee: Hamamatsu Photonics K.K
    Inventors: Takashi Suzuki, Mitsuhito Mase
  • Patent number: 8907392
    Abstract: A semiconductor memory device which includes a memory cell including two or more sub memory cells is provided. The sub memory cells each including a word line, a bit line, a first capacitor, a second capacitor, and a transistor. In the semiconductor device, the sub memory cells are stacked in the memory cell; a first gate and a second gate are formed with a semiconductor film provided therebetween in the transistor; the first gate and the second gate are connected to the word line; one of a source and a drain of the transistor is connected to the bit line; the other of the source and the drain of the transistor is connected to the first capacitor and the second capacitor; and the first gate and the second gate of the transistor in each sub memory cell overlap with each other and are connected to each other.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: December 9, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama
  • Patent number: 8907382
    Abstract: A semiconductor device is provided. An insulating buried layer is formed in a substrate. Deep trench insulating structures are formed on the insulating buried layer. A deep trench contact structure is formed between the deep trench insulating structures. The deep trench contact structure is electrically connected with the substrate under the insulating buried layer.
    Type: Grant
    Filed: November 6, 2008
    Date of Patent: December 9, 2014
    Assignee: Vanguard International Semiconductor Corporation
    Inventor: Jui-Chun Chang
  • Patent number: 8907383
    Abstract: Stack packages are provided. The stack package includes a substrate having first and second bond fingers and a plurality of semiconductor chips stacked on the substrate. Each of the plurality of semiconductor chips has an input bonding pad and an output bonding pad. A first interconnection electrically connects the first bond finger to the input bonding pad of a lowermost semiconductor chip of the plurality of semiconductor chips. A second interconnection electrically connects the output bonding pad of a lower semiconductor chip of the plurality of semiconductor chips to the input bonding pad of an upper semiconductor chip stacked on the lower semiconductor chip. A third interconnection electrically connects the output bonding pad of an uppermost semiconductor chip of the plurality of semiconductor chips to the second bond finger.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: December 9, 2014
    Assignee: SK Hynix Inc.
    Inventor: Ki Yong Lee
  • Patent number: 8860814
    Abstract: A solid-state image sensor according to the present invention includes a number of photosensitive cells 2b, 2c that are arranged in between the first surface 30a of a semiconductor layer 30 and its second surface 30b, which is opposite to the first surface 30a and which receives incoming light. As viewed from the photosensitive cells 2b, 2c, a reflecting portion 3a is arranged on the same side as the first surface 30a in order to reflect an infrared ray that has been transmitted through the photosensitive cell 2c and make it incident on one of the photosensitive cells 2b, 2c. As a result, the intensities of infrared rays to be converted photoelectrically by the photosensitive cells 2b, 2c will be different from each other. And by calculating the difference between the photoelectrically converted signals supplied from the photosensitive cells 2b, 2c, the infrared ray component received by each photosensitive cell can be obtained.
    Type: Grant
    Filed: March 2, 2010
    Date of Patent: October 14, 2014
    Assignee: Panasonic Intellectual Property Corporation of America
    Inventors: Masao Hiramoto, Yoshiaki Sugitani
  • Patent number: 8809915
    Abstract: A gate conductor structure is provided having a barrier region between a N-type device and a P-type device, wherein the barrier region minimizes or eliminates cross-diffusion of dopant species across the barrier region. The barrier region comprises at least one sublithographic gap in the gate conductor structure. The sublithographic gap is formed by using self-assembling copolymers to form a sublithographic patterned mask over the gate conductor structure. According to one embodiment, at least one sublithographic gap is a slit or line that traverses the width of the gate conductor structure. The sublithographic gap is sufficiently deep to minimize or prevent cross-diffusion of the implanted dopant from the upper portion of the gate conductor. According to another embodiment, the sublithographic gaps are of sufficient density that cross-diffusion of dopants is reduced or eliminated during an activation anneal such that changes in Vt are minimized.
    Type: Grant
    Filed: April 18, 2013
    Date of Patent: August 19, 2014
    Assignee: International Business Machines Corporation
    Inventors: Wai-Kin Li, Haining S. Yang
  • Patent number: 8735951
    Abstract: A semiconductor device includes an isolation pattern disposed on a substrate, the isolation pattern defining an active part, a gate pattern crossing the active part on the substrate, the gate pattern including a dielectric pattern and a first conductive pattern, and the dielectric pattern being between the active part and the first conductive pattern, a pair of doping regions in the active part adjacent to side walls of the gate pattern, the gate pattern being between the pair of doping regions, and a diffusion barrier element injection region disposed in an upper region of the active part.
    Type: Grant
    Filed: December 16, 2011
    Date of Patent: May 27, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hajin Lim, Moonhan Park, Jinho Do, Moonkyun Song
  • Patent number: 8735976
    Abstract: A Thin Film Transistor-Liquid Crystal Display (TFT-LCD) array substrate is presented which includes a gate line, a data line, and a pixel electrode. The pixel electrode is disposed in a pixel region defined by the intersection between the gate line and the data line. In the pixel region, a partition groove for forming a pixel electrode pattern is provided at the periphery of the pixel electrode.
    Type: Grant
    Filed: February 26, 2013
    Date of Patent: May 27, 2014
    Assignee: Beijing Boe Optoelectronics Technology Co., Ltd.
    Inventors: Hongxi Xiao, Jae Yun Jung, Zuhong Liu, Taek Ho Hong, Jeong Hun Rhee
  • Patent number: 8722493
    Abstract: A first conductive layer and an underlying charge storage layer are patterned to form a control gate in an NVM region. A first dielectric layer and barrier layer are formed over the control gate. A sacrificial layer is formed over the barrier layer and planarized. A first patterned masking layer is formed over the sacrificial layer and control gate in the NVM region which defines a select gate location laterally adjacent the control gate in the NVM region. A second masking layer is formed in the logic region which defines a logic gate location. Exposed portions of the sacrificial layer are removed such that a first portion remains at the select gate location. A second dielectric layer is formed over the first portion and planarized to expose the first portion. The first portion is removed to result in an opening at the select gate location which exposes the barrier layer.
    Type: Grant
    Filed: April 9, 2012
    Date of Patent: May 13, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Mark D. Hall, Mehul D. Shroff
  • Patent number: 8586463
    Abstract: A method for fabricating a layer including nickel monosilicide NiSi on a substrate including silicon. The method includes the steps of incorporating, on a portion of the thickness of the substrate comprising silicon, an element selected from W, Ti, Ta, Mo, Cr and mixtures thereof; depositing, on the substrate, a layer of nickel and a layer of an element selected from Pt, Pd, Rh, and mixtures thereof or a layer comprising both nickel and an element selected from Pt, Pd, Rh, and mixtures thereof; heating to a temperature sufficient for obtaining the formation of a layer comprising nickel silicide optionally in the form of nickel monosilicide NiSi; incorporating fluorine in the layer; and optionally, heating to a sufficient temperature to convert the layer to a layer comprising nickel silicide entirely in the form of nickel monosilicide NiSi.
    Type: Grant
    Filed: November 5, 2009
    Date of Patent: November 19, 2013
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Fabrice Nemouchi, Veronique Carron
  • Patent number: 8518794
    Abstract: Provided is a semiconductor device. The semiconductor device includes: a substrate; an active layer on the substrate; a capping layer on the active layer; source/drain electrodes on the capping layer; a gate electrode on the active layer; and a first void region on a first sidewall of the gate electrode and a second void region on a second sidewall facing the first sidewall.
    Type: Grant
    Filed: September 1, 2010
    Date of Patent: August 27, 2013
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Hokyun Ahn, Jong-Won Lim, Hyung Sup Yoon, Woojin Chang, Hae Cheon Kim
  • Patent number: 8513125
    Abstract: A method for manufacturing a device comprising a structure with nanowires based on a semiconducting material such as Si and another structure with nanowires based on another semiconducting material such as SiGe, and is notably applied to the manufacturing of transistors.
    Type: Grant
    Filed: August 30, 2010
    Date of Patent: August 20, 2013
    Assignee: Commissariat a l'energie atomique et aux alternatives
    Inventors: Emeline Saracco, Jean-Francois Damlencourt, Michel Heitzmann
  • Patent number: 8492210
    Abstract: The invention relates to a transistor, a semiconductor device comprising the transistor and manufacturing methods for the transistor and the semiconductor device. The transistor according to the invention comprises: a substrate comprising at least a base layer, a first semiconductor layer, an insulating layer and a second semiconductor layer stacked sequentially; a gate stack formed on the second semiconductor layer; a source region and a drain region located on both sides of the gate stack respectively; a back gate comprising a back gate dielectric and a back gate electrode formed by the insulating layer and the first semiconductor layer, respectively; and a back gate contact formed on a portion of the back gate electrode. The back gate contact comprises an epitaxial part raised from the surface of the back gate electrode, and each of the source region and the drain region comprises an epitaxial part raised from the surface of the second semiconductor layer.
    Type: Grant
    Filed: February 25, 2011
    Date of Patent: July 23, 2013
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Qingqing Liang, Huilong Zhu, Huicai Zhong
  • Patent number: 8481375
    Abstract: A method for producing a semiconductor device includes a step of forming a first insulation film, a step of forming a separation layer in a base layer, a step of forming a light-blocking film on the surface of the first insulation film, a step of forming a second insulation film such that the light-blocking film is covered, a step of affixing the base layer provided with the light-blocking film to a substrate, a step of separating and removing along the separation layer a portion of the base layer affixed to the substrate, and a step of forming a semiconductor layer such that at least a portion thereof overlaps with the light-blocking film.
    Type: Grant
    Filed: December 4, 2009
    Date of Patent: July 9, 2013
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Kenshi Tada
  • Patent number: 8466451
    Abstract: A FET inverter is provided that includes a plurality of device layers oriented vertically in a stack, each device layer having a source region, a drain region and a plurality of nanowire channels, wherein the source and drain regions of one or more of the device layers are doped with an n-type dopant and the source and drain regions of one or more other of the device layers are doped with a p-type dopant; a gate common to each of the device layers surrounding the nanowire channels; a first contact to the source regions of the one or more device layers doped with an n-type dopant; a second contact to the source regions of the one or more device layers doped with a p-type dopant; and a third contact common to the drain regions of each of the device layers. Techniques for fabricating a FET inverter are also provided.
    Type: Grant
    Filed: December 11, 2011
    Date of Patent: June 18, 2013
    Assignee: International Business Machines Corporation
    Inventors: Josephine Chang, Paul Chang, Michael A. Guillorn, Jeffrey Sleight
  • Patent number: 8436427
    Abstract: The present invention, in one embodiment, provides a method of forming a semiconductor device that includes providing a substrate including a first conductivity type region and a second conductivity type region; forming a gate stack including a gate dielectric atop the first conductivity type region and the second conductivity type region of the substrate and a first metal gate conductor overlying the high-k gate dielectric; removing a portion of the first metal gate conductor that is present in the first conductivity type region to expose the gate dielectric present in the first conductivity type region; applying a nitrogen based plasma to the substrate, wherein the nitrogen based plasma nitrides the gate dielectric that is present in the first conductivity type region and nitrides the first metal gate conductor that is present in the second conductivity type region; and forming a second metal gate conductor overlying at least the gate dielectric that is present in the first conductivity type region.
    Type: Grant
    Filed: April 6, 2011
    Date of Patent: May 7, 2013
    Assignee: International Business Machines Corporation
    Inventors: Michael P. Chudzik, Wiliam K. Henson, Rashmi Jha, Yue Liang, Ravikumar Ramachandran, Richard S. Wise
  • Patent number: 8404507
    Abstract: A TFT-LCD array substrate and a manufacturing method thereof. The array substrate comprises a gate line, a data line, and a pixel electrode, and the pixel electrode is disposed in a pixel region defined by the intersection between the gate line and the data line. In the pixel region, a partition groove for forming a pixel electrode pattern is provided at the periphery of the pixel electrode. This structure is helpful to form a pixel electrode pattern by a lift-off process, which significantly reduces the production cost and improves the production yield.
    Type: Grant
    Filed: June 24, 2009
    Date of Patent: March 26, 2013
    Assignee: Beijing Boe Optoelectronics Technology Co., Ltd.
    Inventors: Hongxi Xiao, Jae Yun Jung, Zuhong Liu, Taek Ho Hong, Jeong Hun Rhee
  • Patent number: 8399927
    Abstract: A first field effect transistor includes a gate dielectric and a gate electrode located over a first portion of a top semiconductor layer in a semiconductor-on-insulator (SOI) substrate. A second field effect transistor includes a portion of a buried insulator layer and a source region and a drain region located underneath the buried insulator layer. In one embodiment, the gate electrode of the second field effect transistor is a remaining portion of the top semiconductor layer. In another embodiment, the gate electrode of the second field effect transistor is formed concurrently with the gate electrode of the first field effect transistor by deposition and patterning of a gate electrode layer. The first field effect transistor may be a high performance device and the second field effect transistor may be a high voltage device. A design structure for the semiconductor structure is also provided.
    Type: Grant
    Filed: February 7, 2012
    Date of Patent: March 19, 2013
    Assignee: International Business Machines Corporation
    Inventors: Hanyi Ding, Kai D. Feng, Zhong-Xiang He, Zhenrong Jin, Xuefeng Liu, Yun Shi
  • Patent number: 8288799
    Abstract: A thin film field effect transistor is disclosed which provides improved time-based channel stability. The field effect transistor includes first and second disordered semiconductor layers separated by an insulator. In an embodiment a carrier injection terminal is provided in a thin semiconductor layer closest to the gate terminal. An electric field is established in the thin semiconductor layer. At sufficient field strength, the electric field extends into the second semiconductor layer, which is in contact with the source and drain terminals. At sufficient field strength a channel is established in the second semiconductor layer, permitting current to flow between source and drain terminals. Above a certain gate voltage, there is sufficient free charge is induced in the first semiconductor layer so that the field does not extend into the second semiconductor, effectively shutting off current between source and drain. Single-device transition detection (as well as other applications) may be obtained.
    Type: Grant
    Filed: March 21, 2012
    Date of Patent: October 16, 2012
    Assignee: Palo Alto Research Center Incorporated
    Inventors: Sanjiv Sambandan, Ana Claudia Arias, Gregory Lewis Whiting
  • Patent number: 8283703
    Abstract: A solid state Klystron structure is fabricated by forming a source contact and a drain contact to both ends of a conducting wire and by forming a bias gate and a signal gate on the conducting wire. The conducting wire may be at least one carbon nanotube or at least one semiconductor wire with long ballistic mean free paths. By applying a signal at a frequency that corresponds to an integer multiple of the transit time of the ballistic carriers between adjacent fingers of the signal gate, the carriers are bunched within the conducting wire, thus amplifying the current through the solid state Klystron at a frequency of the signal to the signal gate, thus achieving a power gain.
    Type: Grant
    Filed: October 11, 2007
    Date of Patent: October 9, 2012
    Assignee: International Business Machines Corporation
    Inventor: Paul M. Solomon
  • Patent number: 8207582
    Abstract: Semiconductor devices including dual gate structures and methods of forming such semiconductor devices are disclosed. For example, semiconductor devices are disclosed that include a first gate stack that may include a first conductive gate structure formed from a first material, and a second gate stack that may include a dielectric structure formed from an oxide of the first material. For another example, methods including forming a high-K dielectric material layer over a semiconductor substrate, forming a first conductive material layer over the high-K dielectric material layer, oxidizing a portion of the first conductive material layer to convert the portion of the first conductive material layer to a dielectric material layer, and forming a second conductive material layer over both the conductive material layer and the dielectric material layer are also disclosed.
    Type: Grant
    Filed: January 5, 2009
    Date of Patent: June 26, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Jaydeb Goswami
  • Patent number: 8188482
    Abstract: One aspect includes a semiconductor device with self-aligned contacts, integrated circuit and manufacturing method. One embodiment provides gate control structures. Each of the gate control structures is configured to control the conductivity of a channel region within a silicon carbide substrate by field effect. A contact hole is self-aligned to opposing sidewalls of adjacent gate control structures by intermediate spacers.
    Type: Grant
    Filed: December 22, 2008
    Date of Patent: May 29, 2012
    Assignee: Infineon Technologies Austria AG
    Inventors: Michael Treu, Kathrin Rueschenschmidt, Oliver Haeberlen, Franz Auerbach
  • Patent number: 8183116
    Abstract: A planar double-gate transistor is manufactured wherein crystallisation inhibitors are implanted into the channel region (16) of a semiconductor wafer (10), said wafer having a laminate structure comprising an initial crystalline semiconductor layer (14) adjacent an amorphous semiconductor layer (12). Upon heating, partial re-growth of the amorphous semiconductor layer is restricted in the channel area thus allowing for the thickness of the source/drain extension regions to be increased whilst maintaining a thin channel. Any remaining amorphous material is selectively removed leaving a cavity to allow for the forming of gate electrodes (30,32) on opposing sides of the channel region. The invention can be exploited to a greater extent by providing an amorphous layer on both sides of the initial crystalline semiconductor layer thus providing for re-growth limitation in two directions.
    Type: Grant
    Filed: August 1, 2007
    Date of Patent: May 22, 2012
    Assignee: NXP B.V.
    Inventor: Bartlomiej J. Pawlak
  • Patent number: 8164122
    Abstract: A thin film field effect transistor is disclosed which provides improved time-based channel stability. The field effect transistor includes first and second disordered semiconductor layers separated by an insulator. In an embodiment a carrier injection terminal is provided in a thin semiconductor layer closest to the gate terminal. An electric field is established in the thin semiconductor layer. At sufficient field strength, the electric field extends into the second semiconductor layer, which is in contact with the source and drain terminals. At sufficient field strength a channel is established in the second semiconductor layer, permitting current to flow between source and drain terminals. Above a certain gate voltage, there is sufficient free charge is induced in the first semiconductor layer so that the field does not extend into the second semiconductor, effectively shutting off current between source and drain. Single-device transition detection (as well as other applications) may be obtained.
    Type: Grant
    Filed: September 21, 2011
    Date of Patent: April 24, 2012
    Assignee: Palo Alto Research Center Incorporated
    Inventors: Sanjiv Sambandan, Ana Claudia Arias, Gregory Lewis Whiting
  • Patent number: 8164121
    Abstract: A six-phase charge coupled device (CCD) pixel includes a pixel pair, with each pixel having two adjacent control gates overlying corresponding variable potential wells, where voltages applied to the control gates enable charge to be accumulated into and transferred out of the wells. A clear window region overlies a fixed potential gradient region, decreasing in potential away from the control gates. This region enables a wide band of photons to be sensed by the photosensitive silicon of the CCD. The decreasing potential levels facilitate high charge transfer efficiency (i.e., high CTE) from pixel to pixel via the control or transfer gates. By applying particular voltages to the control gates, charge can be quickly and efficiently transferred between pixels.
    Type: Grant
    Filed: May 14, 2010
    Date of Patent: April 24, 2012
    Assignee: Imagerlabs
    Inventor: Mark Wadsworth
  • Patent number: 8089128
    Abstract: A transistor gate forming method includes forming a first and a second transistor gate. Each of the two gates includes a lower metal layer and an upper metal layer. The lower metal layer of the first gate originates from an as-deposited material exhibiting a work function the same as exhibited in an as-deposited material from which the lower metal layer of the second gate originates. However, the first gate's lower metal layer exhibits a modified work function different from a work function exhibited by the second gate's lower metal layer. The first gate's lower metal layer may contain less oxygen and/or carbon in comparison to the second gate's lower metal layer. The first gate's lower metal layer may contain more nitrogen in comparison to the second gate's lower metal layer. The first gate may be a n-channel gate and the second gate may be a p-channel gate.
    Type: Grant
    Filed: April 15, 2009
    Date of Patent: January 3, 2012
    Assignee: Micron Technology, Inc.
    Inventors: D. V. Nirmal Ramaswamy, Ravi Iyer