Employing Resonant Tunneling Patents (Class 257/25)
  • Patent number: 11127850
    Abstract: A semiconductor device includes a first conductivity type semiconductor layer including an active cell portion and an outer peripheral portion around the active cell portion, a second conductivity type body region selectively formed at a surface portion of the semiconductor layer in the active cell portion, a first conductivity type source region formed at an inner part of the body region, a gate electrode that faces a part of the body region through a gate insulating film, a second conductivity type column layer straddling a boundary between the active cell portion and the outer peripheral portion inside the semiconductor layer such that the column layer is disposed at a lower part of the body region in the active cell portion, a source electrode that is electrically connected to the source region, and an outer peripheral electrode that is electrically connected to the column layer in the outer peripheral portion.
    Type: Grant
    Filed: January 25, 2018
    Date of Patent: September 21, 2021
    Assignee: ROHM CO., LTD.
    Inventor: Yusuke Kubo
  • Patent number: 11061647
    Abstract: A device for generating a nondeterministic response to a challenge, the device comprising: a structure that exhibits a nondeterministic electrical output response to an electrical input, the device being arranged to facilitate a challenge of the structure to generate the nondeterministic response, by facilitating an electrical measurement of an output of the structure, the nondeterministic response being derivable from that measurement.
    Type: Grant
    Filed: July 24, 2017
    Date of Patent: July 13, 2021
    Assignee: QUANTUM BASE LIMITED
    Inventors: Ramon Bernardo Gavito, Robert James Young
  • Patent number: 10923335
    Abstract: Systems and methods for loading microfabricated ion traps are disclosed. Photo-ablation via an ablation pulse is used to generate a flow of atoms from a source material, where the flow is predominantly populated with neutral atoms. As the neutral atoms flow toward the ion trap, two-photon photo-ionization is used to selectively ionize a specific isotope contained in the atom flow. The velocity of the liberated atoms, atom-generation rate, and/or heat load of the source material is controlled by controlling the fluence of the ablation pulse to provide high ion-trapping probability while simultaneously mitigating generation of heat in the ion-trapping system that can preclude cryogenic operation. In some embodiments, the source material is held within an ablation oven comprising an electrically conductive housing that is configured to restrict the flow of agglomerated neutral atoms generated during photo-ablation toward the ion trap.
    Type: Grant
    Filed: March 19, 2019
    Date of Patent: February 16, 2021
    Assignee: Duke University
    Inventors: Geert Vrijsen, Jungsang Kim, Robert Spivey, Ismail Inlek, Yuhi Aikyo
  • Patent number: 10916645
    Abstract: A compound semiconductor device includes: a compound semiconductor area including, at an upper most portion, a protective layer made of a compound semiconductor; and an ohmic electrode provided on the compound semiconductor area, the ohmic electrode being away from the protective layer in plan view and being not in contact with the protective layer.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: February 9, 2021
    Assignee: FUJITSU LIMITED
    Inventor: Kozo Makiyama
  • Patent number: 10854735
    Abstract: According to another embodiment, a method of forming a transistor is provided. The method includes the following operations: providing a substrate; providing a source over the substrate; providing a channel connected to the source; providing a drain connected to the channel; providing a gate insulator adjacent to the channel; providing a gate adjacent to the gate insulator; providing a first interlayer dielectric between the source and the gate; and providing a second interlayer dielectric between the drain and the gate, wherein at least one of the formation of the source, the drain, and the channel includes about 20-95 atomic percent of Sn.
    Type: Grant
    Filed: September 3, 2014
    Date of Patent: December 1, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Jean-Pierre Colinge, Carlos H. Diaz
  • Patent number: 10733524
    Abstract: A quantum computing D-state AC-Stark shift gate system comprises at least one gate manipulation source and one or more ions trapped in an ion trap. The at least one gate manipulation source is configured to generate a first gate manipulation signal and a second gate manipulation signal. The first and second gate manipulation signals couple an ion between a set of S-states and a set of D-states. The first and second gate manipulation signals apply a force to an ion of the one or more ions that is dependent on the internal state of the ion. The first and second gate manipulation signals are configured to couple internal states of the ions to their motional state without appreciably altering a population of the ions within the set of S-states.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: August 4, 2020
    Assignee: Honeywell International Inc.
    Inventors: Michael Feig, Jonathon Sedlacek, Mark Kokish, Christopher Langer, John Gaebler, Daniel Stack, Bryce J. Bjork, Grahame Vittorini, David Hayes
  • Patent number: 10600761
    Abstract: A microelectronic assembly including an insulating layer having a plurality of nanoscale conductors disposed in a nanoscale pitch array therein and a pair of microelectronic elements is provided. The nanoscale conductors can form electrical interconnections between contacts of the microelectronic elements while the insulating layer can mechanically couple the microelectronic elements together.
    Type: Grant
    Filed: April 9, 2019
    Date of Patent: March 24, 2020
    Assignee: Invensas Corporation
    Inventors: Liang Wang, Bongsub Lee, Belgacem Haba, Sangil Lee
  • Patent number: 10504882
    Abstract: Provided are optical devices and systems fabricated, at least in part, via printing-based assembly and integration of device components. In specific embodiments the present invention provides light emitting systems, light collecting systems, light sensing systems and photovoltaic systems comprising printable semiconductor elements, including large area, high performance macroelectronic devices. Optical systems of the present invention comprise semiconductor elements assembled, organized and/or integrated with other device components via printing techniques that exhibit performance characteristics and functionality comparable to single crystalline semiconductor based devices fabricated using conventional high temperature processing methods. Optical systems of the present invention have device geometries and configurations, such as form factors, component densities, and component positions, accessed by printing that provide a range of useful device functionalities.
    Type: Grant
    Filed: January 10, 2017
    Date of Patent: December 10, 2019
    Assignees: The Board of Trustees of the University of Illinois, X-Celeprint Limited
    Inventors: John Rogers, Ralph Nuzzo, Matthew Meitl, Etienne Menard, Alfred Baca, Michael Motala, Jong-Hyun Ahn, Sang-Il Park, Chang-Jae Yu, Heung Cho Ko, Mark Stoykovich, Jongseung Yoon
  • Patent number: 10461388
    Abstract: Radio frequency (RF) data transfer between components in rack mounted systems is facilitated through the use of dielectric waveguides and millimeter Wave (mm-Wave) transceivers. A signal generator provides one or more data signals to a serializer/deserializer (SERDES) which serializes a plurality of parallel data signals to produce a single, serialized, signal containing data from each of the input signals to the SERDES. A mm-Wave die upconverts the serialized signal to a mm-Wave signal and a mm-Wave launcher launches the signal into the dielectric waveguide. At the receiving end the process is reversed such that the mm-Wave signal is first downconverted and passed through a SERDES to provide the original one or more signals to a recipient signal generator. Some or all of the components may be formed directly in the semiconductor package.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: October 29, 2019
    Assignee: INTEL CORPORATION
    Inventors: Telesphor Kamgaing, Georgios C. Dogiamis, Sasha N. Oster
  • Patent number: 10388375
    Abstract: A memory cell includes a first resistive memory element, a second resistive memory element electrically coupled with the first resistive memory element at a common node, and a switching element comprising an input terminal electrically coupled with the common node, the switching element comprising a driver configured to float during one or more operations.
    Type: Grant
    Filed: April 9, 2018
    Date of Patent: August 20, 2019
    Assignee: Hefei Reliance Memory Limited
    Inventors: Deepak Chandra Sekar, Gary Bela Bronner, Frederick A. Ware
  • Patent number: 10381456
    Abstract: An enhancement-mode High Electron Mobility Transistor (HEMT) includes a substrate, a Group IIIA-N active layer on the substrate, a Group IIIA-N barrier layer on the active layer, and at least one isolation region through the barrier layer to provide an isolated active area having the barrier layer on the active layer. A p-GaN layer is on the barrier layer. A tunnel diode in the gate stack includes an n-GaN layer on an InGaN layer on the p-GaN layer. A gate electrode is over the n-GaN layer. A drain having a drain contact is on the barrier layer to provide contact to the active layer, and a source having a source contact is on the barrier layer provides contact to the active layer. The tunnel diode provides a gate contact to eliminate the need to form a gate contact directly to the p-GaN layer.
    Type: Grant
    Filed: May 4, 2017
    Date of Patent: August 13, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Chang Soo Suh, Dong Seup Lee, Jungwoo Joh, Naveen Tipirneni, Sameer Prakash Pendharkar
  • Patent number: 10304803
    Abstract: A microelectronic assembly including an insulating layer having a plurality of nanoscale conductors disposed in a nanoscale pitch array therein and a pair of microelectronic elements is provided. The nanoscale conductors can form electrical interconnections between contacts of the microelectronic elements while the insulating layer can mechanically couple the microelectronic elements together.
    Type: Grant
    Filed: May 5, 2016
    Date of Patent: May 28, 2019
    Assignee: Invensas Corporation
    Inventors: Liang Wang, Bongsub Lee, Belgacem Haba, Sangil Lee
  • Patent number: 10122420
    Abstract: Apparatus and methods are provided for wireless communications between integrated circuits or integrated circuit dies of an electronic system. In an example, an apparatus can include a first integrated circuit die including a plurality of integrated circuit devices, a second integrated circuit die including a second plurality of integrated circuit devices, and a conductor device configured to wirelessly receive a signal from the first integrated circuit die, to conduct the signal from a first end of an electrical conductor of the conductor device to a second end of the electrical conductor, and to wirelessly transmit the signal to the second integrated circuit die from the second end of the electrical conductor.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: November 6, 2018
    Assignee: Intel IP Corporation
    Inventors: Thorsten Meyer, Andreas Augustin, Reinhard Golly, Peter Baumgartner
  • Patent number: 10026888
    Abstract: According to one embodiment, a magnetoresistive effect element includes: a first magnetic layer; a second magnetic layer; a non-magnetic film between the first magnetic layer and the second magnetic layer; a first layer on an opposite side of a side of the non-magnetic layer of the first magnetic layer, the first layer including magnesium oxide as a principal component; and a second layer between the first film and the first magnetic layer, the second layer including a material different from a material of the first layer.
    Type: Grant
    Filed: March 5, 2015
    Date of Patent: July 17, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Takao Ochiai, Eiji Kitagawa, Kenji Noma
  • Patent number: 9991385
    Abstract: The present disclosure relates to a semiconductor device that controls a strain on a channel region by forming a dielectric material in recesses, adjacent to a channel region, in order to provide control over a volume and shape of a strain inducing material of epitaxial source/drain regions formed within the recesses. In some embodiments, the semiconductor device has epitaxial source/drain regions arranged in recesses within an upper surface of a semiconductor body on opposing sides of a channel region. A gate structure is arranged over the channel region, and a dielectric material is arranged laterally between the epitaxial source/drain regions and the channel region. The dielectric material consumes some volume of the recesses, thereby reducing a volume of strain inducing material in epitaxial source/drain regions formed in the recesses.
    Type: Grant
    Filed: September 15, 2015
    Date of Patent: June 5, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tung-Wen Cheng, Che-Cheng Chang, Mu-Tsang Lin, Bo-Feng Young, Cheng-Yen Yu
  • Patent number: 9960183
    Abstract: A method of manufacturing a semiconductor device including: preparing a substrate in which an insulating layer, a semiconductor layer, and an insulating film are laminated on a semiconductor substrate, and a device isolation region is embedded in a trench. The insulating film in a bulk region is removed; the semiconductor layer in the bulk region is removed; and thereafter the insulating film in the SOI region and the insulating layer in the bulk region are thinned. An impurity is implanted into the semiconductor substrate in the SOI region, and thereafter the insulating film in the SOI region and the insulating layer in the bulk region are removed.
    Type: Grant
    Filed: May 24, 2017
    Date of Patent: May 1, 2018
    Assignee: Renesas Electronics Corporation
    Inventor: Hideki Makiyama
  • Patent number: 9960346
    Abstract: A magnetic tunnel junction has a conductive first magnetic electrode comprising magnetic recording material. A conductive second magnetic electrode is spaced from the first electrode and comprises magnetic reference material. A non-magnetic tunnel insulator material is between the first and second electrodes. The magnetic recording material of the first electrode comprises a first magnetic region, a second magnetic region spaced from the first magnetic region, and a third magnetic region spaced from the first and second magnetic regions. A first non-magnetic insulator metal oxide-comprising region is between the first and second magnetic regions. A second non-magnetic insulator metal oxide-comprising region is between the second and third magnetic regions. Other embodiments are disclosed.
    Type: Grant
    Filed: May 7, 2015
    Date of Patent: May 1, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Jonathan D. Harms, Wei Chen, Sunil S. Murthy, Witold Kula
  • Patent number: 9954077
    Abstract: A method comprises etching away an upper portion of a substrate to form a trench between two adjacent isolation regions, wherein the substrate has a first crystal orientation and is formed of a first semiconductor material, growing a first semiconductor region in the trench over the substrate, wherein the first semiconductor region is formed of a second semiconductor material and an upper portion of the first semiconductor region has a second crystal orientation and growing a second semiconductor region over the first semiconductor region, wherein the second semiconductor region is formed of a third semiconductor material.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: April 24, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Georgios Vellianitis
  • Patent number: 9871014
    Abstract: 3D joining of microelectronic components and a conductively self-adjusting anisotropic matrix are provided. In an implementation, an adhesive matrix automatically makes electrical connections between two surfaces that have electrical contacts, and bonds the two surfaces together. Conductive members in the adhesive matrix are aligned to automatically establish electrical connections between at least partially aligned contacts on each of the two surfaces while providing nonconductive adhesion between parts of the two surfaces lacking aligned contacts. An example method includes forming an adhesive matrix between two surfaces to be joined, including conductive members anisotropically aligned in an adhesive medium, then pressing the two surfaces together to automatically connect corresponding electrical contacts that are at least partially aligned on the two surfaces. The adhesive medium in the matrix secures the two surfaces together.
    Type: Grant
    Filed: September 6, 2016
    Date of Patent: January 16, 2018
    Assignee: Invensas Corporation
    Inventor: Belgacem Haba
  • Patent number: 9825348
    Abstract: A signal transmission system including: a first connector apparatus, and a second connector apparatus that is coupled with the first connector apparatus. The first connector apparatus and the second connector apparatus are coupled together to form an electromagnetic field coupling unit, and a transmission object signal is converted into a radio signal, which is then transmitted through the electromagnetic field coupling unit, between the first connector apparatus and the second connector apparatus.
    Type: Grant
    Filed: March 29, 2016
    Date of Patent: November 21, 2017
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Hidekazu Kikuchi, Takayuki Mogi, Yoshiyuki Akiyama, Hirofumi Kawamura
  • Patent number: 9769923
    Abstract: Interposer circuitry (130) is formed on a possibly sacrificial substrate (210) from a porous core (130?) covered by a conductive coating (130?) which increases electrical conductance. The core is printed from nanoparticle ink. Then a support (120S) is formed, e.g. by molding, to mechanically stabilize the circuitry. A magnetic field can be used to stabilize the circuitry while the circuitry or the support are being formed. Other features are also provided.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: September 19, 2017
    Assignee: Invensas Corporation
    Inventors: Bong-Sub Lee, Cyprian Emeka Uzoh, Charles G. Woychik, Liang Wang, Laura Wills Mirkarimi, Arkalgud R. Sitaram
  • Patent number: 9716163
    Abstract: Provided is an electronic device including a semiconductor memory. The semiconductor memory includes first and second selecting elements coupled to a variable resistance element, and each of the first and second selecting elements includes a single-electron transistor.
    Type: Grant
    Filed: October 9, 2015
    Date of Patent: July 25, 2017
    Assignee: SK HYNIX INC.
    Inventor: Kyung-Wan Kim
  • Patent number: 9704780
    Abstract: A semiconductor device includes a semiconductor die. A first interconnect structure is disposed over a peripheral region of the semiconductor die. A semiconductor component is disposed over the semiconductor die. The semiconductor component includes a second interconnect structure. The semiconductor component is disposed over the semiconductor die to align the second interconnect structure with the first interconnect structure. The first interconnect structure includes a plurality of interconnection units disposed around first and second adjacent sides of the semiconductor die to form an L-shape border of the interconnection units around the semiconductor die. A third interconnect structure is formed over the semiconductor die perpendicular to the first interconnect structure. An insulating layer is formed over the semiconductor die and first interconnect structure.
    Type: Grant
    Filed: September 26, 2013
    Date of Patent: July 11, 2017
    Assignee: STATS ChipPAC, Pte. Ltd.
    Inventors: Pandi C. Marimuthu, Il Kwon Shim, Yaojian Lin, Won Kyoung Choi
  • Patent number: 9630849
    Abstract: A method for transferring a carbon nanotube array is disclosed. The carbon nanotube array has an ability to have a carbon nanotube structure drawn therefrom. The carbon nanotube array is transferred from a growing substrate to a substitute substrate, meanwhile the carbon nanotube array is still configured for drawing the carbon nanotube structure from the substitute substrate. A coating layer is formed on a top end of a carbon nanotube in the carbon nanotube array. The top end is away from the growing substrate. The substitute substrate is placed on the carbon nanotube array and contacted with the coating layer. Thereby the substitute substrate is combined with the carbon nanotube array by the coating layer. The substitute substrate is separated from the growing substrate. Thereby the carbon nanotube array is separated from the growing substrate. A method for making a carbon nanotube structure is also disclosed.
    Type: Grant
    Filed: October 22, 2014
    Date of Patent: April 25, 2017
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Yang Wei, Shou-Shan Fan
  • Patent number: 9482477
    Abstract: A thermal interface material (TIM) using high thermal conductivity nano-particles, particularly ones with large aspect ratios, for enhancing thermal transport across boundary or interfacial layers that exist at bulk material interfaces is disclosed. The nanoparticles do not need to be used in a fluid carrier or as filler material within a bonding adhesive to enhance thermal transport, but simply in a dry solid state. The nanoparticles may be equiaxed or acicular in shape with large aspect ratios like nanorods and nanowires.
    Type: Grant
    Filed: July 28, 2014
    Date of Patent: November 1, 2016
    Assignee: Northrop Grumman Systems Corporation
    Inventors: John A. Starkovich, Jesse B. Tice, Edward M. Silverman, Hsiao H. Peng
  • Patent number: 9417387
    Abstract: A signal transfer link includes a first plasmonic coupler, and a second plasmonic coupler spaced apart from the first plasmonic coupler to form a gap. An insulator layer is formed over end portions of the first and second plasmonic couplers and in and over the gap. A plasmonic conductive layer is formed over the gap on the insulator layer to excite plasmons to provide signal transmission between the first and second plasmonic couplers.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: August 16, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Phaedon Avouris, Vasili Perebeinos, Mathias B. Steiner, Alberto Valdes Garcia
  • Patent number: 9335471
    Abstract: A signal transfer link includes a first plasmonic coupler, and a second plasmonic coupler spaced apart from the first plasmonic coupler to form a gap. An insulator layer is formed over end portions of the first and second plasmonic couplers and in and over the gap. A plasmonic conductive layer is formed over the gap on the insulator layer to excite plasmons to provide signal transmission between the first and second plasmonic couplers.
    Type: Grant
    Filed: August 7, 2015
    Date of Patent: May 10, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Phaedon Avouris, Vasili Perebeinos, Mathias B. Steiner, Alberto Valdes Garcia
  • Patent number: 9331700
    Abstract: A metal-insulator phase transition (MIT) flip-flop employs a selected one of a pair of bi-stable operating states to represent a logic state of the MIT flip-flop. The MIT flip-flop includes an MIT device having a current-controlled negative differential resistance (CC-NDR) to provide the pair of bi-stable operating states. A bi-stable operating state of the pair is capable of being selected by a programing voltage. Once the bi-stable operating state is selected, the bi-stable operating state is capable of being maintained by a bias voltage applied to the MIT device.
    Type: Grant
    Filed: October 28, 2011
    Date of Patent: May 3, 2016
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Gilberto M. Ribeiro, Matthew D. Pickett
  • Patent number: 9274297
    Abstract: The system (200) provides a photonic waveguide (210) formed on a substrate (220) and a plurality of steering mirrors (230) within the photonic waveguide. The steering mirrors can be configured to direct a light beam (240) between two or more computing components (260). A plurality of steering mirror supports (250) are located within the waveguide having preset locations. The steering mirror supports are configured to enable the steering mirrors to be selectively repositioned at the preset steering mirror supports within the photonic waveguide to create varying configurations. The steering mirrors in the varying configurations direct one or more optical beams to form multiple connectivity channels between computing components within the photonic waveguide.
    Type: Grant
    Filed: January 7, 2009
    Date of Patent: March 1, 2016
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Terrel Morris, Gary Gostin, Eric Peterson
  • Patent number: 9252281
    Abstract: A monolayer or partial monolayer sequencing processing, such as atomic layer deposition (ALD), can be used to form a semiconductor structure of a silicon film on a germanium substrate. Such structures may be useful in high performance electronic devices. A structure may be formed by deposition of a thin silicon layer on a germanium substrate surface, forming a hafnium oxide dielectric layer, and forming a tantalum nitride electrode. The properties of the dielectric may be varied by replacing the hafnium oxide with another dielectric such as zirconium oxide or titanium oxide.
    Type: Grant
    Filed: May 28, 2014
    Date of Patent: February 2, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Patent number: 9252329
    Abstract: Light emitting devices having an enhanced degree of polarization, PD, and methods for fabricating such devices are described. A light emitting device may include a light emitting region that is configured to emit light having a central wavelength, ?, and a degree of polarization, PD, where PD>0.006??b for 200 nm???400 nm, wherein b?1.5.
    Type: Grant
    Filed: December 16, 2011
    Date of Patent: February 2, 2016
    Assignee: PALO ALTO RESEARCH CENTER INCORPORATED
    Inventors: John E. Northrup, Christopher Chua, Michael Kneissl, Thomas Wunderer, Noble M. Johnson
  • Patent number: 9240421
    Abstract: A display panel is discloses. A gate line and a gate connection line of an array substrate are disposed perpendicular to each other. A passivation layer is formed on a side of a source electrode or a drain electrode of the array substrate which is close to the color filter substrate. A first via hole is disposed in the passivation layer. A color filter substrate includes a first substrate, and a data line parallel to the gate connection line is formed on a side of the first substrate which is close to the array substrate. A protection layer, a black matrix and a common electrode are sequentially formed on a side of the data line which is close to the array substrate. A second via hole is disposed in a region of the protection layer, the black matrix and the common electrode which corresponds to the data line.
    Type: Grant
    Filed: November 27, 2013
    Date of Patent: January 19, 2016
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Fan Li
  • Patent number: 9224847
    Abstract: A High Electron Mobility Transistor (HEMT) includes a first III-V compound layer having a first band gap, and a second III-V compound layer having a second band gap over the first III-V compound layer. The second band gap is greater than the first band gap. A crystalline interfacial layer is overlying and in contact with the second III-V compound layer. A gate dielectric is over the crystalline interfacial layer. A gate electrode is over the gate dielectric. A source region and a drain region are over the second III-V compound layer, and are on opposite sides of the gate electrode.
    Type: Grant
    Filed: July 11, 2014
    Date of Patent: December 29, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Han-Chin Chiu, Po-Chun Liu, Chi-Ming Chen, Chung-Yi Yu, King-Yuen Wong
  • Patent number: 9184266
    Abstract: A transistor device having a graphene base for the transport of electrons into a collector is provided. The transistor consists of a heterostructure comprising an electron emitter, an electron collector, and a graphene material base layer consisting of one or more sheets of graphene situated between the emitter and the collector. The transistor also can further include an emitter transition layer at the emitter interface with the base and/or a collector transition layer at the base interface with the collector. The electrons injected into the graphene material base layer can be “hot electrons” having an energy E substantially greater than EF, the Fermi energy in the graphene material base layer or can be “non-hot electrons” having an energy E approximately equal to than EF. The electrons can have the properties of ballistic transit through the base layer.
    Type: Grant
    Filed: September 19, 2014
    Date of Patent: November 10, 2015
    Assignee: The United States of America, as represented by the Secretary of the Navy
    Inventor: Francis J. Kub
  • Patent number: 9134481
    Abstract: A signal transfer link includes a first plasmonic coupler, and a second plasmonic coupler spaced apart from the first plasmonic coupler to form a gap. An insulator layer is formed over end portions of the first and second plasmonic couplers and in and over the gap. A plasmonic conductive layer is formed over the gap on the insulator layer to excite plasmons to provide signal transmission between the first and second plasmonic couplers.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: September 15, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Phaedon Avouris, Vasili Perebeinos, Mathias B. Steiner, Alberto Valdes Garcia
  • Patent number: 9117753
    Abstract: According to one aspect of the inventive concept there is provided a process for manufacturing a semiconductor device, comprising: providing a channel layer (104), providing a mask (106) on the channel layer, epitaxially growing a contact layer (108) in contact with the channel layer, epitaxially growing a support layer (110) on the contact layer, wherein the support layer is arranged to be etched at a higher rate than the contact layer, forming a trench extending through the support layer by removing the mask, and providing a conductor (118) in the trench. There is also provided an intermediate product for the manufacture of a semiconductor device.
    Type: Grant
    Filed: June 1, 2012
    Date of Patent: August 25, 2015
    Assignee: Acconeer AB
    Inventors: Mikael Egard, Erik Lind, Lars-Erik Wernersson
  • Patent number: 9087717
    Abstract: Device structures, fabrication methods, and design structures for tunnel field-effect transistors. A drain comprised of a first semiconductor material having a first band gap and a source comprised of a second semiconductor material having a second band gap are formed. A tunnel barrier is formed between the source and the drain. The second semiconductor material exhibits a broken-gap energy band alignment with the first semiconductor material. The tunnel barrier is comprised of a third semiconductor material with a third band gap larger than the first band gap and larger than the second band gap. The third band gap is configured to bend under an external bias to assist in aligning a first energy band of the first semiconductor material with a second energy band of the second semiconductor material.
    Type: Grant
    Filed: November 26, 2014
    Date of Patent: July 21, 2015
    Assignee: International Business Machines Corporation
    Inventors: Douglas M. Daley, Hung H. Tran, Wayne H. Woods, Jr., Ze Zhang
  • Patent number: 9059265
    Abstract: A graphene device having a ribbon structure with soft boundaries formed between two thin parallel transport barriers in a “railroad track” configuration. Such a structure permits transport along the ribbon, and also permits transport of electrons across the barriers by means of resonant tunneling through quasi-bound states within the railroad track confinement. The transport barriers can be of any form of so long as transport through the barriers leads to the formation of isolated resonant bands with a transport gap. In some embodiments, the transport barriers can be in the form of a pair of parallel line defects, wherein the line defects delineate the central ribbon section and the two lateral sections. In some such embodiments, the line defects are chemically decorated by the adsorption of diatomic gases. In other embodiments, the transport barriers can be formed by the application of large local potentials directly to the graphene sheet.
    Type: Grant
    Filed: December 6, 2013
    Date of Patent: June 16, 2015
    Assignee: The United States of America, as represented by the Secretary of the Navy
    Inventors: L. Daniel Gunlycke, Carter T. White
  • Patent number: 9040958
    Abstract: Transistors, and methods of manufacturing the transistors, include graphene and a material converted from graphene. The transistor may include a channel layer including graphene and a gate insulating layer including a material converted from graphene. The material converted from the graphene may be fluorinated graphene. The channel layer may include a patterned graphene region. The patterned graphene region may be defined by a region converted from graphene. A gate of the transistor may include graphene.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: May 26, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chang-seung Lee, Yong-sung Kim, Joo-ho Lee, Yong-seok Jung
  • Patent number: 8975618
    Abstract: A resonant tunneling device includes a first semiconductor material with an energy difference between valence and conduction bands of Eg1, and a second semiconductor material with an energy difference between valence and conduction bands of Eg2, wherein Eg1 and Eg2 are different from one another. The device further includes an energy selectively transmissive interface connecting the first and second semiconductor materials.
    Type: Grant
    Filed: March 30, 2011
    Date of Patent: March 10, 2015
    Assignee: Sharp Kabushiki Kaisha
    Inventors: James Andrew Robert Dimmock, Stephen Day, Matthias Kauer, Jonathan Heffernan
  • Publication number: 20150041762
    Abstract: A transistor device having a graphene base for the transport of electrons into a collector is provided. The transistor consists of a heterostructure comprising an electron emitter, an electron collector, and a graphene material base layer consisting of one or more sheets of graphene situated between the emitter and the collector. The transistor also can further include an emitter transition layer at the emitter interface with the base and/or a collector transition layer at the base interface with the collector. The electrons injected into the graphene material base layer can be “hot electrons” having an energy E substantially greater than EF, the Fermi energy in the graphene material base layer or can be “non-hot electrons” having an energy E approximately equal to than EF. The electrons can have the properties of ballistic transit through the base layer.
    Type: Application
    Filed: September 19, 2014
    Publication date: February 12, 2015
    Applicant: The Government of the United States of America, as represented by the Secretary of the Navy
    Inventor: Francis J. Kub
  • Publication number: 20150001469
    Abstract: Structures include a tunneling device disposed over first and second lattice-mismatched semiconductor materials. Process embodiments include forming tunneling devices over lattice-mismatched materials.
    Type: Application
    Filed: September 12, 2014
    Publication date: January 1, 2015
    Inventors: Zhiyuan Cheng, Calvin Sheen
  • Patent number: 8890111
    Abstract: A method for producing an emissive pixel screen includes forming an active pixel matrix along which an electrode forming layer runs and having pixels arranged according to a distribution, forming an anisotropic substrate that includes a set of light emitting diodes constituted by parallel nanowires and arranged in an insulating matrix transversely with respect to a substrate thickness and having a density higher than a density of the pixels irrespective of the pixel distribution, connecting the substrate to the active pixel matrix by connecting only sub-groups of the parallel nanowires by a first end to separate pixel electrodes defined in the electrode forming layer according to the distribution of the pixels in the matrix, and connecting the sub-groups, by another end, to a common electrode, and delimiting the sub-groups by rendering the nanowires of the substrate that are arranged between the sub-groups emissively inactive.
    Type: Grant
    Filed: October 19, 2010
    Date of Patent: November 18, 2014
    Assignee: Commissariat à l'énergie atomique et aux énergies alternatives
    Inventors: Francois Templier, Laurent Clavelier, Marc Rabarot
  • Patent number: 8890119
    Abstract: Vertically oriented nanowire transistors including semiconductor layers or gate electrodes having compositions that vary over a length of the transistor. In embodiments, transistor channel regions are compositionally graded, or layered along a length of the channel to induce strain, and/or include a high mobility injection layer. In embodiments, a gate electrode stack including a plurality of gate electrode materials is deposited to modulate the gate electrode work function along the gate length.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: November 18, 2014
    Assignee: Intel Corporation
    Inventors: Brian S. Doyle, Roza Kotlyar, Uday Shah, Charles C. Kuo
  • Patent number: 8860160
    Abstract: Structures include a tunneling device disposed over first and second lattice-mismatched semiconductor materials. Process embodiments include forming tunneling devices over lattice-mismatched materials.
    Type: Grant
    Filed: December 17, 2013
    Date of Patent: October 14, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Zhiyuan Cheng, Calvin Sheen
  • Patent number: 8785910
    Abstract: A thin film transistor, a display device including the same, and a method of manufacturing the display device, the thin film transistor including a substrate; a gate electrode on the substrate; a gate insulating layer on the gate electrode; a semiconductor layer on the gate insulating layer; and source/drain electrodes electrically connected with the semiconductor layer, wherein the gate electrode has a thickness of about 500 ? to about 1500 ? and the gate insulating layer has a thickness of about 1600 ? to about 2500 ?.
    Type: Grant
    Filed: December 2, 2010
    Date of Patent: July 22, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jong-Hyun Park, Chun-Gi You, Sun Park, Jin-Hee Kang, Yul-Kyu Lee
  • Patent number: 8742399
    Abstract: A quantum dot, which is an ultrafine grain, has a core-shell structure having a core portion and a shell portion protecting the core portion. The surface of the shell portion is covered with two kinds of surfactants, a hole-transporting surfactant and an electron-transporting surfactant, which are concurrently present. Moreover, the hole-transporting surfactant has a HOMO level which tunneling-resonates with the valence band of the quantum dot and the electron-transporting surfactant has a LUMO level which tunneling-resonates with the transfer band of the quantum dot. Thus, a nanograin material which has good carrier transport efficiency and is suitable for use in a photoelectric conversion device is achieved.
    Type: Grant
    Filed: March 26, 2012
    Date of Patent: June 3, 2014
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Koji Murayama
  • Patent number: 8686402
    Abstract: A TFET includes a source region (110, 210), a drain region (120, 220), a channel region (130, 230) between the source region and the drain region, and a gate region (140, 240) adjacent to the channel region. The source region contains a first compound semiconductor including a first Group III material and a first Group V material, and the channel region contains a second compound semiconductor including a second Group III material and a second Group V material. The drain region may contain a third compound semiconductor including a third Group III material and a third Group V material.
    Type: Grant
    Filed: September 2, 2011
    Date of Patent: April 1, 2014
    Inventors: Niti Goel, William Tsai, Jack Kavalieros
  • Patent number: 8603872
    Abstract: The field effect device comprises a sacrificial gate electrode having side walls covered by lateral spacers formed on a semiconductor material film. The source/drain electrodes are formed in the semiconductor material film and are arranged on each side of the gate electrode. A diffusion barrier element is implanted through the void left by the sacrificial gate so as to form a modified diffusion area underneath the lateral spacers. The modified diffusion area is an area where the mobility of the doping impurities is reduced compared with the source/drain electrodes.
    Type: Grant
    Filed: January 24, 2012
    Date of Patent: December 10, 2013
    Assignee: Commissariat a l'Energie Atomique et aux Energies Alternatives
    Inventors: Laurent Grenouillet, Yannick Le Tiec, Nicolas Posseme, Maud Vinet
  • Patent number: 8597964
    Abstract: A method for manufacturing a plurality of holders each being for an LED package structure includes steps: providing a base, pluralities of through holes being defined in the base to divide the base into a plurality of basic units; etching the base to form a dam at an upper surface of each of the basic units of the base; forming a first electrical portion and a second electrical portion on each basic unit of the base, the first electrical portion and the second electrical portion being separated and insulated from each other by the dam; providing a plurality of reflective cups each on a corresponding basic unit of the base, each of the reflective cups surrounding the corresponding dam; and cutting the base into the plurality of basic units along the through holes to form the plurality of holders.
    Type: Grant
    Filed: April 11, 2012
    Date of Patent: December 3, 2013
    Assignee: Advanced Optoelectronic Technology, Inc.
    Inventors: Chih-Hsun Ke, Ming-Ta Tsai, Chao-Hsiung Chang