Abstract: The present invention relates to radiation, preferably light emitting, devices with a high radiation emission efficiency and to fabricating these as small devices in an array of such devices. In one embodiment, the emitting devices can be placed in dense arrays. In another embodiment, outcoupling efficiency of the devices is improved, which leads to a reduced power consumption for a given radiation output power. In another embodiment, the speed of the radiation is increased, hence the serial bandwidth per optical channel is increased. The invention further relates to light emitting devices that exhibit uniform radiation emission characteristics.

Abstract: The semiconductor device of the present invention includes: particles or interface states for passing charge formed on a p-type silicon substrate via a barrier layer; and particles for holding charge formed above the charge-passing particles via another barrier layer. The charge-holding particles are different from the charge-passing particles in parameters such as the particle diameter, the capacitance, the electron affinity, and the sum of electron affinity and forbidden bandwidth, to attain swift charge injection and release as well as stable charge holding in the charge-holding particles.

Abstract: A magneto-resistive device and a magneto-resistive effect type storage device are provided, which have improved selectivity and output signals by controlling bias to be applied. Two resistive devices are connected in series, and a magneto-resistive device is used for at least one of the resistive devices. When both of the resistive devices are magneto-resistive devices, their magnetic resistance should be controlled independently from each other, and by allowing the first magneto-resistive device to include a nonmagnetic substance of an electrical insulator and the second magneto-resistive device to include a nonmagnetic substance of a conductive substance, the second magneto-resistive device is operated as a bias control device for controlling the characteristics of the first magneto-resistive device so as to control the voltage to be applied to the storage device.

Abstract: The electron tunneling device includes first and second non-insulating layers spaced apart such that a given voltage can be provided therebetween. The device also includes an arrangement disposed between the non-insulating layers and configured to serve as a transport of electrons between the non-insulating layers. This arrangement includes a first layer of an amorphous material such that using only the first layer of amorphous material in the arrangement would result in a given value of a parameter in the transport of electrons, with respect to the given voltage. The arrangement further includes a second layer of material, which is configured to cooperate with the first layer of amorphous material such that the transport of electrons includes, at least in part, transport by tunneling, and such that the parameter, with respect to the given voltage, is increased above the given value of the parameter.

Abstract: An electronic transportor that allows for the resonant tunneling of electrons between guided states, such as those found in a quantum wire or a line defect in a solid, and localized states, such as those found in a quantum dot or a point defect in a solid, using lateral coupling. In some embodiments, the transporter allows electrons of different energies to be transported to different ports of associated waveguides. In other embodiments, the transportor allows electrons of different energies to be transported at different phases.

Abstract: The invention is a semiconductor optical device and a method of manufacture. The device includes a first waveguide having an edge, and a second waveguide adjacent to at least a portion of the first waveguide including the edge so that light is coupled from the first to the second waveguide. The second waveguide has a modal index which is essentially constant at least at the edge of the first waveguide. The method includes forming at least the second waveguide by Selective Area Growth (SAG) using oxide pads of a particular geometry to achieve the essentially constant modal index. In one embodiment, the device is an expanded beam laser with an expander portion which is less than 300 microns.

Abstract: The electron tunneling device includes first and second non-insulating layers spaced apart such that a given voltage can be provided therebetween. The device also includes an arrangement disposed between the non-insulating layers and configured to serve as a transport of electrons between the non-insulating layers. This arrangement includes a first layer of an amorphous material such that using only the first layer of amorphous material in the arrangement would result in a given value of a parameter in the transport of electrons, with respect to the given voltage. The arrangement further includes a second layer of material, which is configured to cooperate with the first layer of amorphous material such that the transport of electrons includes, at least in part, transport by tunneling, and such that the parameter, with respect to the given voltage, is increased above the given value of the parameter.

Abstract: A semiconductor quantum oscillation device, which realizes Bloch oscillation on the basis of a novel carrier injection scheme, comprises a multilayer semiconductor structure and a means for applying a voltage to said structure. The multilayer structure comprises a tunneling injection region and a pair of oscillation regions which are located on both sides of the tunneling injection region and adjacent to it. The voltage applied across the tunneling region and the pair of oscillation regions causes valence electrons to enter into the conduction band through interband tunneling in the tunneling injection region and leads to electrons and holes being injected into the pair of oscillation regions, respectively. The electrons and holes injected this way undergo quantum oscillation motion and produce far-infrared radiation. The device of the present invention will pave the way for effectively utilizing the electromagnetic spectral resource between the high-end of millimeter-wave and the low-end of far infrared.

Abstract: Provided are a semiconductor device which shows excellent negative differential conductance or negative transconductance and is manufactured without a complicated manufacturing process and a method of manufacturing the same. The semiconductor device includes a channel layer serving as a conduction region and a floating region electrically separated from the channel layer. Provided between the channel layer and the floating region is a quantum well layer constituted with a pair of barrier layers and a quantum well layer sandwiched between the pair of barrier layers. A source electrode and a drain electrode are electrically connected to the channel layer. A gate electrode is provided in an opposite position from the well layer in the floating region. When changing a drain voltage relative to a predetermined gate voltage, drain current characteristics show negative differential conductance.

Abstract: A nitride semiconductor laser device includes an n-type contact layer of n-type GaN and an n-type cladding layer of n-type Al0.35Ga0.65N formed on a substrate of sapphire. On the n-type cladding layer, a multiple quantum well active layer of Al0.2Ga0.8N/Al0.25Ga0.75N, a p-type leak barrier layer of p-type Al0.5Ga0.5N0.975P0.025 and a p-type cladding layer of p-type Al0.4Ga0.6N0.98P0.02 are successively formed. The p-type leak barrier layer has a wider energy gap than the n-type cladding layer, and the p-type leak barrier layer and the p-type cladding layer include phosphorus for making an acceptor level shallow with keeping a wide energy gap.

Abstract: A heterojunction bipolar transistor (HBT) having an emitter structure capable of reducing the current crowding effect and preventing thermal instabilities is disclosed, wherein a negative differential resistance. (NDR) element is added to the layer structure of the conventional emitter. In accordance with the invention, the NDR element can be implemented, for example, by a Resonant Tunnel Diode (RTD) or an Esaki Diode structure. The NDR element is designed to limit the tunneling current to the maximal emitter current density required for safe transistor operation, thereby also reducing the current crowding effect.

Abstract: An InP/InGaAlAs heterojunction bipolar transistor with the characteristics of amplification and negative-differential-resistance phenomenon is presented in the invention. The 3-terminal current-voltage characteristics of the heterojunction bipolar transistor can be controlled by the applied base current. In the large collector current regime, the heterojunction bipolar transistor has the characteristics as similar to conventional bipolar junction transistors. However, in a small collector current regime, both the transistor active region and negative-differential-resistance loci are observed. The negative-differential-resistance phenomenon is caused by the insertion of a thin base layer and a &dgr;-doped sheet. Moreover, the use of a setback layer with a thickness of 50 Å added at the emitter-base junction can suppress the diffusion of doping impurity in the base and reduce the potential spike at emitter-base heterojunction so as to improve the confinement of holes injected from base to emitter.

Abstract: An intersubband (ISB) optical device comprises first quantum well (QW) interior regions having upper and lower energy states between which ISB transitions take place; and superlattice (SL) barrier regions interposed between the first QW interior regions. The SL barrier regions include second barriers and second QW interior regions, with the second QW interior regions being interposed between the second barrier regions. The first QW interior regions and the SL barrier regions are configured to produce an energy gap between the upper and lower states that is larger than the energy of a 1.7 &mgr;m wavelength photon. In accordance with another aspect of our invention, an intersubband optical device comprises a core region that includes a multiplicity of repeat units (RUs), each RU including a first barrier region and a QW active region disposed adjacent thereto, characterized in that (1) each of the QWs has upper and lower energy states separated by an energy greater than that of a 1.

Abstract: A nonlinear coupling oscillator array is configured in such a manner that, for example, two layers in each of which a number of quantum dots as oscillators are arranged two-dimensionally are laid one on another. Adjacent quantum dots in the upper layer have tunnel coupling that exhibits a nonlinear current-voltage characteristic. The quantum dots in the upper layer receive an input of initial data/bias current, and each quantum dot in the upper layer is coupled with one quantum dot in the lower layer via a gate function having a time constant. Adjacent quantum dots in the lower layer do not interact with each other and the quantum dots in the lower layer are connected to the ground. For example, initial data are input by generating electron-hole pairs by applying light having an intensity profile corresponding to data, and injecting resulting electrons into the quantum dots of the upper layer.

Abstract: A tunnel diode has a quantum well having at least one layer of semiconductor material. The tunnel diode also has a pair of injection layers on either side of the quantum well. The injection layers comprise a collector layer and an emitter layer. A barrier layer is positioned between each of the injection layers and the quantum well. The quantum well has an epitaxial relationship with the emitter layer. An amount of one element of the well layer is increased to increase the lattice constant a predetermined amount. The lattice constant may have a reduction in the conduction band energy. A second element is added to the well layer to increase the conduction band energy but not to change the lattice constant. By controlling the composition in this matter, the negative resistance, and thus the effective mass, may be controlled for various diode constructions.

Abstract: According to the invention, a bidirectional semiconductor light emitting element is provided, which comprises: a first semiconductor region of a first type of conductivity; a second semiconductor region of a second type of conductivity provided on the first semiconductor region; a third semiconductor region of a first conductivity type provided on the second semiconductor region; and a semiconductor light emitting layer interposed in the second semiconductor region, the light emitting layer emitting light by an injection of a tunneling current generated at a reverse-biased p-n junction between the first and second regions or between the second and third regions under an application of a voltage of a first polarity across the first and third semiconductor regions, and the light emitting layer emitting light by an injection of a tunneling current generated at another reverse-biased p-n junction between the first and second regions or between the second and third regions under an application of a voltage of a se

Abstract: CMOS semiconductor latch and register (500) circuitry is disclosed, comprising a first tunneling structure latch circuit (502); data input circuitry (506), coupled and adapted to pass data to (504) said first tunneling structure latch circuit (502), a second tunneling structure latch circuit (514), data transmission circuitry (516), coupled between said first and second tunneling structure latch circuits, and adapted to transfer data from said first tunneling structure latch circuit to said second tunneling structure latch circuit, and data output circuitry (518), coupled to (512) said second tunneling structure latch circuit (514).

Abstract: The present invention provides a compact structure for the above-discussed SRAM cell as well as a method for fabricating the structure. The structure is preferably implemented in silicon. The standby power consumption of the cell is only approximately 0.5 nanowatts. The cell structure allows an SRAM cell to be fabricated in only a 16 feature-square area using planar technology. The structure of the cell according to one embodiment of the present invention is comprised of two bus bars of minimum feature size width, each of which has a tunnel diode implanted therein, and an elongated center land area (also of minimum feature size width) between the two bus bars. The transistor is constructed along the elongated center land area. In a preferred embodiment, transistors of neighboring cells share a common drain area and bit line contact. A corresponding method for fabricating the structure is also provided.

Abstract: A circuit device is disclosed comprising at least two circuit layers or circuit devices vertically interconnected with a plurality of parallel and substantially equi-length nanowires disposed therebetween. The nanowires may comprise composites, e.g., having a heterojunction present along the length thereof, to provide for a variety of device applications. Also disclosed is a method for making the circuit device comprising growing a plurality of nanowires on a dissolvable or removable substrate, equalizing the length of the nanowires (e.g., so that each one of the plurality of nanowires is substantially equal in length), transferring and bonding exposed ends of the plurality of nanowires to a first circuit layer; and removing the dissolvable substrate. The nanowires attached to the first circuit layer then can be further bonded to a second circuit layer to provide the vertically interconnected circuit device.

Abstract: A route to the fabrication of electronic devices is provided, in which the devices consist of two crossed wires sandwiching an electrically addressable molecular species. The approach is extremely simple and inexpensive to implement, and scales from wire dimensions of several micrometers down to nanometer-scale dimensions. The device of the present invention can be used to produce crossbar switch arrays, logic devices, memory devices, and communication and signal routing devices. The present invention enables construction of molecular electronic devices on a length scale than can range from micrometers to nanometers via a straightforward and inexpensive chemical assembly procedure. The device is either partially or completely chemically assembled, and the key to the scaling is that the location of the devices on the substrate are defined once the devices have been assembled, not prior to assembly.

Abstract: A variable capacity device having an nin, pip, nn−p, np−p, or nip junction whose middle layer is constituted by a quantum-wave interference layer with plural periods of a first layer W and a second layer B as a unit. The second layer B has a wider band gap than the first layer W. Each thickness of the first layer W and the second layer B is determined by multiplying by an odd number one fourth of a wavelength of a quantum-wave of carriers in each of the first layer W and the second layer B existing around the lowest energy level of the second layer B. A &dgr; layer, for changing energy band suddenly, is formed at interfaces between the first layer W and the second layer B and has a thickness substantially thinner than the first layer W and the second layer B. Plurality of quantum-wave interference units are formed sandwiching carrier accumulation layers in series. Then a voltage-variation rate of capacity of the variable capacity device is improved.

Abstract: The present invention relates to a semiconductor hetereostructure radiation detector for wavelengths in the infrared spectral range. The semiconductor heterostructure radiation detector is provided with an active layer composed of a multiplicity of periodically recurring single-layer systems each provided with a potential well structure having at least one quantum well with subbands (quantum well), the so-called excitation zone, which is connected on one side to a tunnel barrier zone, whose potential adjacent to the excitation zone is higher than the band-edge energy of a drift zone adjoining on the other side of the potential-well structure.

Abstract: A new switching element and a circuit device and the like using the same element are provided, which comprises semiconductor in which a channel region is formed at an interface with an insulating film, first and second terminals S, D, which are located in corresponding manner to both ends of the channel region, and through which a tunnel current is let to flow into the channel region, and a third terminal G giving a high frequency vibration to a potential barrier of the channel region through the insulating film, wherein the tunnel current flowing into the channel region is increased as a value of an exponential function is increased with a predetermined threshold vibration frequency as a boundary value.

Abstract: It is made possible to conduct writing and erasing information at high speed with a low gate voltage, to attain high integration with reduced power dissipation and to retain information accurately. A barrier layer, a transition layer, a barrier layer, a transition layer, a barrier layer, a charge accumulation layer and a barrier layer are stacked one after another on a conduction layer to cause transition of charges in the conduction layer to the charge accumulation layer by resonance tunneling. The conduction layer, the transition layers, and the charge accumulation layer are respectively made of Si. The barrier layers are respectively made of SiO2 so that electron affinity is made large and small alternately between those layers. Each capacitance respectively of the barrier layers is made smaller than e2/kBT so that charge transition does not occur according to the Coulomb blockade effect even if a voltage within a predetermined range is applied.

Abstract: Presented is an integrated asymmetric resonant tunneling diode pair circuit exhibiting current-voltage characteristics providing multistable states which may be tailored for multistable solutions. Also presented are apparatus incorporating the invention therein, for which the invention provides a simple, integrated design that greatly reduces circuit complexity and size. The present invention is useful in all applications utilizing multiple peak characteristics of the current-voltage curve, such as multiple-valued logic analog-to-digital quantizers, frequency multiplication devices, waveform scrambling devices, memory operations, and parity-bit generation, among others.

Abstract: A method/system for forming a resonant tunneling diode latch is disclosed. The method/system comprises the steps of forming a gate on a silicon substrate, the silicon substrate having at least one SOI layer disposed therein, providing an oxide spacer over the gate, providing a first ion implant in a first region of the silicon substrate, and then providing an oxide layer. The method further comprises polishing the oxide back to the gate, removing the gate, providing a second ion implant in a second region of the silicon substrate wherein the first and second regions have an undoped portion of silicon there between. According to the present invention, the method/system for forming a resonant tunneling diode latch in an SOI substrate that is easily implemented and results in an increased throughput of resonant tunneling diode devices.

Abstract: Disclosed is a photodetector adapted to be used with a voltage source for replacing the conventional CCD. The photodetector includes a substrate electrically connected with an electrode of the voltage source for generating electron-hole pairs in response to a light, a conducting layer electrically connected with the other electrode of the voltage source, and an ultra thin (˜nm) insulating layer formed between the conducting layer and the substrate, wherein one of electrons and holes, excited by the light, in the substrate will move to the conducting layer through the insulating layer so as to form a photo current when the voltage source provides a bias voltage.

Abstract: A method of forming a crystalline silicon well over a silicon oxide barrier layer, preferably for use in formation of a tunneling diode. A silicon substrate is provided of predetermined crystallographic orientation. A layer of crystallographic silicon oxide is formed over the silicon substrate and substantially matched to the crystallographic orientation of the silicon substrate. A layer of crystallographic silicon is formed over the silicon oxide layer substantially matched to the crystallographic orientation of the silicon oxide layer. The layer of silicon oxide is formed by the steps of placing the silicon substrate in a chamber having an oxygen ambient and heating the substrate to a temperature in the range of from about 650 to about 750 degrees C. at a pressure of from about 10−4 to about 10−7 until the silicon oxide layer has reached a predetermined thickness.

Abstract: A solid state electronic device exhibiting negative differential resistance is fabricated by depositing a thin layer of amorphous silicon on a single crystal substrate, doped N+. The amorphous silicon is simultaneously crystallized and oxidized in a dry N2 and O2 mixture. The result is a layer of amorphous SiO2 surrounding microclusters of crystalline silicon. A layer of polycrystalline silicon is deposited to a thickness of approximately 0.5 micron. Ohmic metal contacts are made to the top and bottom. These active layers are isolated by insulating SiO2. A bias voltage applied between the metal contacts results in negative differential resistance due to tunneling through resonant energy levels in microclusters.

Abstract: A resonant tunneling diode is produced in a gallium arsenide material system formed with barrier layers of AlGaAs with a quantum well layer of low band-gap material between them. The material of the well is selected to adjust the second energy level to the edge of the conduction band in GaAs, with a preferred quantum well layer formed of InGaAs. The resonant tunneling diode structure is grown by a metal organic chemical vapor deposition process on the surface of the nominally exact (100) GaAs substrate. Layers of doped GaAs may be formed on either side of the multilayer resonant tunneling diode structure, and spacer layers of GaAs may also be provided on either side of the barrier layers to reduce the intrinsic capacitance of the structure.

Abstract: A resonant tunneling diode (400) made of a quantum well (406) with tunneling barriers (404, 408) made of two different materials such as calcium fluoride (408) and silicon dioxide (404). The calcium fluoride provides lattice match between the emitter (410) and the quantum well (406). Further resonant tunneling diodes with silicon lattice match barriers may be made of III-V compounds containing nitrogen.

Abstract: A device for emitting radiation it a predetermined wavelength is disclosed. The device has a cavity comprising a first bulk region and a second bulk region of opposite conductivity type wherein a barrier is provided for spatially separating the charge carriers of the first and the second region substantially at the antinode of the standing wave pattern of said cavity. The recombination of the charge carriers at the barrier create radiation, the emission wavelength of the radiation being determined by the cavity.

Abstract: A static memory cell having no more than three transistors. A static memory cell comprises a semiconductor substrate of a first conductivity type; a buried layer in the substrate, the buried layer having a second conductivity type opposite to the first conductivity type; a transistor formed over the buried layer, the transistor having a source of the second conductivity type, a gate, and a drain of the second conductivity type, the source having a depth in the substrate greater than the depth of the drain; and alternating layers of insulative and conductive material formed proximate the source, including two conductive layers and two insulative layers, one of the insulative layers being in junction relation to the source.

Abstract: A method of forming a layer of crystalline silicon over silicon oxide and a resonant tunnel diode wherein there is provided a sufficiently clean (surface impurities<10.sup.13 /cm.sup.2), atomically smooth (rms roughness<3 Angstroms) crystalline silicon surface. Spaced apart regions of silicon oxide are formed on the surface sufficiently thin so that deposited silicon over the surface and silicon oxide will be capable of using the surface as a seed to form crystalline silicon with deposited silicon extending over the silicon oxide. The silicon is then deposited over the surface including the silicon oxide to provide the crystalline silicon over silicon oxide.

Abstract: The invention is to develop a high-speed low power consumption resonant tunneling element--a superlatticed negative-differential-resistance (NDR) functional transistor. The proposed element exhibits amplification and obvious NDR phenomena simultaneously. In this element, the emitter region includes 5-period GaInAs/AlInAs super lattice resonant tunneling and emitter layers. Since the emitter--base interface is of homojunction, the collector--emitter offset voltage (V.sub.CE, offset) may be lowered down significantly. In addition, the produced infinitesimal potential (.DELTA.Ev) at GaInAs/AlInAs interface due to heterojunction in discrete valence bands may be applied as barriers to prohibit holes flow from base towards emitter. By doing so, the base current is remarkably depressed so as to elevate efficiency of emitter injection as well as current gain.

Abstract: The invention provides a semiconductor device, having a variety of functions such as a bistable memory and a logic circuit, in which a MOS semiconductor element, a resonance tunnel diode, a hot electron transistor and the like are formed on a common substrate. An n-type Si layer and a p-type Si layer surrounded with an isolation oxide film are formed on an SOI substrate. A mask oxide film and a gate oxide film are formed, and the n-type Si layer is subjected to crystal anisotropic etching by using the mask oxide film as a mask, so as to change the n-type Si layer into the shape of a thin Si plate. After first and second tunnel oxide films are formed on side faces of this n-type Si layer, first and second polysilicon electrodes of a resonance tunnel diode and a polysilicon electrode working as a gate electrode of a MOS semiconductor element are formed out of a common polysilicon film. Thus, a Si/SiO.sub.2 type quantum device can be manufactured with ease at a low cost.

Abstract: A new quantum well MOS transistor is described along with a processes for manufacturing it. In this transistor, the source and drain areas are separated from the channel by sufficiently thin insulating layers to enable the passage of charge carriers by the tunnel effect. Each of the source and drain areas is separated from the substrate by an electrically insulating layer that is sufficiently thick to prevent charge carriers from passing through this insulating layer.

Abstract: A quantum device functioning as a memory device is provided for allowing high-speed writing and erasing of data with a low gate voltage. A source electrode and a drain electrode are formed on a substrate. A gate electrode is formed between the source and drain electrodes. Between the substrate and the gate electrode, a first barrier layer, a first quantum well layer, a second barrier layer, a second quantum well layer and a third barrier layer are stacked to form coupled quantum well layer. The thickness of each of the first and second barrier layers allows electron tunneling. The thickness of the third barrier layer does not allow electron tunneling. The energy level of the first quantum well layer is higher than the Fermi level of a conduction layer. The energy level of the second quantum well layer is lower than the energy level of the first quantum well layer.

Abstract: The present invention discloses both an n+ and a p+ unipolar, three-terminal, resonant-tunneling transistor that can be operated as a hot-electron transistor or a field effect transistor at temperatures at least as low as 77 degree Kelvin. The doped first terminal (collector or gate) is made of 3D metal or semiconductor material. An undoped insulating barrier is deposited on the first terminal. The doped electrically-contacted second terminal (emitter or source), made of a 2D semiconductor material, is deposited on the insulating barrier. An undoped double-barrier resonant-tunneling structure is deposited on the second terminal. A doped third terminal, made of 3D metal or semiconductor material, is deposited on a portion of the double-barrier resonant-tunneling structure. A doped tunneling-contact, made of 3D metal or semiconductor material, is deposited on the double-barrier resonant-tunneling structure so that the tunneling contact is isolated from the third terminal.

Abstract: A method of forming a crystalline silicon well over a perovskite barrier layer, preferably for use in formation of a resonant tunneling diode. A silicon substrate (1) is provided of predetermined crystallographic orientation. A layer of crystallographic perovskite material (5) is formed over the silicon substrate and substantially matched to the lattice constant of the silicon substrate. A layer of crystallographic silicon (7) is formed over the perovskite layer substantially matched to the lattice constant of the perovskite layer. The perovskite layer is formed by the steps of placing the silicon substrate in a chamber and then evaporating a layer of barium strontium oxide (3) thereon with a thickness of from about three to about six Angstroms and then evaporating a layer of calcium strontium titanate (5) thereon having a thickness of from about six to about 25 Angstroms thereon in the case of a tunneling diode.

Abstract: A semiconductor integrated circuit (IC) device has a silicon-on-insulator substrate having a semiconductor substrate, an insulating film formed on the semiconductor substrate, and a silicon layer formed on the insulating film. The semiconductor IC device includes at least one semiconductor device formed on the semiconductor substrate, and at least one semiconductor device formed on the silicon layer and operated with a power-supply voltage different from a power-supply voltage for the semiconductor device formed on the semiconductor substrate.

Abstract: There is provided a negative-resistance device which is easier to manufacture and can be manufactured at a lower cost as compared with the prior art, and yet has a comparatively large PV ratio, and a method for manufacturing the same. The negative-resistance device is a molecular-doped negative-resistance device which comprises a molecular-doped layer (2) made of an electron transporting lower molecular organic compound, in which the molecular-doped layer (2) is formed to be sandwiched between a pair of electrodes (2, 4), in which respective molecules of said electron transporting lower molecular organic compound are isolated from one another by an electrically insulating organic polymer, and in which said molecular-doped negative-resistance device has a negative-resistance.

Abstract: A semiconductor device includes spaced apart source and drain regions formed in a semiconductor substrate and a gate electrode insulatively spaced from a channel region between the source region and the drain region by a gate insulating film. Insulating layers are respectively formed between the source region and the channel region and between the drain region and the channel region.

Abstract: A semiconductor device is presented which exhibits both interband and intraband tunnelling. The device comprises two active layers (21, 23) which are sandwiched between two barrier layers (3, 5). These layers are located between first and second terminals (7, 9). The active layers (21, 23) are chosen such that the conduction band edge (27) of the first active layer (21) having a lower energy than the valence band edge (25) of the second active layer (23);the first active layer (21) having a first confined conduction band energy level (29) with an energy higher than that of the conduction band edge (27) of the first active layer (21);the second active layer (23) having a first confined valence band energy level (33) with an energy lower than that of the valence band edge (25) of the second active layer (23);wherein the first confined valence band energy level (33) and the first confined conduction band energy level (29) are located such that the device can exhibit both intraband and interband tunnelling.

Abstract: The method for forming a semiconductor microstructure of this invention includes the steps of: forming a mask pattern having a first opening and a second opening on a substrate having a semiconductor layer as an upper portion thereof; and selectively etching the semiconductor layer using the mask pattern to form a semiconductor microstructure extending in a first direction parallel to a surface of the substrate, wherein, in the step of selectively etching the semiconductor layer, an etching rate in a second direction vertical to the first direction and parallel to the surface of the substrate is substantially zero with respect to an etching rate in the first direction, and a width of the semiconductor microstructure is substantially equal to a shortest distance between the first opening and the second opening in the second direction.

Abstract: In a semiconductor device, concave sections in which an opening area becomes small in proportion as a depth becomes deep are formed in a crystal layer, and a quantum structure is formed on at least one crystal face of a bottom section of the concave section and a border formed between plural sidewalls thereof. In case the quantum structure is formed in the bottom section, a quantum box is formed therein. If the quantum structure is formed in the border between the sidewalls of the concave section, a quantum wire is formed therein. In case the quantum structure is formed in the sidewall of the concave section, a two-dimensional quantum well is formed therein.

Abstract: A multiple peak resonant tunneling diode (10) includes multiple vertical semiconductor structures (12, 13). The vertical structures (12, 13) include a resonant tunneling diode having a predetermined cross-sectional area and a series resistor of a predetermined resistance. The vertical structures (12, 13) are spaced from one another and interconnected in parallel. Additionally, the vertical semiconductor structures (12, 13) are fabricated such that their predetermined diode cross-sectional areas and series resistances have values that vary by predetermined amounts to adjust the respective peak currents and/or peak voltages of the vertical semiconductor structures (12, 13).

Abstract: The present invention is related to a hot-electron photo transistor. By applying the combination of quantum dots or quantum wires with sizes, the wide spacer layers, and the blocking layers to the electron injecting barrier of the emitter, the wide range of infrared detection can be attained and the resolution of detected infrared wavelength can be increased. And by introducing the resonant tunneling quantum well structure to the base layer the selection, amplification and processing of the specific infrared frequency is possible and the reduction of the dark current is induced. Therefore, the present invention is applicable to ultra-high speed tunable infrared detectors and amplifiers, ultra-high speed switching and logic devices, high speed infrared logic devices with new features, new high-speed infrared logic devices which can reduce the number of logic devices.

Abstract: A magnetic sensor has a three-terminal magnetic device consisting of an emitter, a base, and a collector. A semiconductor layer serving as the collector and a magnetic multilayered film serving as the base form a Schottky junction. The magnetic multilayered film has two magnetic films opposing each other with a nonmagnetic film between them. The emitter constructed of a metal film and the base are connected via a tunnel insulating film. The relationship between the magnetization directions in the magnetic films changes in accordance with an external magnetic field, and this changes the value of a current flowing through the magnetic device. The external magnetic field is sensed on the basis of this change in the current value.

Abstract: A semiconductor device for detecting radiation includes a plurality of quantum well layers, each of which has bound ground and excited states, interleaved with a plurality of superlattice barrier layers, each of which has a miniband of energy states. By selection of the thicknesses and compositions of the layers, the excited states of the quantum wells have energies that are approximately equal to energies of states in the minibands. Thus, the excited states and minibands form a band of energy states that is substantially continuous across the pluralities of layers. Carriers are excited from the quantum wells' ground states to the excited states by photon absorption and are swept into and through the minibands by an externally applied electric field. The carriers are collected as photocurrent. The excited states may be selectively positioned in the minibands to tailor the properties of the devices, which can have both n-type and p-type dopants.