Abstract: A method for manufacturing a plurality of holders each being for an LED package structure includes steps: providing a base, pluralities of through holes being defined in the base to divide the base into a plurality of basic units; etching the base to form a dam at an upper surface of each of the basic units of the base; forming a first electrical portion and a second electrical portion on each basic unit of the base, the first electrical portion and the second electrical portion being separated and insulated from each other by the dam; providing a plurality of reflective cups each on a corresponding basic unit of the base, each of the reflective cups surrounding the corresponding dam; and cutting the base into the plurality of basic units along the through holes to form the plurality of holders.

Abstract: The present invention provides a single-electron transistor device 100. The device comprises a source 105 and drain 110 located over a substrate 115 and a quantum island 120 situated between the source and drain, to form tunnel junctions 125, 130 between the source and drain. The device further includes a fixed-gate electrode 135 located adjacent the quantum island 120. The fixed-gate electrode has a capacitance associated therewith that varies as a function of an applied voltage to the fixed-gate electrode. The present invention also includes a method of fabricating a single-electron device 300, and a transistor circuit 800 that include a single-electron device 810.

Abstract: A photon source comprising: a quantum dot; electrical contacts configured to apply an electric field across said quantum dot: and an electrical source coupled to said contacts, said electrical source being configured to apply a potential such that carriers are supplied to said quantum dot to form a bi-exciton or higher order exciton, wherein said photon source further comprises a barrier configured to increase the time which a carrier takes to tunnel to and from said quantum dot to be greater than the radiative lifetime of an exciton in the quantum dot, the quantum dot being suitable for emission of entangled photons during decay of a bi-exciton or higher order exciton.

Abstract: A method to fabricate a hetero-junction in a Tunnel Field Effect Transistor device configuration (e.g. in a segmented nanowire TFET) is provided. A thin transition layer is inserted in between the source region and channel region such that the out-diffusion is within a very limited region of a few nm, guaranteeing extremely good doping abruptness thanks to the lower diffusion of the dopants in the transition layer. The transition layer avoids the direct contact between the highly doped source region and the lowly doped or undoped channel and allows to contain the whole doping entirely within the source region and transition layer. The thickness of the transition layer can be engineered such that the transition layer coincides with the steep transition step from the highly doped source region to the intrinsic region (channel), and hence maximizing the tunneling current.

Abstract: An embodiment of the present invention improves the fabrication and operational characteristics of a type-II superlattice material. Layers of indium arsenide and gallium antimonide comprise the bulk of the superlattice structure. One or more layers of indium antimonide are added to unit cells of the superlattice to provide a further degree of freedom in the design for adjusting the effective bandgap energy of the superlattice. One or more layers of gallium arsenide are added to unit cells of the superlattice to counterbalance the crystal lattice strain forces introduced by the aforementioned indium antimonide layers.

Abstract: A stand-off sensor assembly is provided. The sensor assembly includes a plurality of electron state definers for generating resonant tunneling current in response to the electric field, wherein the electron state definers include at least one variable characteristic such that a change in the variable characteristic affects the tunneling current, and a monitor for monitoring a change in the tunneling current exiting an electron state definer based on a change in the variable characteristic of the tunneling device.

Abstract: A gated resonant tunneling diode (GRTD) that operates without cryogenic cooling is provided. This GRTD employs conventional CMOS process technology, preferably at the 65 nm node and smaller, which is different from other conventional quantum transistors that require other, completely different process technologies and operating conditions. To accomplish this, the GRTD uses a body of a first conduction type with a first electrode region and a second electrode region (each of a second conduction type) formed in the body. A channel is located between the first and second electrode regions in the body. A barrier region of the first conduction type is formed in the channel (with the doping level of the barrier region being greater than the doping level of the body), and a quantum well region of the second conduction type formed in the channel. Additionally, the barrier region is located between each of the first and second electrode regions and the quantum well region.

Abstract: A light-emitting device includes an n-type silicon thin film (2), a silicon thin film (3), and a p-type silicon thin film (4). The silicon thin film (3) is formed on the n-type silicon thin film (2) and the p-type silicon thin film (4) is formed on the silicon thin film (3). The n-type silicon thin film (2), the silicon thin film (3), and the p-type silicon thin film (4) form a pin junction. The n-type silicon thin film (2) includes a plurality of quantum dots (21) composed of n-type Si. The silicon thin film (3) includes a plurality of quantum dots (31) composed of p-type Si. The p-type silicon thin film (4) includes a plurality of quantum dots (41) composed of p-type Si. Electrons are injected from the n-type silicon thin film (2) side and holes are injected from the p-type silicon thin film (4) side, whereby light is emitted at a silicon nitride film (3).

Abstract: A resonant tunneling device includes a first semiconductor material with an energy difference between valence and conduction bands of Eg1, and a second semiconductor material with an energy difference between valence and conduction bands of Eg2, wherein Eg1 and Eg2 are different from one another. The device further includes an energy selectively transmissive interface connecting the first and second semiconductor materials.

Abstract: One or more quantum dots are used to control current flow in a transistor. Instead of being disposed in a channel between source and drain, the quantum dot (or dots) are vertically separated from the source and drain by an insulating layer. Current can tunnel between the source/drain electrodes and the quantum dot (or dots) by tunneling through the insulating layer. Quantum dot energy levels can be controlled with one or more gate electrodes capacitively coupled to some or all of the quantum dot(s). Current can flow between source and drain if a quantum dot energy level is aligned with the energy of incident tunneling electrons. Current flow between source and drain is inhibited if no quantum dot energy level is aligned with the energy of incident tunneling electrons. Here energy level alignment is understood to have a margin of about the thermal energy (e.g., 26 meV at room temperature).

Abstract: A high-efficiency white-light-emitting device that includes a polariton light emitter that emits UV or blue light to a down-converting material that converts the polariton emissions to white light. The polariton light emitter includes an active region situated within a resonant optical cavity formed on a substrate. The down-converting material can comprise a luminophoric phosphor or other material. The polariton light and down-converting material can be arranged in a single apparatus to provide a white-light-emitting device that can be used for lighting and instrumentation. The device can also be configured for high-frequency modulation to provide optical signals for communications and control systems.

Abstract: A quantum dot, which is an ultrafine grain, has a core-shell structure having a core portion and a shell portion protecting the core portion. The surface of the shell portion is covered with two kinds of surfactants, a hole-transporting surfactant and an electron-transporting surfactant, which are concurrently present. Moreover, the hole-transporting surfactant has a HOMO level which tunneling-resonates with the valence band of the quantum dot and the electron-transporting surfactant has a LUMO level which tunneling-resonates with the transfer band of the quantum dot. Thus, a nanograin material which has good carrier transport efficiency and is suitable for use in a photoelectric conversion device is achieved.

Abstract: A device and method for manipulating a direction of motion of current carriers are presented. The device comprises a structure containing a two-dimensional gas of current carriers configured to define at least one region of inhomogeneity which is characterized by a substantially varying value of at least one parameter from the following: a spin-orbit coupling constant, density of the spin carriers, and a mobility of the gas. The device may be configured and operable to perform spin manipulation of a flux of the spin carrying current carriers to provide at least one of the following types of deviation of said spin-carrying current: spin dependent refraction, spin dependent reflection and spin dependent diffraction on desired deviation angles of a direction of motion of the spin-carrying current carriers being incident on said at least one region of inhomogeneity.

Abstract: An integrated circuit (IC) includes a plurality of circuit modules, a millimeter wave (MMW) transceiver, a controller. The controller is further operably coupled to: obtain potential inter-chip millimeter wave (MMW) communication links within a device; identify at least one of the inter-chip potential inter-chip MMW communication links as being a dedicated point-to-point MMW link; determine requirements to establish the dedicated point-to-point MMW link; and, when inter-chip MMW resources are available to support the requirements, allocate the inter-chip MMW resources to support the dedicated point-to-point MMW link.

Abstract: An electron transport device, including at least one transport layer in which at least one periodic dislocation and/or defect array is produced, and a mechanism for guiding electrons in the transport layer.

Abstract: A transistor device having a graphene base for the transport of electrons into a collector is provided. The transistor consists of a heterostructure comprising an electron emitter, an electron collector, and a graphene material base layer consisting of one or more sheets of graphene situated between the emitter and the collector. The transistor also can further include an emitter transition layer at the emitter interface with the base and/or a collector transition layer at the base interface with the collector. The electrons injected into the graphene material base layer can be “hot electrons” having an energy E substantially greater than EF, the Fermi energy in the graphene material base layer or can be “non-hot electrons” having an energy E approximately equal to than EF. The electrons can have the properties of ballistic transit through the base layer.

Abstract: The invention suggests a transistor (21) comprising a source (24) and a drain (29) as well as a barrier region (27) located between the source and the drain. The barrier region is separated from the source and the drain by intrinsic or lowly doped regions (26, 28) of a semiconductor material. Potential barriers are formed at the interfaces of the barrier region and the intrinsic or lowly doped regions. A gate electrode (32) is provided in the vicinity of the potential barriers such that the effective height and/or width of the potential barriers can be modulated by applying an appropriate voltage to the gate electrode.

Abstract: To provide a resonator that includes a resonant tunneling diode that can generate an electromagnetic wave. In the resonator, the resonant tunneling diode and a resistor layer are sandwiched between first and second conductors in a direction approximately perpendicular to the in-plane direction of the resonant tunneling diode. Further, the in-plane cross-sectional area of the resistor layer is larger than that of the resonant tunneling diode. Further, the width of the in-plane cross-sectional area of the resistor layer is more than twice as large as the skin depth of an electromagnetic wave to be caused to resonate.

Abstract: A transistor includes: a semiconductor substrate; a channel region arranged on the semiconductor substrate; a source and a drain respectively arranged on either side of the channel region; and a conductive nano tube gate arranged on the semiconductor substrate to transverse the channel region between the source and the drain. Its method of manufacture includes: arranging a conductive nano tube on a surface of a semiconductor substrate; defining source and drain regions having predetermined sizes and traversing the nano tube; forming a metal layer on the source and drain regions; removing a portion of the metal layer formed on the nano tube to respectively form source and drain electrodes separated from the metal layer on either side of the nano tube; and doping a channel region below the nano tube arranged between the source and drain electrodes by ion-implanting.

Abstract: A TFET includes a source region (110, 210), a drain region (120, 220), a channel region (130, 230) between the source region and the drain region, and a gate region (140, 240) adjacent to the channel region. The source region contains a first compound semiconductor including a first Group III material and a first Group V material, and the channel region contains a second compound semiconductor including a second Group III material and a second Group V material. The drain region may contain a third compound semiconductor including a third Group III material and a third Group V material.

Abstract: An object is to provide a resonator and a vibrator with a high Q value in which dissipation of vibration energy in vibration of the vibrator is small, and a thickness of a support part of the vibrator of a beam structure is made thicker than a thickness of the vibrator and the support part is formed in axisymmetry with respect to a length direction of a beam. By this configuration, brittleness of the support part is improved and loss of vibration energy from the support part is reduced and also loss of vibration energy resulting from surface roughness of a surface of the vibrator can be reduced, so that a resonator having a high Q value can be provided.

Abstract: The invention relates to an interconnection network and an integrated circuit and a method for manufacturing the same. Furthermore, the invention relates to a method for signal transfer between semiconductor structures. The invention is characterized in that a signal of a first semiconductor structure is supplied to a transmitter, which generates from the signal a plasmon wave, and couples the latter into a waveguide. The plasmons fed through the waveguide are received by a receiver, converted to an electric signal and forwarded to a second semiconductor structure.

Abstract: A molecular quantum interference device for use in molecular electronics. In one embodiment, the device includes a molecular quantum interference unit having a first terminal group and a second terminal group between which quantum interference affects electrical conduction, a molecular spacer having a first terminal group and a second terminal group and coupled to the molecular quantum interference unit through a chemical bonding between the first terminal group of the molecular spacer and the second terminal group of the molecular quantum interference unit, a first electrode electrically coupled to the molecular quantum interference unit and configured to supply charge carriers to or receive charge carriers from the molecular quantum interference unit, and a second electrode electrically coupled to the molecular spacer and configured to receive charge carriers from or supply charge carriers to the molecular spacer.

Abstract: A method of manufacturing a parallel redundant array of single-electron devices. The method includes (a) providing a mask for diffusing a plurality of n-doped regions defined by a first set of a plurality of active regions, (b) providing a mask for disposing a plurality of polysilicon gates defined by a second set of a plurality of exposed regions, wherein an offset between a first member of the plurality of the exposed region of the first set differs in offset from a second member of the plurality of the exposed region of the second set, and (c) fabricating the parallel redundant array of single-electron devices as a function of the offset.

Abstract: A semiconductor device and method for fabricating a semiconductor device incorporating gate control over a resonant tunneling structure. The semiconductor device includes a source terminal, a gate terminal, a drain terminal, and a resonant tunneling structure located beneath or adjacent to the gate terminal, where the gate terminal controls an electrostatic potential drop through the resonant tunneling structure as well as controlling a potential within a portion of the conduction channel immediately beneath the gate terminal as in a MOSFET. The semiconductor device is fabricated by growing epitaxial layers of tunnel barriers and quantum wells, where a quantum well is formed between each set of two tunneling barriers. Additionally, the epitaxial layers of tunnel barriers and quantum wells are grown, etched and patterned to form a resonant tunneling structure. Further, the semiconductor device is grown, etched and patterned to form a gate, source and drain electrode.

Abstract: A quantum device comprises first conductive members and second conductive members confining carriers in the z direction and having two dimensional electron gas on the xy plane. Third conductive members generating an electric field having an effect on the first conductive members. An insulating member easily passing a tunnel current between the first conductive members and the second conductive members. Another insulating member hardly passing a tunnel current between the first conductive members and the third conductive members. An electric field generated by a potential applied to the third conductive members has an effect on the sub-band of the first conductive members.

Abstract: A device comprising a nanotube configured as a resonator, a source electrode, a gate electrode, a drain electrode and at least one impeding element, wherein the at least one impeding element is configured to minimize energy loss due to a contact resistance between at least the source electrode and the nanotube.

Abstract: A system is provided. The system includes a device that includes top and bottom thermally conductive substrates positioned opposite to one another, wherein a top surface of the bottom thermally conductive substrate is substantially atomically flat and a thermal blocking layer disposed between the top and bottom thermally conductive substrates. The device also includes top and bottom electrodes separated from one another between the top and bottom thermally conductive substrates to define a tunneling path, wherein the top electrode is disposed on the thermal blocking layer and the bottom electrode is disposed on the bottom thermally conductive substrate.

Abstract: A resonant tunneling structure for generating oscillation with multiple fundamental oscillation frequencies is provided. A first quantum well layer has a second sub-band (E2). A second quantum well layer has a first sub-band (E1) and a third sub-band (E3). When no electric field is applied, the resonant tunneling structure satisfies “(Eb1, Eb2)<E1<E2<E3”, where band edge energies of a first and second electrical contact layers relative to a carrier are expressed by Eb1 and Eb2, respectively. When a first electric field (Va) is applied, a resonant tunneling phenomenon is caused by the third sub-band and the second sub-band. When a second electric field (Vb) different in polarity from the first electric field is applied, a resonant tunneling phenomenon is caused by the second sub-band and the first sub-band.

Abstract: A gated resonant tunneling diode (GRTD) that operates without cryogenic cooling is provided. This GRTD employs conventional CMOS process technology, preferably at the 65 nm node and smaller, which is different from other conventional quantum transistors that require other, completely different process technologies and operating conditions. To accomplish this, the GRTD uses a body of a first conduction type with a first electrode region and a second electrode region (each of a second conduction type) formed in the body. A channel is located between the first and second electrode regions in the body. A barrier region of the first conduction type is formed in the channel (with the doping level of the barrier region being greater than the doping level of the body), and a quantum well region of the second conduction type formed in the channel. Additionally, the barrier region is located between each of the first and second electrode regions and the quantum well region.

Abstract: An oscillation device has a resonant tunneling diode formed by interposing a gain medium including a first barrier layer, a quantum well layer and a second barrier layer between a first thickness adjusting layer and a second thickness adjusting layer. The oscillation device also has a switch for switching the polarity of a bias voltage being applied to the resonant tunneling diode. The first thickness adjusting layer and the second thickness adjusting layer have different thicknesses. Thus, a single oscillation device is driven to oscillate with different oscillation frequencies.

Abstract: A single-electron transistor (1) has an elongate conductive channel (2) and a side gate (3) formed in a 5 nm-thick layer (4) of Ga0.98Mn0.02As. The single-electron transistor (1) is operable, in a first mode, as a transistor and, in a second mode, as non-volatile memory.

Abstract: To provide an oscillation device having a long oscillation wavelength in which wavelength variable width is relatively broad and wavelength sweep rate is relatively high. An oscillation device includes a gain medium having a gain with respect to an electromagnetic wave to be oscillated, cavity structures for resonating the electromagnetic wave, and energy injection means and for injecting pumping energy into the gain medium. The gain medium is sandwiched between a first negative permittivity medium and a second magnetic permittivity medium each of which real part of permittivity with respect to the electromagnetic wave is negative. Electric field application means is provided for at least one of the first negative permittivity medium and the second negative permittivity medium to apply an electric field for changing a depletion region formed at a boundary part with the gain medium.

Abstract: Structures include a tunneling device disposed over first and second lattice-mismatched semiconductor materials. Process embodiments include forming tunneling devices over lattice-mismatched materials.

Abstract: An integrated circuit pad structure includes a ground strip (206) positioned below a pad (101). In one example a conductive element (102) is coupled to the pad (101), and at least two tiled layers, positioned below the first conductive element (102) and positioned above the ground strip (206) are included. A conductor (203), may run beneath the ground strip (206). In a second example, a pad (101) is seated on a ground shield cage having a bottom conductive ground element (302) including several ground strips where at least one ground strip (116) is along a signal routing path. The ground shield cage further includes a set of stacked conductive ground elements, stacked to form sidewalls (209, 210) of the cage. The top conductive ground element (301) of the stacked elements has an inner perimeter and an outer perimeter, such that the inner perimeter surrounds the pad (101) and the top conductive ground element (301) is in the plane of the conductive element (102) coupled to the pad (101).

Abstract: A multi-junction device can be used as a high efficiency solar cell, laser, or light-emitting diode. Multiple epitaxial films grown over a substrate have very low defect densities because an initial epitaxial layer is a coincidence-site lattice (CSL) layer that has III-V atoms that fit into lattice sites of Silicon atoms in the substrate. The substrate is a Si (111) substrate which has a step height between adjacent terraces on its surface that closely matches the step height of GaAs (111). Any anti-phase boundaries (APBs) formed at terrace steps cancel out within a few atomic layers of GaAs in the (111) orientation since the polarity of the GaAs molecule is aligned with the (111) direction. A low CSL growth temperature grows GaAs horizontally along Si terraces before vertical growth. Tunnel diode and active solar-cell junction layers can be grown over the CSL at higher temperatures.

Abstract: A pn junction type Group III nitride semiconductor light-emitting device 10 (11) of the present invention has a light-emitting layer 2 of multiple quantum well structure in which well layers 22 and barrier layers 21 including Group III nitride semiconductors are alternately stacked periodically between an n-type clad layer 105 and a p-type clad layer 107 which are formed on a crystal substrate and which include Group III nitride semiconductors, in which one end layer 21m of the light-emitting layer 2 is closest to and opposed to the n-type clad layer, and the other end layer 21n of the light-emitting layer 2 is closest to and opposed to the p-type clad layer, both the one and the other end layers are barrier layers, and the other end layer 21n is thicker than the barrier layer of the one end layer.

Abstract: A semiconductor device and method for fabricating a semiconductor device incorporating gate control over a resonant tunneling structure. The semiconductor device includes a source terminal, a gate terminal, a drain terminal, and a resonant tunneling structure located beneath or adjacent to the gate terminal, where the gate terminal controls an electrostatic potential drop through the resonant tunneling structure as well as controlling a potential within a portion of the conduction channel immediately beneath the gate terminal as in a MOSFET. The semiconductor device is fabricated by growing epitaxial layers of tunnel barriers and quantum wells, where a quantum well is formed between each set of two tunneling barriers. Additionally, the epitaxial layers of tunnel barriers and quantum wells are grown, etched and patterned to form a resonant tunneling structure. Further, the semiconductor device is grown, etched and patterned to form a gate, source and drain electrode.

Abstract: A quantum-well photoelectric device, such as a quantum cascade laser, is constructed of monocrystalline nanoscale membranes physically removed from a substrate and mechanically assembled into a stack.

Abstract: One or more quantum dots are used to control current flow in a transistor. Instead of being disposed in a channel between source and drain, the quantum dot (or dots) are vertically separated from the source and drain by an insulating layer. Current can tunnel between the source/drain electrodes and the quantum dot (or dots) by tunneling through the insulating layer. Quantum dot energy levels can be controlled with one or more gate electrodes capacitively coupled to some or all of the quantum dot(s). Current can flow between source and drain if a quantum dot energy level is aligned with the energy of incident tunneling electrons. Current flow between source and drain is inhibited if no quantum dot energy level is aligned with the energy of incident tunneling electrons. Here energy level alignment is understood to have a margin of about the thermal energy (e.g., 26 meV at room temperature).

Abstract: A silicon integrated circuit device comprising a near intrinsic silicon substrate in which there are one or more ohmic contact regions. An insulating layer lies above the substrate, and on top of the insulating layer is a lower layer of one or more aluminium gates. The surface of each of the lower gates is oxidised to insulate them from an upper aluminium gate that extends over the lower gates.

Abstract: A solid-state light source includes a substrate, a solid-state light-emitting chip, a plurality of micro-members and a light-permeable encapsulation. The substrate has a substantially flat surface. The solid-state light-emitting chip is arranged on the substantially flat surface of the substrate and electrically connected to the substrate. The micro-members are arranged on the surface of the substrate and parallel with the solid-state light emitting chip. The light-permeable encapsulation is arranged on the surface of the substrate and covers the solid-state light-emitting chip and the micro-members.

Abstract: A semiconductor photodetector for photon detection without the use of avalanche multiplication, and capable of operating at low bias voltage and without excess noise. In one embodiment, the photodetector comprises a plurality of InP/AlInGaAs/AlGaAsSb layers, capable of spatially separating the electron and the hole of an photo-generated electron-hole pair in one layer, transporting one of the electron and the hole of the photo-generated electron-hole pair into another layer, focalizing it into a desired volume and trapping it therein, the desired volume having a dimension in a scale of nanometers to reduce its capacitance and increase the change of potential for a trapped carrier, and a nano-injector, capable of injecting carriers into the plurality of InP/AlInGaAs/AlGaAsSb layers, where the carrier transit time in the nano-injector is much shorter than the carrier recombination time therein, thereby causing a very large carrier recycling effect.

Abstract: A method for a thin film transistor array panel includes forming a gate line and a pixel electrode on a substrate, forming a gate insulating layer covering the gate line, forming a data line including a source electrode and a drain electrode on the gate insulating layer, forming an interlayer insulating layer covering the data line and the drain electrode on the gate insulating layer, forming a first opening in the interlayer insulating layer, forming an organic semiconductor in the first opening, forming a passivation layer on the organic semiconductor and the interlayer insulating layer, and forming a second opening in the interlayer insulating layer to expose the pixel electrode.

Abstract: According to some embodiments, the present invention provides a nanoelectronic device based on a nanostructure that may include a nanotube with first and second ends, a metallic nanoparticle attached to the first end, and an insulating nanoparticle attached to the second end. The nanoelectronic device may include additional nanostructures so a to form a plurality of nanostructures comprising the first nanostructure and the additional nanostructures. The plurality of nanostructures may arranged in a network comprising a plurality of edges and a plurality of vertices, wherein each edge comprises a nanotube and each vertex comprises at least one insulating nanoparticle and at least one metallic nanoparticle adjacent the insulating nanoparticle. The combination of at least one edge and at least one vertex comprises a diode. The device may be an optical rectenna.

Abstract: A semiconductor photodetector for photon detection without the use of avalanche multiplication, and capable of operating at low bias voltage and without excess noise. In one embodiment, the photodetector comprises a plurality of InP/AlInGaAs/AlGaAsSb layers, capable of spatially separating the electron and the hole of an photo-generated electron-hole pair in one layer, transporting one of the electron and the hole of the photo-generated electron-hole pair into another layer, focalizing it into a desired volume and trapping it therein, the desired volume having a dimension in a scale of nanometers to reduce its capacitance and increase the change of potential for a trapped carrier, and a nano-injector, capable of injecting carriers into the plurality of InP/AlInGaAs/AlGaAsSb layers, where the carrier transit time in the nano-injector is much shorter than the carrier recombination time therein, thereby causing a very large carrier recycling effect.

Abstract: A nonmagnetic semiconductor device which may be utilized as a spin resonant tunnel diode (spin RTD) and spin transistor, in which low applied voltages and/or magnetic fields are used to control the characteristics of spin-polarized current flow. The nonmagnetic semiconductor device exploits the properties of bulk inversion asymmetry (BIA) in (110)-oriented quantum wells. The nonmagnetic semiconductor device may also be used as a nonmagnetic semiconductor spin valve and a magnetic field sensor. The spin transistor and spin valve may be applied to low-power and/or high-density and/or high-speed logic technologies. The magnetic field sensor may be applied to high-speed hard disk read heads. The spin RTD of the present invention would be useful for a plurality of semiconductor spintronic devices for spin injection and/or spin detection.

Abstract: A semiconductor transistor device includes one or more conductive base regions, a first semiconductor barrier region, a second semiconductor barrier region, a conductive emitter region, and a conductive collector region. The first semiconductor barrier region or the second semiconductor barrier region has a dimension smaller than 100 ?. A first Schottky barrier junction is formed at the interface of the first semiconductor barrier region and the one or more conductive base regions. A second Schottky barrier junction is formed at the interface of the second semiconductor barrier region and the one or more conductive base regions. A third Schottky barrier junction is formed at the interface of the conductive emitter region and the first semiconductor barrier region. A fourth Schottky barrier junction is formed at the interface of the conductive collector region and the second semiconductor barrier region.

Abstract: A memory cell that includes a first magnetic layer, the magnetization of which is free to rotate under the influence of spin torque; a tunneling layer comprising a magnetic resonant tunneling diode (MRTD); and a second magnetic layer, wherein the magnetization of the second magnetic layer is pinned, wherein the tunneling layer is between the first magnetic layer and the second magnetic layer.

Abstract: A gated resonant tunneling diode (GRTD) that operates without cryogenic cooling is provided. This GRTD employs conventional CMOS process technology, preferably at the 65 nm node and smaller, which is different from other conventional quantum transistors that require other, completely different process technologies and operating conditions. To accomplish this, the GRTD uses a body of a first conduction type with a first electrode region and a second electrode region (each of a second conduction type) formed in the body. A channel is located between the first and second electrode regions in the body. A barrier region of the first conduction type is formed in the channel (with the doping level of the barrier region being greater than the doping level of the body), and a quantum well region of the second conduction type formed in the channel. Additionally, the barrier region is located between each of the first and second electrode regions and the quantum well region.