Abstract: A gated resonant tunneling diode (GRTD) is disclosed including a metal oxide semiconductor (MOS) gate over a gate dielectric layer which is biased to form an inversion layer between two barrier regions, resulting in a quantum well less than 15 nanometers wide. Source and drain regions adjacent to the barrier regions control current flow in and out of the quantum well. The GRTD may be integrated in CMOS ICs as a quantum dot or a quantum wire device. The GRTD may be operated in a negative conductance mode, in a charge pump mode and in a radiative emission mode.

Abstract: A gated resonant tunneling diode (GRTD) that operates without cryogenic cooling is provided. This GRTD employs conventional CMOS process technology, preferably at the 65 nm node and smaller, which is different from other conventional quantum transistors that require other, completely different process technologies and operating conditions. To accomplish this, the GRTD uses a body of a first conduction type with a first electrode region and a second electrode region (each of a second conduction type) formed in the body. A channel is located between the first and second electrode regions in the body. A barrier region of the first conduction type is formed in the channel (with the doping level of the barrier region being greater than the doping level of the body), and a quantum well region of the second conduction type formed in the channel. Additionally, the barrier region is located between each of the first and second electrode regions and the quantum well region.

Abstract: A resonant tunneling structure for generating oscillation with multiple fundamental oscillation frequencies is provided. A first quantum well layer has a second sub-band (E2). A second quantum well layer has a first sub-band (E1) and a third sub-band (E3). When no electric field is applied, the resonant tunneling structure satisfies “(Eb1, Eb2)<E1<E2<E3”, where band edge energies of a first and second electrical contact layers relative to a carrier are expressed by Eb1 and Eb2, respectively. When a first electric field (Va) is applied, a resonant tunneling phenomenon is caused by the third sub-band and the second sub-band. When a second electric field (Vb) different in polarity from the first electric field is applied, a resonant tunneling phenomenon is caused by the second sub-band and the first sub-band.

Abstract: Embodiments described herein include LEDs that promote photon tunneling. One embodiment of an LED device can have a quantum well layer adapted to generate light having a wavelength, a p-doped alloy layer on a first side of the quantum well layer and an n-doped alloy layer on the other side of the quantum well layer. The device can also include an electrode electrically connected to the p-doped alloy layer and an electrode electrically connected to the n-doped alloy layer. According to one embodiment the thickness of the n-doped alloy layer is less than the wavelength of light generated by the quantum well layer to allow light generated by the quantum well layer to tunnel to the medium (e.g., air). In another embodiment, the entire layer structure can have a thickness that is less than the wavelength.

Abstract: A circuit includes a resonant tunneling device having first and second terminals, and biased to exhibit a negative resistance between the terminals, the terminals being coupled at spaced locations to a further section made of a material which has a plasma resonance tuned to a selected frequency. A different circuit includes a resonant tunneling structure with plural layers, including an outer layer coupled to a further layer made of a material which has a plasma resonance tuned to a selected frequency. Two circuit sections are respectively coupled to the resonant tunneling structure at spaced locations thereon. A bias is applied across the tunneling structure and further layer, and causes the tunneling structure to exhibit a negative resistance.

Abstract: A hetero-crystalline device structure and a method of making the same include a first layer and a nanostructure integral to a crystallite in the first layer. The first layer is a non-single crystalline material. The nanostructure is a single crystalline material. The nanostructure is grown on the first layer integral to the crystallite using epitaxial growth.

Abstract: An integrated ion chip for a large scale quantum device of interconnected ion (or other charged particles) traps each holding a small number of particles for a finite period of time, in a preferred embodiment using sapphire as the substrate, having an internal trapping, translation, and quantum manipulation zones and having a first set of electrodes and a second set of electrodes for trapping ions and for quantum manipulations, in a preferred embodiment using silicon carbide (and materials of similar characteristics) as a core structure material, and utilizing unique fabrication processes using micromachining and thin film techniques.

Abstract: A tunnel junction light emitting device according to the present invention is provided with an active layer and an electron tunneling region supplying the active layer with carriers. The electron tunneling region has a first p-type semiconductor layer, a second p-type semiconductor layer and an n-type semiconductor layer. The second p-type semiconductor layer is sandwiched between the first p-type semiconductor layer and the n-type semiconductor layer, and the first p-type semiconductor layer, the second p-type semiconductor layer and the n-type semiconductor layer form a tunnel junction to which a reverse bias is applied. An energy level at a valence band edge of the second p-type semiconductor layer is equal to or lower than an energy level at a valence band edge of the first p-type semiconductor layer.

Abstract: Method of manufacturing an optical device, and an optical device, the optical device having one or more layers (13) of quantum-dots located in-between barrier layers (12). A spacer layer (15) is grown on a barrier layer (12), such that the spacer layer (15) is adapted for substantially blocking strain fields induced by quantum-dot layers, thereby producing a smooth growth front for a subsequent barrier layer (12).

Abstract: The present invention provides a single-electron transistor device 100. The device comprises a source 105 and drain 110 located over a substrate 115 and a quantum island 120 situated between the source and drain, to form tunnel junctions 125, 130 between the source and drain. The device further includes a fixed-gate electrode 135 located adjacent the quantum island 120. The fixed-gate electrode has a capacitance associated therewith that varies as a function of an applied voltage to the fixed-gate electrode. The present invention also includes a method of fabricating a single-electron device 300, and a transistor circuit 800 that include a single-electron device 810.

Abstract: An electron tunneling device includes a first non-insulating strip and a second non-insulating strip spaced apart from one another such that first and second end portions, respectively, of the first and second non-insulating strips cooperate to form an antenna having an antenna impedance. The first and second non-insulating strips include a transition region that extends from the antenna to a tunneling region in which the first and second non-insulating strips are in a confronting relationship. An arrangement cooperates with a portion of each of the first and second non-insulating strips in the tunneling region to form an electron tunneling structure exhibiting a tunneling region impedance. The transition region is configured to match the antenna impedance to the tunneling region impedance. The transition region can provide for changing an electromagnetic field orientation between the antenna and the tunneling region.

Abstract: A molecular quantum interference device for use in molecular electronics. In one embodiment, the device includes a molecular quantum interference unit having a first terminal group and a second terminal group between which quantum interference affects electrical conduction, a molecular spacer having a first terminal group and a second terminal group and coupled to the molecular quantum interference unit through a chemical bonding between the first terminal group of the molecular spacer and the second terminal group of the molecular quantum interference unit, a first electrode electrically coupled to the molecular quantum interference unit and configured to supply charge carriers to or receive charge carriers from the molecular quantum interference unit, and a second electrode electrically coupled to the molecular spacer and configured to receive charge carriers from or supply charge carriers to the molecular spacer.

Abstract: A semiconductor device includes a conduct structure to which are arranged contacts for a source and a drain, a resonance region including at least two barrier regions, at least one resonator between the barrier regions and a control electrode and which resonance region is arranged between the contacts. The conduct structure between the contacts is homogeneous and the barrier regions are formed of narrows arranged to the conduct structure. In addition, disclosed are methods to control the state of a semiconductor device and manufacture the same.

Abstract: A Spin-Dependent Tunnelling cell comprises a first barrier layer of a first material and a second barrier layer of a second material sandwiched between a first ferromagnetic layer and a second ferromagnetic layer. The first and second barrier layers are formed to a combined thicknesses so that a Tunnelling Magnetoresistance versus voltage characteristic of the cell has a maximum at a non-zero bias voltage.

Abstract: A detector includes a voltage source for providing a bias voltage and first and second non-insulating layers, which are spaced apart such that the bias voltage can be applied therebetween and form an antenna for receiving electromagnetic radiation and directing it to a specific location within the detector. The detector also includes an arrangement serving as a transport of electrons, including tunneling, between and to the first and second non-insulating layers when electromagnetic radiation is received at the antenna. The arrangement includes a first insulating layer and a second layer configured such that using only the first insulating in the arrangement would result in a given value of nonlinearity in the transport of electrons while the inclusion of the second layer increases the nonlinearity above the given value. A portion of the electromagnetic radiation incident on the antenna is converted to an electrical signal at an output.

Abstract: One embodiment of the invention includes a quantization circuit. The circuit comprises a sense resistor configured to provide a voltage that is indicative of a digital quantization of an input voltage. The circuit also comprises a plurality of resonant tunneling diodes (RTDs) arranged in series between the input voltage and the sense resistor. The circuit further comprises a sequencing circuit arranged in parallel with the plurality of RTDs and configured to conduct a portion of a current flowing between the input voltage and the sense resistor to define a sequential order of triggering of the plurality of RTDs in response to a given magnitude of the input voltage.

Abstract: A resonant transistor includes a substrate, a source and a drain formed on the substrate, an input electrode and a carbon nanotube gate. A gap is formed between the source and the drain. The input electrode is formed on the substrate. The carbon nanotube gate is clamped on one end by a contact electrode and positioned, preferably cantilevered, over the gap and over the input electrode.

Abstract: A flash memory cell includes a substrate and a gate structure formed on the substrate. The gate structure includes a tunneling layer over the substrate, a storage layer over the tunneling layer, a blocking layer over the storage layer, and a gate electrode over the dielectric. The storage layer preferably has a conduction band lower than a conduction band of silicon. The blocking layer is preferably formed of a high-k dielectric material.

Abstract: A field effect transistor (FET) includes a semiconductor region of a first conductivity type and a well region of a second conductivity type extending over the semiconductor region. A gate electrode is adjacent to but insulated from the well region, and a source region of the first conductivity type is in the well region. A heavy body region is in electrical contact with the well region, and includes a material having a lower energy gap than the well region.

Abstract: A Resonant Cavity Light Emitting Diode (RCLED) device having a first active region having one or more quantum wells disposed within, a first chamber and a second chamber coupled to the first active region and a first reflector and a second reflector coupled to the first and second chambers respectively is disclosed. The RCLED can be optimized to emit radiation in the carbon-dioxide absorption band.

Abstract: A variety of processes are disclosed for controlling NDR characteristics for an NDR element, such as peak-to-valley ratio (PVR), NDR onset voltage (VNDR) and related parameters. The processes are based on conventional semiconductor manufacturing operations so that an NDR device can be fabricated using silicon based substrates and along with other types of devices.

Abstract: A nonmagnetic semiconductor device which may be utilized as a spin resonant tunnel diode (spin RTD) and spin transistor, in which low applied voltages and/or magnetic fields are used to control the characteristics of spin-polarized current flow. The nonmagnetic semiconductor device exploits the properties of bulk inversion asymmetry (BIA) in (110)-oriented quantum wells. The nonmagnetic semiconductor device may also be used as a nonmagnetic semiconductor spin valve and a magnetic field sensor. The spin transistor and spin valve may be applied to low-power and/or high-density and/or high-speed logic technologies. The magnetic field sensor may be applied to high-speed hard disk read heads. The spin RTD of the present invention would be useful for a plurality of semiconductor spintronic devices for spin injection and/or spin detection.

Abstract: A light source is provided including an LED component having an emitting surface, which may include: i) an LED capable of emitting light at a first wavelength; and ii) a re-emitting semiconductor construction which includes a second potential well not located within a pn junction having an emitting surface; or which may alternately include a first potential well located within a pn junction and a second potential well not located within a pn junction; and which additionally includes a converging optical element.

Abstract: A vertical gate-depleted single electron transistor (SET) is fabricated on a conducting or insulating substrate. A plurality of lightly doped basic materials and tunneling barriers are fabricated on top of a substrate, wherein at least two of the layers of basic materials sandwich the layers of tunneling barriers and at least two of the layers of tunneling barriers sandwich at least one of the layers of basic materials. A mesa is fabricated on top of the layers of basic materials and tunneling barriers, and has an undercut shape. An ohmic contact is fabricated on top of the mesa, and one or more gate Schottky contacts are fabricated on top of the layers of lightly doped basic materials and tunneling barriers. A quantum dot is induced by gate depletion, when a source voltage is set as zero, a drain voltage is set to be less than 0.1, and a gate voltage is set to be negative.

Abstract: The present invention relates to a device structure that contains two or more conducting layers, two peripheral insulating layers, one or more intermediate insulating layers, and two or more conductive contacts. The two or more conducting layers are sandwiched between the two peripheral insulating layers, and they are spaced apart by the intermediate insulating layers to form two or more quantum wells. Each of the conductive contacts is directly and selectively connected with one of the conducting layers, so the individual quantum wells can be selectively accessed through the conductive contacts. Such a device structure preferably contains a coupled quantum well devices having two or more quantum wells that can be coupled together by inter-well tunneling effect at degenerate energy levels. More preferably, the device structure contains a memory cell having three quantum wells that can be arranged and constructed to define two different memory states.

Abstract: Device designs and techniques for providing efficient hybrid silicon-on-insulator devices where a silicon waveguide core or resonator is clad by the insulator and a top functional cladding layer in some implementations of the designs.

Abstract: A sub-micron, on the order of 80-nanometer diameter, resonant tunneling diode having a peak-to-valley ratio of approximately 5.1 to 1, and a method for its manufacture. The invention is unique in that its performance characteristics are unmatched in comparably sized resonant tunneling diodes. Further, the polyimide passivation and planarization methodology provides unexpected processing advantages with respect to application in the fabrication of resonant tunneling diodes. The invention includes a substrate 100 that serves as a foundation for bottom contact layers 102 and a polyimide 700 coating. An ohmic metal contact 300 and emitter metal contact 400 protrude above the polyimide 700 coating exposing the ohmic metal contact 300 and emitter metal contact 400. The contacts are capped with an etch-resistant coating 710 thus allowing for the polyimide etch, and other etching processes without adversely affecting the contacts.

Abstract: A nonmagnetic semiconductor device which may be utilized as a spin resonant tunnel diode (spin RTD) and spin transistor, in which low applied voltages and/or magnetic fields are used to control the characteristics of spin-polarized current flow. The nonmagnetic semiconductor device exploits the properties of bulk inversion asymmetry (BIA) in (110)-oriented quantum wells. The nonmagnetic semiconductor device may also be used as a nonmagnetic semiconductor spin valve and a magnetic field sensor. The spin transistor and spin valve may be applied to low-power and/or high-density and/or high-speed logic technologies. The magnetic field sensor may be applied to high-speed hard disk read heads. The spin RTD of the present invention would be useful for a plurality of semiconductor spintronic devices for spin injection and/or spin detection.

Abstract: Various embodiments of the present invention are related to microresonator systems that can be used as a laser, a modulator, and a photodetector and to methods for fabricating the microresonator systems. In one embodiment, a microresonator system comprises a substrate having a top surface layer, at least one waveguide embedded within the substrate, and a microdisk having a top layer, an intermediate layer, a bottom layer, current isolation region, and a peripheral annular region. The bottom layer of the microdisk is in electrical communication with the top surface layer of the substrate and is positioned so that at least a portion of the peripheral annular region is located above the at least one waveguide. The current isolation region is configured to occupy at least a portion of a central region of the microdisk and has a relatively lower refractive index and relatively larger bandgap than the peripheral annular region.

Abstract: A transistor comprises a nanowire (22, 22?) having a source (24) and a drain (29) separated by an intrinsic or lowly doped region (26, 28). A potential barrier is formed at the interface of the intrinsic or lowly doped region (26, 28) and one of the source (24) and the drain (29). A gate electrode (32) is provided in the vicinity of the potential barrier such that the height of the potential barrier can be modulated by applying an appropriate voltage to the gate electrode (32).

Abstract: The invention suggests a transistor (21) comprising a source (24) and a drain (29) as well as a barrier region (27) located between the source and the drain. The barrier region is separated from the source and the drain by intrinsic or lowly doped regions (26, 28) of a semiconductor material. Potential barriers are formed at the interfaces of the barrier region and the intrinsic or lowly doped regions. A gate electrode (32) is provided in the vicinity of the potential barriers such that the effective height and/or width of the potential barriers can be modulated by applying an appropriate voltage to the gate electrode.

Abstract: A photosensitive device is disclosed which comprises a semiconductor substrate, at least one reverse biased device, such as a P-N junction diode formed in the semiconductor substrate, and at least one photosensitive layer disposed above the semiconductor substrate and substantially covering the reverse biased device, the photosensitive layer releasing electrons and holes when struck by photons, wherein the photon generated electrons and holes in the photosensitive layer reach the reverse biased device and create a combination current therein when a light shines thereon.

Abstract: A device comprising a number of different wavelength-selective active-layers arranged in a vertical stack, having band-alignment and work-function engineered lateral contacts to said active-layers, consisting of a contact-insulator and a conductor-insulator. Photons of different energies are selectively absorbed in or emitted by the active-layers. Contact means are arranged separately on the lateral sides of the vertical stack for injecting charge carriers into the photon-emitting layers and extracting charge carriers generated in the photon-absorbing layers. The device can be used for various applications for light emission or light absorption. The stack of active layers may also include top and bottom electrodes whereby the device can also be operated as a FET device.

Abstract: The present invention relates to a transistor based on resonant tunneling effect of double barrier tunneling junctions comprising: a substrate, an emitter, a base, a collector and a first and a second tunneling barrier layers; wherein the first tunneling barrier layer is located between the emitter and the base, and the second tunneling barrier layer is located between the base and the collector; furthermore, the junction areas of the tunneling junctions which are formed between the emitter and the base and between the base and collector respectively are 1 ?m2˜10000 ?m2; the thickness of the base is comparable to the electron mean free path of material in the layer; the magnetization orientation is unbounded in one and only one pole of said emitter, base and collector. Because the double-barrier structure is used, it overcomes the Schottky potential between the base and the collector.

Abstract: An electron transport device, including at least one transport layer in which at least one periodic dislocation and/or defect array is produced, and a mechanism for guiding electrons in the transport layer.

Abstract: The Bell-state analyzer includes a semiconductor device having quantum dots formed therein and adapted to support Fermions in a spin-up and/or spin-down states. Different Zeeman splittings in one or more of the quantum dots allows resonant quantum tunneling only for antiparallel spin states. This converts spin parity into charge information via a projective measurement. The measurement of spin parity allows for the determination of part of the states of the Fermions, which provides the states of the qubits, while keeping the undetermined part of the state coherent. The ability to know the parity of qubit states allows for logic operations to be performed on the qubits, i.e., allows for the formation of (two-qubit) quantum gates, which like classical logic gates, are the building blocks of a quantum computer. Quantum computers that perform a parity gate and a CNOT gate using the Bell-state analyzer of the invention are disclosed.

Abstract: A Si-based diode (10, 10?, 100) is formed by epitaxially depositing a Si-based diode structure on a silicon substrate. The Si-based diode structure includes a Si-based pn junction (16, 16?, 18, 18?, 30, 32, 160, 161) having a backward diode current-voltage characteristic in which the forward tunneling current is substantially smaller than the backward tunneling current at comparable voltage levels. In some embodiments, the Si-based pn junction includes at least one non-silicon or silicon alloy layer such as at least one SiGe layer (16, 16?, 160, 161). In some embodiments, at least one delta doping (30, 32) is disposed on the silicon substrate in or near the pn junction, that together with the Si-based pn junction define an electrical junction having the backward diode current-voltage characteristic. A large area detector array may include a plurality of such Si-based diodes (10, 10?, 100).

Abstract: The present invention comprises a tunneling device in which the collector electrode is modified so that tunneling of higher energy electrons from the emitter electrode to the collector electrode is enhanced. In one embodiment, the collector electrode is contacted with an insulator layer, preferably aluminum or silicon nitride, disposed between the collector and emitter electrodes. The present invention additionally comprises a method for enhancing tunneling of higher energy electrons from an emitter electrode to a collector electrode, the method comprising the step of contacting the collector electrode with an insulator, preferably aluminum or silicon nitride, and placing the insulator between the collector electrode and the emitter electrode.

Abstract: Structures include a tunneling device disposed over first and second lattice-mismatched semiconductor materials. Process embodiments include forming tunneling devices over lattice-mismatched materials.

Abstract: Methods and systems for depositing nanomaterials onto a receiving substrate and optionally for depositing those materials in a desired orientation, that comprise providing nanomaterials on a transfer substrate and contacting the nanomaterials with an adherent material disposed upon a surface or portions of a surface of a receiving substrate. Orientation is optionally provided by moving the transfer and receiving substrates relative to each other during the transfer process.

Abstract: A method of forming a semiconductor device includes the following steps: providing a plurality of semiconductor layers; providing means for coupling signals to and/or from layers of the device; providing a layer of quantum dots disposed between adjacent layers of the device; and providing an auxiliary layer disposed in one of the adjacent layers, and spaced from the layer of quantum dots, the auxiliary layer being operative to communicate carriers with the layer of quantum dots.

Abstract: A silicon-on-insulator (SOI) memory device (such as an SRAM) using negative differential resistance (NDR) elements is disclosed. Body effect performances for NDR FETs (and other FETs) that may be used in such device are enhanced by floating a body of some/all the NDR FETs.

Abstract: A polarization-dependent device is provided that includes organic materials having electric dipoles. The polarization-dependent device comprises: (a) a source region and a drain region separated by a channel region having a length L, formed on a substrate; (b) a dielectric layer on at least a portion of the channel region; and (c) a molecular layer on the dielectric layer, the molecular layer comprising molecules having a switchable dipolar moiety. Addition of a gate over the molecular layer permits fabrication of a transistor, while omission of the gate, and utilization of suitable molecules that are sensitive to various changes in the environment permits fabrication of a variety of sensors. The molecular transistor and sensors are suitable for high density nanoscale circuits and are less expensive than prior art approaches.

Abstract: An integrated circuit chip includes a formation of integrated layers configured to define at least one integrated electronic component. The integrated layers further define an integrated electron tunneling device, which includes first and second non-insulating layers spaced apart from one another such that a given voltage can be provided thereacross. The integrated electron tunneling device further includes an arrangement disposed between the first and second non-insulating layers and serving as a transport of electrons between and to the first and second non-insulating layers. The arrangement includes at least a first layer configured such that the transport of electrons includes, at least in part, transport by means of tunneling. The integrated electron tunneling device further includes an antenna structure connected with the first and second non-insulating layers, and the integrated electron tunneling device is electrically connected with the integrated electronic component.

Abstract: A tunnel junction structure comprises an n-type tunnel junction layer of a first semiconductor material, a p-type tunnel junction layer of a second semiconductor material and a tunnel junction between the tunnel junction layers. The first semiconductor material includes gallium (Ga), nitrogen (N), arsenic (As) and is doped with a Group VI dopant. The probability of tunneling is significantly increased, and the voltage drop across the tunnel junction is consequently decreased, by forming the tunnel junction structure of materials having a reduced difference between the valence band energy of the material of the p-type tunnel junction layer and the conduction band energy of the n-type tunnel junction layer. Doping the first semiconductor material n-type with a Group VI dopant maximizes the doping concentration in the first semiconductor material, thus further improving the probability of tunneling.

Abstract: The design and operation of a p-i-n device, operating in a sequential resonant tunneling condition for use as a photodetector and an optically pumped emitter, is disclosed. The device contains III-nitride multiple-quantum-well (MQW) layers grown between a III-nitride p-n junction. Transparent ohmic contacts are made on both p and n sides. The device operates under a certain electrical bias that makes the energy level of the first excitation state in each well layer correspond with the energy level of the ground state in the adjoining well layer. The device works as a high-efficiency and high-speed photodetector with photo-generated carriers transported through the active MQW region by sequential resonant tunneling. In a sequential resonant tunneling condition, the device also works as an optically pumped infrared emitter that emits infrared photons with energy equal to the energy difference between the first excitation state and the ground state in the MQWs.

Abstract: A two-terminal NDR device can be formed by coupling the gate and drain of an NDR-capable FET, such that the coupled gate and drain form a first terminal and the source of the NDR-capable FET forms the second terminal. By applying an appropriate body bias between the body and source of an NDR-capable FET configured in this manner, the NDR-capable FET can be forced to operate with a negative threshold voltage, thereby allowing the resulting two-terminal device to exhibit the desired NDR characteristics. This two-terminal device can, for example, be used as a load element in a static random access memory (SRAM) cell and various other circuits where the NDR behavior of the device would be beneficial.

Abstract: Semiconductor quantum well devices and methods of making the same are described. In one aspect, a device includes a quantum well structure that includes semiconductor layers defining interleaved heavy-hole and light-hole valance band quantum wells. Each of the quantum wells includes a quantum well layer interposed between barrier layers. One of the semiconductor layers that functions as a barrier layer of one of the light-hole quantum wells also functions as the quantum well layer of one of the heavy-hole quantum wells. Another of the semiconductor layers that functions as a barrier layer of one of the heavy-hole quantum wells also functions as the quantum well layer of one of the light-hole quantum wells.

Abstract: A light device includes an electron supply defining an emitter surface. A dielectric tunneling layer is disposed between the electron supply and a cathode layer. The cathode layer has at least partial photon transparency that is substantially uniform across the emitter surface.

Abstract: An InGaAlAs-based buried type laser is expected to improve properties of the device, but generates defects at a re-growth interface and is difficult to realize a long-term reliability necessary for optical communication, due to inclusion of Al in an active layer. A semiconductor optical device and an optical module including a package substrate and a semiconductor optical device mounted on the package substrate are provided, whereby there are realized the improvement of device properties and the long-term reliability through the use of an Al composition ratio-reduced tensile strained quantum well layer.