Abstract: The invention relates to a light-sensitive semiconductor component that consists of pixels (1), wherein n doped dot zones (7) are provided, in a preferably hexagonal pattern, on the surface of a p doped channel region, the dot zones (7) of a pixel (1) being electrically connected to one another by means of leads (6) and to a collecting lead (4). The dot zones (7) form parallel connected semiconductor diodes whereby minority charge carriers that are generated by the incidence of light in the channel region can be detected after having traveled to the dot zones (7) by diffusion. The described arrangement enables a high sensitivity to be achieved throughout the channel region and also a minimum capacitance of the semiconductor constructed by means of the CMOS technique. Diffusion of charge carriers out of a pixel is prevented by a guard ring (3) of an opposed type of doping.

Abstract: A substrate exposure apparatus, having a display apparatus and a control system. The display apparatus is used to display the pattern and to transfer the pattern to the photoresist, and includes a non-self luminescent display or a self-luminescent display. The control system is used to control the pattern displayed on the display apparatus.

Abstract: A photodetector is integrated on a single semiconductor chip with bipolar transistors including a high speed poly-emitter vertical NPN transistor. The photodetector includes a silicon nitride layer serving as an anti-reflective film. The silicon nitride layer and oxide layers on opposite sides thereof insulate edges of a polysilicon emitter from the underlying transistor regions, minimizing the parasitic capacitance between the NPN transistor's emitter and achieving a high frequency response.

Abstract: Methods for treating a wafer to protect a fuse box of a semiconductor chip are provided. These methods include applying an insulating coating solution onto the surface of at least one of a plurality of fuse boxes in a semiconductor chip so as to prevent moisture or impurities from seeping into the fuse box. With these methods, the degradation of the semiconductor chip can be substantially reduced by protecting the fuse box from a high-temperature and very humid atmosphere, and impurities such as particles. Thus, characteristics and reliability of the semiconductor chip can be also improved.

Abstract: Minority carriers generated by photoelectric conversion in an isolation layer and a semiconductor region with the same conduction type as that of the isolation layer are provided with an effective diffusion length owing to a trench formed in the isolation layer and with no path, which could be a straight escape route for the minority carriers, and false signals, therefore, scarcely enters to a neighboring cell, so that smear and color interference can be suppressed.

Abstract: A memory array and some addressing circuitry therefor are formed by creating circuit elements at the crossing-points of two layers of electrode conductors that are separated by a layer of a semiconductor material. The circuit elements formed at the crossing-points function as data storage devices in the memory array, and function as connections for a permuted addressing scheme for addressing the elements in the array. In order to construct the addressing circuitry, the electrode conductors are fabricated with a controlled geometry at selected crossing-points such that selected circuit elements have increased or decreased cross-sectional area. By applying a programming electrical signal to the electrodes, the electrical characteristics (e.g. resistance) of selected circuit elements can be changed according to the controlled electrode geometry.

Abstract: An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region (3), and one implantation of a dopant ion that does not influence a position of the p/n junction between the source and drain regions (S and D) and the well region with a shallow implantation depth and a large implantation amount. After conducting an activation heat treatment of the dopant, a surface of the source/drain region is made into cobalt silicide 12, so that the source/drain region (S and D) can have a low resistance, and a p/n junction leakage can be reduced.

Abstract: An imaging circuit (10) is formed on a semiconductor substrate (40) having first and second regions (41, 42) for capturing a light signal (LIGHT) to produce first and second charges, respectively. A conductive material (52, 53) is extended from the first region to the second region for controlling the first and second charges in response to a control signal (COL1, ROW1) to produce an output signal (VOUT) of the imaging circuit.

Abstract: A semiconductor light-emitting unit includes: a semiconductor laser diode; a photodetector functioning as a sub-mount for mounting the diode thereon; and a heating member, incorporated with the photodetector, for heating the diode. If the ambient temperature of the diode falls within a range where kinks are possibly caused in the low-temperature I-L characteristic of the diode, then current is supplied to the heating member, thereby heating the diode. The heating member may be either a doped region defined within a semiconductor substrate or a doped polysilicon film formed on the substrate. Also, the heating member is preferably located under the laser diode with a heat-dissipating layer and an insulating layer interposed therebetween. The semiconductor light-emitting unit with this structure can effectively eliminate kinks from the low-temperature I-L characteristic of the semiconductor laser diode.

Abstract: An electronic component includes two semiconductor chips on an intermediate carrier, which is provided on its underside with external contacts, which are located on a plane with first external contacts on a first active chip surface of the first semiconductor chip. A rear side of the first semiconductor chip faces an active chip surface of the second semiconductor chip. The invention additionally relates to a process for the production of the electronic component.

Abstract: A micro array chip is formed by high-speed injection molding. A chip body has a thickness of 1 mm and each well has a capacity of 1.2 &mgr;L with the bottom having a wall thickness of 250 &mgr;m. An opening of each well is surrounded by an annular protrusion part, which is raised from a surface of the chip body by a height of 200 &mgr;m. The openings of wells may be closed with a sheet of sealant made of aluminum or a resin. An overall shape of the micro array chip is rectangular and is a flat plate with a level bottom surface. Therefore, the micro array chip can be used with a heat block in flat plate form, which is independent of chip specifications such as a number of wells and their shape.

Abstract: A lateral high-breakdown-voltage transistor comprises an n− drain region and an n+ source region formed in a p− silicon substrate, separated from each other, a gate electrode formed on a channel, insulated from the substrate, an n+ drain contact region formed in the drain region, drain wiring electrically connected to the drain region via the drain contact region, a p+ substrate contact region formed in contact with the source region, and source wiring electrically connected to the source region and also connected to the semiconductor layer via the substrate contact region. The transistor is characterized in that the substrate contact regions have respective portions made to be in contact with the source wiring, and accordingly laterally extend from inside the contact surface of the source wiring to outside the contact surface.

Abstract: A light shield film is provided adjacent to an anode of an EL element that consists of the anode, an EL layer, and a cathode. The anode and the cathode are transparent or semitransparent to visible light and hence transmit EL light. With this structure, ambient light is absorbed by the light shield film and does not reach an observer. This prevents an external view from appearing on the observation surface.

Abstract: A cross under metal wiring structure which may prevent “latch-up” from causing at a pnpn-structure is provided. The cross under metal wiring structure comprises a lower wiring provided on a topmost layer of the pnpn-structure isolated in an island by a groove, and an upper wiring connected to the lower wiring through a first contact hole opened in an insulating film covered the isolated pnpn-structure and to a layer just below the topmost layer through a second contact hole opened in the insulating film.

Abstract: Disclosed is a semiconductor structure and manufacturing process for making an integrated FET and photodetector optical receiver on a semiconductor substrate. A FET is formed by forming at least one p channel in a p-well of the substrate and forming at least one n channel in the p-well of the substrate. A p-i-n photodetector is formed in the substrate by forming at least one p channel in an absorption region of the substrate when forming the at least one p channel in the p well of the FET and forming at least one n channel in the absorption region of the substrate when forming the at least one n channel in the p-well of the FET.

Abstract: An epitaxial wafer comprises epitaxial layers 3-6 formed on a main surface of a compound semiconductor single crystal substrate 2, wherein the epitaxial layer 3a on the main surface is exposed in a back surface of the compound semiconductor single crystal substrate 2, and an exposed portion 8 of the epitaxial layer 3a has a carrier concentration of 1×1017 cm−3 to 2×1018 cm−3. The epitaxial wafer provides for an ultra thin type light emitting diode where generation of ohmic electrode failure is suppressed.

Abstract: A microchip (3) is mounted to a chip carrier (1) in such a way as to avoid an earth fault between the chip (3) and the carrier (1). When mounting chips, the chip (3) is placed on a chip carrier (1) that includes an electrically and thermally conductive element (13). The element includes a surface (17) and a recess (15) arranged relative to the surface. The microwave chip (3) is arranged at the surface (17) of the electrically and thermally conductive element (13) by means of a fixing or bonding substance (19), which is disposed at least partially in the recess (15). When mounting the chip, the chip (3) is positioned so that an earth plane (3d) of the microwave chip (3) will lie level with the surface (17) of the electrically and thermally conductive element (13). The chip carrier (1) is suitable for a chip mounting process and can be produced both readily and inexpensively.

Abstract: A semiconductor device that has a p-n junction with a photosensitive region partially having a diffusion region and a non-diffused region when the p-n junction is subjected to a reverse bias voltage. When an incident light (e.g. a laser) is directed at the surface of the photosensitive region, hole-electron pairs are generated in the partial diffusion region within the photosensitive region. As a result, the current through the photosensitive region changes in a substantially linear fashion with the intensity of the incident light. The semiconductor device can be configured in a circuit to provide substantially linear power amplification.

Abstract: A laser fuse comprising of a conventional laser fuse and an NMOS transistor. The two voltage source terminals of the fuse are connected to a low voltage and a high voltage respectively. A laser window is formed on the high voltage source terminal serving as a fuse-breaking port for a laser beam. The gate terminal of the NMOS transistor is connected to a position between the two input terminals of the fuse. One source/drain terminal of the NMOS transistor is connected to an input terminal while the other source/drain terminal of the NMOS transistor is connected to an output terminal. When the fuse is completely broken, the NMOS transistor is non-conductive because a voltage lower than the threshold voltage of the NMOS transistor is supplied to the gate terminal. Even if the fuse is only partially broken, resistance at the second voltage source is increased so much that the voltage at the gate terminal of the NMOS transistor is again lower than the threshold voltage.

Abstract: An integrated optoelectronic circuit chip for optical data communication systems includes a silicon substrate, at least one MOS field effect transistor (MOSFET) formed on a portion of the silicon substrate, and an avalanche photodetector operatively responsive to an incident optical signal and formed on another portion of the substrate. The avalanche photodetector includes a light absorbing region extending from a top surface of the silicon substrate to a depth h and doped to a first conductivity type. The light absorbing region is ionizable by the incident optical signal to form freed charge carriers in the light absorbing region. A light responsive region is formed in the light absorbing region and extends from the top surface of the silicon substrate to a depth of less than h. The light responsive region is doped to a second conductivity type of opposite polarity to the first conductivity type.

Abstract: A semiconductor device that has a p-n junction with a photosensitive region partially having a diffusion region and a non-diffused region when the p-n junction is subjected to a reverse bias voltage. When an incident light (e.g. a laser) is directed at the surface of the photosensitive region, hole-electron pairs are generated in the partial diffusion region within the photosensitive region. As a result, the current through the photosensitive region changes in a substantially linear fashion with the intensity of the incident light. The semiconductor device can be configured in a circuit to provide substantially linear power amplification. The semiconductor device can be configured by itself or with a complimentary device to form push-pull operations.

Abstract: On a liquid crystal display device (80) comprising a first substrate (81) and a second substrate (82) with electrodes (83, 84), formed thereon, respectively, and liquid crystal (85) sealed thereinbetween, a semiconductor device (1) for driving the liquid crystal display device (80) is mounted. The semiconductor device (1) is provided with a plurality of bumps (24), each electrically conductive with respective electrode pads provided on the upper surface of a semiconductor chip (12) with an integrated circuit formed thereon, through the intermediary of respective lower electrodes, provided so as to stretch over the upper surface and two sidewall faces of the semiconductor chip (12), respectively.

Abstract: A method and apparatus for providing a meshed power and signal bus system on an array type integrated circuit that minimizes the size of the circuit. In a departure from the art, through-holes for the mesh system are placed in the cell array, as well as the peripheral circuits. The power and signal buses of the mesh system run in both vertical and horizontal directions across the array such that all the vertical buses lie in one metal layer, and all the horizontal buses lie in another metal layer. The buses of one layer are connected to the appropriate bus(es) of the other layer using through-holes located in the array. Once connected, the buses extend to the appropriate sense amplifier drivers. The method and apparatus are facilitated by an improved subdecoder circuit implementing a hierarchical word line structure.

Abstract: A high emission intensity group-III nitride semiconductor light-emitting device obtained by eliminating crystal lattice mismatch with substrate crystal and using a gallium nitride phosphide-based light emitting structure having excellent crystallinity. A gallium nitride phosphide-based multilayer light-emitting structure is formed on a substrate via a boron phosphide (BP)-based buffer layer. The boron phosphide-based buffer layer is preferably grown at a low temperature and rendered amorphous so as to eliminate the lattice mismatch with the substrate crystal. After the amorphous buffer layer is formed, it is gradually converted into a crystalline layer to fabricate a light-emitting device while keeping the lattice match with the gallium nitride phosphide-based light-emitting part.

Abstract: Grey scale linearity and power efficiency in active matrix (O) LEDs are enhanced by storing the grey value in a memory circuit, coupled to an adjusting circuit, preferably via a current mirror.

Abstract: A circuit (20) includes a resistor (26) and a current source (32) for raising the voltage of the source of the N-channel transistor in order to keep the base-emitter voltage of the parasitic bipolar device from forward biasing to prevent conduction in the parasitic bipolar device. In one embodiment, a relatively small resistor (26) is coupled between the source of an N-channel transistor (24) and ground. The current source (32) is used to direct some of the ESD current from a positive ESD event through the small source resistor (26) so that the source of the N-channel transistor (24) is elevated during the event, thus preventing snapback of the parasitic bipolar device.

Abstract: Device layouts are described which increase the photon current of a metal oxide semiconductor image sensor. The metal oxide semiconductor can be NMOS, PMOS, or CMOS. The key part of the photon current of the image sensors comes from the depletion region at the PN junction between the drain region and the substrate material. The layouts used significantly increase the area of this depletion region illuminated by a stream of photons. The layouts have a drain region which takes the shape of a number of parallel fingers perpendicular to the gate electrode, a number of parallel fingers parallel to the gate electrode, or a spiral. The drain regions of these layouts significantly increase the area of the drain depletion region illuminated by a stream of electrons.

Abstract: Thin-film switching elements (20,21) of a display device or the like include a first electrode (22,23) on a substrate (11) and a layer of switching material (24,25) on the first electrode. These switching elements may be semiconductor PIN or Schottky diodes, or MIMs, or TFTs. The switching material is typically .alpha.-Si:H in the case of the semiconductor diodes and TFTs, and tantalum oxide or silicon nitride in the case of the MIMs. An auxiliary layer (28,29) of insulating material is provided between the first electrode (22,23) and the layer of switching material (24,25), leaving an edge (30,31) of the first electrode uncovered, so that the layer of switching material is connected to this edge only. The switching elements with this construction can be patterned using an inexpensive proximity printer, and have a low capacitance value, so counter-acting kickback and crosstalk which can occur in a switching matrix, e.g in the display of television pictures.

Abstract: The invention provides a method for producing wiring and contacts in an integrated circuit including the steps of forming insulated gate components on a semiconductor substrate; applying a photo-reducible dielectric layer to cover the substrate; etching holes and forming contacts; photo-reducing the dielectric to increase its conductivity; covering the resulting structure with an interconnect layer; etching the interconnect layer to define wiring in electrical contact with the contacts; and oxidizing the dielectric to reduce its conductivity.

Abstract: A light-receiving element includes a semiconductor substrate of a first conductivity type; a first semiconductor layer of a second conductivity type which is formed in a predetermined region on a surface of the semiconductor substrate of the first conductivity type; and at least one semiconductor region of the first conductivity type which is formed so as to extend from an upper surface of the first semiconductor layer of the second conductivity type to the surface of the semiconductor substrate of the first conductivity type, thereby dividing the first semiconductor layer of the second conductivity type into a plurality of semiconductor regions of the second conductivity type. In the light-receiving element, a specific resistance of the semiconductor substrate of the first conductivity type is set in a predetermined range such that a condition Xd.gtoreq.

Abstract: A photoelectric conversion device suitable for use as an element of a photodetector array includes a photodiode for generating a first signal charge in response to incident light, an output unit including a JFET, and at least one transistor having an electrode that generates a second signal charge in response to incident light. The first and second signal charges may be output separately or combined. The second signal charge, or the first and second signal charges combined, may be monitored during an exposure time to determine the desired end of the exposure. An image sensor array may have one or more pixels with such light monitoring capability. The output signal for monitoring the light may be output over a reset drain interconnection, directly from the monitoring pixel or through other pixels via inter-pixel MOSFETS. Exposure time may be controlled, by timing a shutter or a strobe or the like, based on the monitored accumulation of signal charge during exposure.

Abstract: A radiation imager is disclosed that is resistant to degradation due to moisture by either contact pad corrosion, guard ring corrosion or by photodiode leakage. A contact pad of a large area imager is disclosed that is formed into three distinct and electrically connected regions. The resulting structure of the contact pad regions forms reliable contact that is resistant to corrosion damage. Also disclosed is a data line of an imager, or a display, the resistance of which is reduced by patterning an aluminum (Al) line on top of a transistor island structure, with the formed data line preferably being encapsulated. In addition, a guard ring having first and second regions and photosensitive element are disclosed. The second region comprises an electrical contact between ITO and underlying metal and a second tier which acts as a moisture barrier and is preferably disposed at the corner of the guard ring and separated from the contact pads of the imager in such a manner as to minimize corrosion.

Abstract: A method for designing an integrated circuit having optical inputs and outputs includes the step of selecting an integrated circuit design which includes at least one circuit cell design for processing electric signals. The circuit cell design has a predetermined number of electric inputs and electric outputs. The integrated circuit design also includes a plurality of layers of metalization for providing electric coupling. After the electronic integrated circuit design is selected, a predetermined number of optical input devices are located on the circuit cell design in a first prearranged orientation. The predetermined number of optical input devices is no greater than the predetermined number of electric inputs to the circuit cell. Also after the electronic circuit design is selected, a predetermined number of optical output devices are located on the circuit cell design in a second prearranged orientation.

Abstract: The present invention is a active pixel sensor cell and method of making and using the same. The active pixel sensor cell approximately doubles the available signal for a given quanta of light. The device of the present invention utilizes the holes produced by impinging photons in a active pixel sensor cell circuit. Two active pixel sensor cell circuits, an NFET circuit and PFET circuit are created for use with a photodiode. The NFET circuit captures electron current. The PFET circuit captures hole current. The sum of the currents is approximately double that of conventional active pixel sensor circuits using similarly sized photodiode regions.

Abstract: A color active pixel sensor cell is formed by utilizing four photodiodes which are each covered with a layer of oxide. The thicknesses of the layers of oxide are set so that a first layer of oxide prohibits red light from entering the first photodiode, a second layer of oxide prohibits green light from entering the second photodiode, a third layer of oxide prohibits blue light from entering the third photodiode, and a fourth layer of oxide allows visible light to enter the fourth photodiode. The amount of red light received by the cell is then determined by subtracting the light energy collected by the first photodiode from the light energy collected by the fourth photodiode. Similarly, the amount of green and blue light received by the cell is determined by subtracting the light energy collected by the second and third photodiodes, respectively, from the amount of light energy collected by the fourth photodiode.

Abstract: A photoelectric conversion element includes a photoelectric conversion portion for generating and storing a charge according to incident light, an amplifying portion having a control region for generating a signal output according to the charge received in the control region from the photoelectric conversion portion, a transfer control portion for transferring the charge generated and stored in the photoelectric conversion portion to the control region of the amplifying portion, a reset-purpose charge draining region for draining the charge transferred to the control region of the amplifying portion, and a reset-purpose control region for controlling the reset-purpose charge draining region. A reset operation can be performed without operating the amplifying portion. Also, a photoelectric conversion apparatus having high sensitivity and low dissipation power can be obtained.

Abstract: An active matrix OED array includes an array area defined on a semiconductor substrate defining rows and columns of pixels and driver areas spaced from the array area with driver circuits including row drivers coupled to row buses and column drivers coupled to column buses formed in the driver areas. An active control circuit and an OED are formed in each pixel of the array area and coupled to a row and a column bus adjacent each pixel. A second substrate is formed of light transmissive material and includes externally accessible electrical connectors coupled to the driver circuits. The semiconductor substrate includes a first bump pad encircling the array area and the second substrate includes a mating second bump pad with the first and second bump pads engaged to seal the array area.

Abstract: A light-emitting-diode array includes a non-doped compound semiconductor layer between a substrate and a first compound semiconductor layer. A plurality of isolation regions extend from the first compound semiconductor layer to the surface of the non-doped compound semiconductor layer, and provide separation into isolated block regions each containing an equal number of diffusion regions. A plurality of shared electrode lines are connected to the diffusion regions in a plurality of the block regions, in such a relationship that diffusion regions selected from each of the block regions are connected to a common shared electrode. At least a surface portion of the substrate is formed of silicon. The density of the diffusion regions can be increased without increasing the number of the electrode pads. Moreover, the substrate is free from breakage or cracks.

Abstract: A tunable antenna-coupled intersubband terahertz (TACIT) detector is based on intersubband absorption in doped semiconductor quantum wells. THz-frequency radiation impinges on a coplanar antenna. The antenna couples radiation into a narrow constriction in a two dimensional electron gas (the "active region") with electric field perpendicular to the plane of the antenna. Radiation, which is at the intersubband absorption frequency, is absorbed in the active region. The resulting change in resistance through the constriction is detected. The frequency of the absorption, and hence the detection frequency, can be tuned over the 1-5 THz range by applying small voltages between a front and back gate. The efficiency with which radiation couples from the antenna into the active region can be optimized at each frequency.TACIT detectors solve a number of outstanding problems associated with Terahertz detection including:1.

Abstract: Optoelectronic devices such as photodetectors, modulators and lasers with improved optical properties are provided with an atomically smooth transition between the buried conductive layer and quantum-well-diode-containing intrinsic region of a p-i-n structure. The buried conductive layer is grown on an underlying substrate utilizing a surfactant-assisted growth technique. The dopant and dopant concentration are selected, as a function of the thickness of the conductive layer to be formed, so that a surface impurity concentration of from 0.1 to 1 monolayer of dopant atoms is provided. The presence of the impurities promotes atomic ordering at the interface between the conductive layer and the intrinsic region, and subsequently results in sharp barriers between the alternating layers comprising the quantum-well-diodes of the intrinsic layer.

Abstract: A photo FET device having a large area backside optical energy reception surface is disclosed. The photo FET device is fabricated in the source gate and drain upward configuration and then inverted onto a new permanent substrate member and an original surrogate substrate member removed in order to expose the active area backside optical energy reception surface. Electrical characteristics including curve tracer electrical data originating in both dark and illuminated devices and devices of varying size and both depletion mode and enhancement mode operation are also disclosed. Fabrication of the device from gallium arsenide semiconductor material and utilization for infrared energy transducing in a number of differing electronic applications are also disclosed.

Abstract: A semiconductor detector structure consists of a unipolar or single-pole nsistor disposed or arranged on a substantially depleted semiconductor body, with a drain, a source, a resetting contact, a top gate and a potentially floating layer forming at least one gate of the unipolar transistor, as well as at least one capacitor. The source is directly connected to the first electrode or electrodes of the capacitor or capacitors. The capacitor or the capacitors are integrated jointly with or into the semiconductor structure.

Abstract: In a light receiving element and a semiconductor device manufacturing method, the low density PN junction is formed by constructing the internal composition of the photodiode with N.sup.+ type diffusion layer, N.sup.- type epitaxial layer, P.sup.- type epitaxial layer, P.sup.+ type deposit layer, and P type Si from the light receiving surface, the vacant layer to be occurred when the photodiode is reverse biased will be widened and the light receiving sensitivity and the frequency characteristic will be improved. Furthermore, since the separation of bipolar elements will be conducted by P.sup.- epitaxial layer, the efficiency in density control at the time of P.sup.- type epitaxial growth can be improved.

Abstract: A light sensitive semiconductor device (10) is formed in a well region (12) in a semiconductor substrate (11). A first voltage (30) is applied to a source region (4) of the semiconductor device (10) and to a contact region (13) to the well region (12) to attract holes. A second voltage (31) is applied to the source region (14) and a drain region (16) to provide a current flow. As photons (23) from a light source are absorbed by semiconductor device (10), the source to drain current is decreased.

Abstract: Solid state image sensor which can improve photic sensitivity of photodiodes by providing only one transmission line between the photodiodes, leading to reduction of width of the transmission line passing between the photodiodes, including a substrate, photodiodes formed on the substrate, a first to a fourth transmission gates arranged in sequence by four for every two photodiodes on a part of the substrate on one side of each of the photodiode, a first, and a second transmission lines arranged one by one alternatively extended at length on the substrate between adjacent photodiodes connected to the first, and the second transmission gates respectively for applying a first, and a second driving clock signals, respectively, a first contact formed at the third transmission gate, a second contact formed at the fourth transmission gate, and a third, and a fourth transmission lines formed over the transmission gates in parallel at length connected through the third, and the fourth transmission gates and the first,

Abstract: An FET or MESFET having a semiconductor optically transparent gate. A substrate having a doped channel placed thereon together with a source and a drain with a semiconductor gate formed therebetween may be manufactured using conventional semiconductor manufacturing techniques. The optically transparent highly doped semiconductor gate forms an n+-n junction with the n-type doped channel. This junction is modulated or changed by an optical signal causing a photovoltaic effect that reduces the barrier potential at the n+-n junction resulting in a depletion of the accumulation region. This results in increased flow of current in the doped channel. The transparent highly doped semiconductor gate increases performance of the FET or MESFET optical detector. This is an improvement over conventional metal semiconductor field-effect transistor (MESFET) technology, and can be applied to microwave monolithic integrated circuits (MMIC).

Abstract: An optically coupled FET comprised of bottom layer, a top layer in which FET is formed and an intermediate layer having a waveguide communicating with a grating in registration with the FET.

Abstract: An amplification-type photoelectric conversion device utilizes a JFET and is capable of amplifying charges generated by photoelectric conversion with a high amplification factor and improves the S/N ratio. The device is provided with a drive circuit for respectively applying driving signals to a source region, a drain region and a gate electrode of the JFET. The drive circuit has a first signal mode for accumulating charges generated by incident light on the JFET, and a second signal mode for causing the flow of current between the source and the drain and raising a potential difference between the source and the drain to a high level thereby causing an impact-ionization effect corresponding to an amount of the charges accumulated by the first mode to accumulate the resulting charges. A signal output corresponding to a total amount of the charges accumulated by the first and second modes is delivered from the drain.

Abstract: This invention provides an opto-electronic integrated circuit for receiving optical signals as well as method for manufacturing the same in which both the receipt sensitivity and reliability are improved to achieve both high operation speed and process simplicity. This is accomplished by integrating the photo-detector and the amplifier on a single chip, which are essential elements of the optical receiver of the optical communication system. Also, layer between a PIN photo-detector and a junction-field effect transistor (JFET) is shared as large as possible through a two times epitaxial growth. In this way, the opto-electronic integrated circuit is optimized.

Abstract: An application-type solid state imaging device which includes a plurality of picture elements arranged in a two-dimensional matrix. A sensor region is surrounded by a substrate and a gate region is positioned laterally substantially about the sensor region. A source region is formed through one surface of the substrate and aligned vertically with the sensor region, while a drain is formed at an opposing surface of the substrate and is likewise aligned with the sensor region. The sensor region and the gate region together define a channel through which source-drain current flows. Light incident on the substrate passes therethrough to the sensor region where charge accumulates photoelectrically for producing an image signal by controlling the source-drain current in proportion to the magnitude of the photoelectrically accumulated charge. The device is reset after reading by removing charge accumulated in the sensor region through the gate region.