Employing Resonant Tunneling Patents (Class 257/25)
  • Patent number: 5280182
    Abstract: According to this invention, a resonant tunneling transistor includes a first semiconductor layer having an n-type conductivity and serving as a collector layer, a second semiconductor layer having a p-type conductivity and serving as a base layer, a third semiconductor layer having the n-type conductivity and serving as an emitter layer, a fourth semiconductor layer serving as a first barrier layer against either of electrons and holes in the first and second semiconductor layers, and a fifth semiconductor layer serving as a second barrier layer against either of electrons and holes in the second and third semiconductor layers. The first, second, third, fourth, and fifth semiconductor layers are sequentially stacked in an order of the first, fourth, second, fifth, and third semiconductor layers.
    Type: Grant
    Filed: April 20, 1992
    Date of Patent: January 18, 1994
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventor: Takao Waho
  • Patent number: 5270225
    Abstract: A resonant tunneling semiconductor device having two large bandgap barrier layers (12, 14) separated by a quantum well (13) is provided. The two barriers (12,14) and the quantum well (13) are formed between first and second semiconductor layers (11, 16) of a first conductivity type. A monolayer (17) of material having a different bandgap than the quantum well material is provided in the quantum well thereby lowering the ground state energy level of the quantum well. Alternatively, monolayers (18, 19) having a different bandgap than that of the first and second semiconductor layers (11, 16) are formed in the first and second semiconductor layers, respectively, outside of the quantum well (13).
    Type: Grant
    Filed: February 21, 1992
    Date of Patent: December 14, 1993
    Assignee: Motorola, Inc.
    Inventors: Herbert Goronkin, Jun Shen, Saied Tehrani
  • Patent number: 5266814
    Abstract: A resonant-tunneling transistor comprises a first semiconductor layer acting as a collector, a second semiconductor layer provided on the first semiconductor layer and forming a potential barrier of electrons in the conduction band, a third semiconductor layer provided on the second semiconductor layer and forming a quantum well of electrons in the conduction band, a fourth semiconductor layer provided on the third semiconductor layer and forming a quantum well of holes in the valence band, the fourth semiconductor layer simultaneously forming a potential barrier of electrons in the conduction band, a fifth semiconductor layer provided on the fourth semiconductor layer acting as an emitter, a first electrode provided in contact with the first semiconductor layer for recovering electrons therefrom, a second electrode provided in contact with the fifth semiconductor layer for injecting electrons thereinto, and an optical passage for introducing an optical beam to the first semiconductor layer.
    Type: Grant
    Filed: September 10, 1991
    Date of Patent: November 30, 1993
    Assignee: Fujitsu Limited
    Inventors: Tsuguo Inata, Shunichi Muto
  • Patent number: 5243198
    Abstract: A semiconductor radio-frequency power detector comprises, in a stack, an ohmic contact layer, undoped layer of a first semiconductor material, such as GaAs, of thickness l.sub.1, an undoped layer of a second semiconductor material, such as AlGaAs, of larger band gap than the first semiconductor material, the thickness of the layer being such that transport in the layer is primarily by intraband tunnelling, a second undoped layer of the first semiconductor material of thickness l.sub.2, where l.sub.2 >20l.sub.1, and a second ohmic contact layer. The difference between the thicknesses of the layers of the first semiconductor material gives rise to asymmetry in the current density/applied voltage characteristic for the device. An n+ layer may be incorporated in the second layer of the intrinsic first material to reduce "band bending" and to increase the current density.
    Type: Grant
    Filed: June 10, 1992
    Date of Patent: September 7, 1993
    Assignee: GEC - Marconi Limited
    Inventors: Richard T. Syme, Michael J. Kelly, Nigel R. Couch
  • Patent number: 5233205
    Abstract: A novel concept and structure of a semiconductor circuit are disclosed which utilize the fact that the interaction between the carriers such as electrons and holes supplied in a meso-scopic region and the potential field formed in the meso-scopic region leads to such effects as quantum interference and resonance, with the result that the output intensity is changed.
    Type: Grant
    Filed: June 22, 1992
    Date of Patent: August 3, 1993
    Assignee: Hitachi, Ltd.
    Inventors: Toshiyuki Usagawa, Shirun Ho, Ken Yamaguchi, Yoshiaki Takemura
  • Patent number: 5229623
    Abstract: A semiconductor device is disclosed, which includes a multiple negative differential resistance element having negative differential resistance characteristics at at least two places in the current-voltage characteristics, and which is suitable for constructing a neural network having a high density integration and a high reliability.
    Type: Grant
    Filed: August 13, 1991
    Date of Patent: July 20, 1993
    Assignee: Hitachi, Ltd.
    Inventors: Tomonori Tanoue, Hiroshi Mizuta, Susumu Takahashi
  • Patent number: 5225692
    Abstract: A non-linear semiconductor optical device comprises a first quantum well layer having discrete quantum levels of carriers including a first quantum level for electrons and a second quantum level for holes with an energy gap corresponding to a wavelength of an incident optical beam; a pair of barrier layers provided above and below the first quantum well layer in contact therewith with a thickness that allows a tunneling of the carriers therethrough for defining a potential well in correspondence to the first quantum well layer; and a second quantum well layer provided in contact with the barrier layers for accepting the carriers that have been created in the first quantum well layer upon excitation by the incident optical beam and escaped therefrom by tunneling through the barrier layer. The second quantum well layer comprises a material that has a conduction band including therein a .GAMMA. valley and an X valley, wherein said .GAMMA.
    Type: Grant
    Filed: March 27, 1992
    Date of Patent: July 6, 1993
    Assignee: Fujitsu Limited
    Inventors: Atsushi Takeuchi, Hideaki Ishikawa, Shunichi Muto
  • Patent number: 5216261
    Abstract: A non-linear optical device having the TBQ structure comprises an active layer forming a quantum well for interacting with an incident optical beam, an electron removal layer provided adjacent to the active layer at a first side thereof with a first barrier layer intervening therebetween for removing the electrons from the active layer; and a hole removal layer provided adjacent to the active layer at a second, opposite side of the active layer with a second barrier layer intervening therebetween for removing the holes from the active layer; wherein the first and second barrier layers have respective thicknesses determined such that the probability of tunneling of the electrons through the first barrier layer and the probability of tunneling of the holes through the second barrier layer are substantially equal with each other.
    Type: Grant
    Filed: December 19, 1991
    Date of Patent: June 1, 1993
    Assignee: Fujitsu Limited
    Inventors: Tsuguo Inata, Shunichi Muto
  • Patent number: 5216262
    Abstract: A quantum well structure useful for semiconducting devices comprises two barrier regions and a thin epitaxially grown monocrystalline semiconductor material quantum well sandwiched between said barrier regions. Each barrier region consists essentially of alternate strain layers forming a superlattice, each of said layers being thinner than said quantum well. The layers are so thin that no defects are generated as a result of the release of stored strain energy.
    Type: Grant
    Filed: March 2, 1992
    Date of Patent: June 1, 1993
    Inventor: Raphael Tsu
  • Patent number: 5162877
    Abstract: A semiconductor integrated circuit device comprising a negative differential resistance element, such as an RHET and RBT, and a field effect transistor, such as an SBFET and heterojunction type FET, which are formed on the same semiconductor substrate, a base layer of the negative differential resistance element and a channel layer of the field effect transistor being formed on the same epitaxial layer, and the same conductive material is used to simultaneously form an emitter electrode and a gate. A monolithic integration of both the element and transistor can be achieved both rationally and easily.
    Type: Grant
    Filed: April 30, 1991
    Date of Patent: November 10, 1992
    Assignee: Fujitsu Limited
    Inventor: Toshihiko Mori