Abstract: A semiconductor device comprises mutually separated first and third barrier layers interposed between the first and second patterned terminals. The device operates by the resonant tunneling of carriers from the second terminal to the first terminal. The first terminal is patterned into a section and a plurality of layers comprising the mutually separated first and second barrier layers are formed on top of the first terminal. A second terminal is then formed on top of the plurality of semiconductor layers. The second terminal is then patterned so that it only overlies the first terminal in confined region. A front-gate is then formed on top of the patterned second terminal.

Abstract: A semiconductor integrated circuit comprising a first functional block consisting essentially of a first circuit which includes a small junction device, and a second functional block consisting essentially of a second circuit which includes a field effect transistor, the second functional block being mutually connected to the first functional block.

Abstract: A method of fabricating ultra-small semiconductor devices including providing a mesa on a substrate. A plurality of overlying layers of semiconductor material are grown in overlying relationship to the mesa so that a perpendicular discontinuity is produced in the layers at the mesa sidewall and the first layer overlying the mesa is in contact with the last layer overlying the substrate adjacent the mesa. A spacer of nonconductive material is formed on the discontinuity and the plurality of overlying layers are etched, using the spacer as a mask, so as to form a contact area overlying the mesa and a contact area overlying the substrate adjacent the mesa, and a semiconductor device positioned adjacent the sidewall beneath the spacer and between the contact areas.

Abstract: A memory system is organized as a matrix including a memory cell at each intersection of a bit line with write and read word lines. Each memory cell comprises a first FET 20 having its gate coupled to a write word line and its drain coupled to a bit line, a second FET 22 having its source coupled to the bit line and its drain coupled to a read word line, and first and second negative resistnce devices 24,26 coupled in series between a supply voltage and a substrate voltage, the common point SN of the series-connected negative resistance devices being coupled to the source of the first FET and to the gate of the second FET. Preferably, the first FET 20 is a p-channel device, the second FET 22 is an n-channel device, and the first and second negative resistance devices 24,26 are RTDs. In a second embodiment, a memory system has a memory cell at each intersection of a bit line with a word line.

Abstract: A quantization functional device includes: a silicon thin layer having a first surface and a second surface each made of a predetermined crystal surface, and the silicon thin layer being formed of single crystalline silicon having a thickness sufficiently thin to function as a quantum well; a pair of tunnel barriers respectively provided on the first and second surfaces of the silicon thin layer; and a first electrode and a second electrode operatively coupled to each other and formed so as to interpose the silicon thin layer and the pair of the tunnel barriers therebetween.

Abstract: The present invention relates to a semiconductor photoelectric device including a InAs layer formed to monoatomic thickness sandwiched between spacer layers adjacent to an emitter to maximize a difference in energy between two quantum states in accumulation layer of a resonant tunneling diode having a double barrier structure, resulting in separating the resonant tunneling current determined by two quantum states of the triangular well in accumulation layer of resonant tunneling diode, even when light of a low intensity is irradiated to the surface of the resonant tunneling diode. Thus, there is provided an optical controlled resonant tunneling diode, making it possible to manufacturing a switching device for controlling an electric signal using light source by adjusting, using light, the resonant tunneling determined by an excited state of the triangular well.

Abstract: There is provided a negative differential resistance amplifier comprising a negative differential resistance transistor having negative input conductance by utilizing resonant tunneling effect. The transistor is electrically connected to a signal source circuit in cascade, and the following relation is established in the negative differential resistance amplifier:0<gs-gi<Gwherein gs (gs>0) indicates a conductance measured when viewed from an interface between the negative differential resistance transistor and the signal source circuit to the signal source circuit, -gi (gi>0) indicates a conductance of the negative differential resistance transistor, and G (G<gs) indicates a predetermined conductance. The above mentioned negative differential resistance amplifier provides not only excellent signal unilaterality, but also higher gain, lower noise and wider band by setting certain matching conditions between the negative differential resistance transistor and the signal source circuit.

Abstract: The present invention is to solve the problems caused in various methods used to improve the performance of the device by improvement of conventional base layer. The present invention discloses a hot electron device which can improve the performance of the device such as the improvement in the current density and decrease in transition time by reducing the dispersion phenomenon by introducing indium arsenide layer having v-shape conduction band due to the graded composition as the base layer of hetero structure hot electron device (HET).In addition, the present invention discloses a resonant tunneling hot electron device which is constructed by adding an emitter electron projection layer to the hot electron device of the present invention so that the Fermi energy and alignment can occur due to the stark shift and the projection of hot electron to the base region can occur through the Fermi energy and alignment.

Abstract: Apparatus for optical communications (10, 110, 210) includes a low-temperature grown photoconductor (12, 140, 220) coupled to at least one resonant tunneling device (14, 120, 130, 230, 240). When exposed to an input light, low-temperature grown photoconductor (10, 110, 210) absorbs photons, which decreases the resistivity, and thus the resistance of the photoconductor. This decrease in resistance causes a decrease in the voltage drop across photoconductor (12, 140, 220), which causes a corresponding increase in the voltage drop across resonant tunneling device (14, 120, 130, 230, 140).

Abstract: On a first cladding layer formed of n-type Al.sub.0.7 Ga.sub.0.3 P, an active region having a staggered-type (type II) heterojunction superlattice structure is disposed. The active region includes 50 light emitting layers formed of Al.sub.0.1 Ga.sub.0.9 P doped with nitrogen and 50 barrier layers formed of Al.sub.0.7 Ga.sub.0.3 P. The 50 light emitting layers and the 50 barrier layers formed of such materials are stacked alternately to form 50 pairs. On the active region, a second cladding layer formed of Al.sub.0.1 Ga.sub.0.9 P is disposed. In the formation of the active layers the composition of the light emitting layer and the barrier layer end the thickness of the barrier layer are controlled so that the isoelectronic level in the light emitting layer and the quantum level in the barrier layer will fulfill the resonance conditions.

Abstract: A lateral resonant tunneling transistor having two non-symmetric quantum dots is disclosed. When a negative voltage is supplied to each plurality of thin split gates, two non-symmetric quantum dots are formed owing to the formation of the potential barrier. Thus when a forward bias voltage is applied, the resonant tunneling phenomena occur twice successively. Through these two successive resonant tunneling phenomena and by lowering the height of the third potential barrier 6a, the resonant tunneling current can be maximized.

Abstract: A light emitting device made of semiconducting materials. The device has an optical microcavity which supports a resonant mode of predetermined photon energy. Within the cavity is a quantum well of predetermined thickness and energy depth. The quantum well is designed such that it forms bound electron, exciton, lower polariton, and hole energy states of predetermined energy. The energy of an exciton state is set to equal the predetermined photon energy of the microcavity mode such that polariton states are created. A means is provided for resonantly tunneling electrons into a quantum well energy state. In a first embodiment, electrons resonantly tunnel into an electron energy state. In a second embodiment, electrons resonantly tunnel into an exciton energy state, during which tunneling the electrons simultaneously fuse with holes to form excitons.

Abstract: A resonant tunneling diode stack used as a memory cell stack (X0-Xn) with sequential read out of bits of data cells (X1-Xn) by increasing ramp rates to transfer the stored bit to a lowest ramp rate cell (X0).

Abstract: The present invention relates to a semiconductor device in which an electric resistance in a carrier path is modulated by changing a voltage applied to the carrier path. The semiconductor device is provided with a semiconductor layer in which conductive particles are dispersed to scatter carriers, a first electrode, and a second electrode for passing the carriers through the semiconductor device in cooperation with the first electrode.

Abstract: A semiconductor device has a semiconductor substrate, a source and a drain region, each formed at the surface of said semiconductor substrate, and each having a potential barrier with respect to the semiconductor substrate. A gate electrode is formed on the semiconductor substrate and positioned between the source and drain regions. The gate electrode controls the height of discrete energy levels of carriers of said semiconductor substrate, and provides a conduction state and a non-conduction state depending upon the existence or non-existence of resonant tunneling current flow.

Abstract: A quantum box structure and a carrier conductivity modulating quantum device are disclosed. The quantum box structure comprises a quantum boxes array including a plurality of quantum boxes arranged adjacent to each other on a common plane. Each quantum box is asymmetric in a direction orthogonal to the plane in one of composition of materials constituting the quantum box and geometry of the quantum box. The carrier conductivity modulating quantum device comprises a plurality of regions including quantum boxes arrays including a plurality of quantum boxes arranged on a common plane. Each regions exhibits at least one of a metal phase and an insulator phase. Each quantum box is asymmetric in a direction orthogonal to the plane at least in one of composition of materials constituting the quantum box and geometry of the quantum box.

Abstract: A new high-speed resonant tunneling device, namely, a long-period superlattice resonant tunneling transistor, is developed according to the invention. The structure of the proposed 20-period superlattice resonant tunneling transistor consists of an InP substrate, a buffer layer formed by GaInAs material on the substrate, a collector layer formed by GaInAs material on the buffer layer, a base layer formed by GaInAs material on the collector layer, an emitter layer formed by GaInAs material on the base, a 20-period superlattice resonant tunneling layer formed by AlInAs and GaInAs materials on the emitter layer, and an ohmic contact layer formed by GaInAs material on the 20-period superlattice resonant tunneling layer. Furthermore, the emitter region includes a 20-period AlInAs/GaInAs superlattice and an emitter layer. Due to the presence of an emitter-base homojunction, collector-emitter offset voltage (V.sub.CE,offset) can be reduced significantly. In addition, the valence band discontinuity (.DELTA.

Abstract: A double electron layer tunneling device is presented. Electrons tunnel from a two dimensional emitter layer to a two dimensional tunneling layer and continue traveling to a collector at a lower voltage. The emitter layer is interrupted by an isolation etch, a depletion gate, or an ion implant to prevent electrons from traveling from the source along the emitter to the drain. The collector is similarly interrupted by a backgate, an isolation etch, or an ion implant. When the device is used as a transistor, a control gate is added to control the allowed energy states of the emitter layer. The tunnel gate may be recessed to change the operating range of the device and allow for integrated complementary devices. Methods of forming the device are also set forth, utilizing epoxy-bond and stop etch (EBASE), pre-growth implantation of the backgate or post-growth implantation.

Abstract: Resonant-tunneling transmission lines in the various architectures rely on discrete or continuous resonant-tunneling heterostructures to actively modify propagating logic signals. One embodiment utilizes amplification of logic signals to counteract ubiquitous losses and distortion associated with any transmission medium. Basically, the logic signal is incrementally reamplified and reshaped as it propagates along the transmission line. Another embodiment is directed to a clocking system that transmits a signal represented by a sinusoid. Then, in proximity to the logic gates or modules, the sinusoid is converted into a square wave that actually clocks the gates and other logic structures. The inventive active transmission line naturally performs this feature, thus enabling clock signal transmission over longer links coupled with sinusoid-to-square wave conversion in a limited area. Still other embodiments implement step or continuous variations in the physical width of the resonant-tunneling transmission line.

Abstract: A semiconductor functional device includes a semi-insulating semiconductor substrate; a resonant tunneling structure which includes, on the substrate, an n-type collector layer, an epitaxial multilayer structure including a double barrier structure constituted of a plurality of barrier layers holding a well layer therebetween, and an n-type emitter layer; an emitter electrode formed on the emitter layer; and a collector electrode formed on the collector layer. An undoped semiconductor barrier layer is interposed between the semi-insulating semiconductor substrate and the collector layer.

Abstract: A memory device consists of an array of resonant tunnel diodes in the form of pillars which are formed by selective etching. Each pillar includes first and second barriers (B1, B2) disposed between terminal regions (T1, T2) and a conductive region (CR1) between the barriers. The diameter of the pillars is typically of the order of 20-50 nm and is sufficiently small that the device exhibits first and second relatively high and low stable resistive states in the absence of an applied voltage between the terminal regions. The device can be used as a non-volatile memory at room temperature.

Abstract: A resonant tunneling diode (400) made of a silicon quantum well (406) with silicon oxide tunneling barriers (404, 408). The tunneling barriers have openings (430) of size smaller than the electron wave packet spread to insure crystal alignment through the diode without affecting the tunneling barrier height.

Abstract: A step junction is provided for superconductor/semiconductor heterostructure hybrid devices like tunneling transistors, in a body of p-InAs with a vertical side connecting the low plateau and high plateau on which superconductors, preferably of niobium, are applied.

Abstract: A quantum dot logic unit (8) is provided which comprises a row of quantum dots (14, 16, and 18), with each quantum dot separated by vertical heterojunction tunneling barriers (20, 22, 24, and 26). Electric potentials placed on inputs (32, 34, and 36) are operable to modulate quantum states within the quantum dots, thus controlling electron tunneling through the tunneling barriers.

Abstract: A resonant-tunnelling hot transistor includes buffer layers undoped with impurities on either side of a collector or an emitter potential barrier having a quantum well structure. When a voltage is applied to the transistor, most of the potential drop occurs at the first buffer layer and the second buffer layer due to their thickness. This enables the inclination of the energy band of the collector barrier layer or the emitter barrier layer to be diminished, whereby the energy of the confined energy state E.sub.QW of the quantum well and the energy change of the confined state is diminished. In addition, the NDR region of I-V characteristics curve can be moved by controlling the biasing voltage, and the wave form of the curve maintains its original form.

Abstract: The present invention provides a resonant tunneling electronic device having a plurality of nearly decoupled quantum barrier layers and quantum-well layers alternatively formed between an emitter layer and a collector layer, and has a stacked structure in such a manner that in the order of their stack the heights of the quantum barriers are gradually increased, and the widths of the quantum-wells interposed between the quantum barrier layers are gradually decreased, so that electron resonant tunneling through the aligned quantum with confined states under the application of external bias can occur.

Abstract: A solid-state frequency multiplier circuit (10) is provided which includes a bipolar quantum-well resonant tunneling transistor (12), a resistive load (14), and an A.C. output coupling capacitor (16), all which may be formed in a single integrated circuit or as discrete components. The value of the resistive load (14) determines the frequency multiplication factor of the circuit (10), and can produce frequencies in a range from about 2 GHz to over 20 GHz. A different embodiment of the present invention provides a frequency multiplication circuit (20) which generates a sinusoidal output waveform, without using an output A.C. coupling capacitor.

Abstract: A static memory cell having no more than three transistors. A static memory cell comprises a semiconductor substrate of a first conductivity type; a buried layer in the substrate, the buried layer having a second conductivity type opposite to the first conductivity type; a transistor formed over the buried layer, the transistor having a source of the second conductivity type, a gate, and a drain of the second conductivity type, the source having a depth in the substrate greater than the depth of the drain; and alternating layers of insulative and conductive material formed proximate -the source, including two conductive layers and two insulative layers, one of the insulative layers being in junction relation to the source.

Abstract: On a first cladding layer formed of n-type Al.sub.0.7 Ga.sub.0.3 P, an active region having a staggered-type (type II) heterojunction superlattice structure is disposed. The active region includes 50 light emitting layers formed of Al.sub.0.1 Ga.sub.0.9 P doped with nitrogen and 50 barrier layers formed of Al.sub.0.7 Ga.sub.0.3 P. The 50 light emitting layers and the 50 barrier layers formed of such materials are stacked alternately to form 50 pairs. On the active region, a second cladding layer formed of Al.sub.0.1 Ga.sub.0.9 P is disposed. In the formation of the active layer, the composition of the light emitting layer and the barrier layer and the thickness of the barrier layer are controlled so that the isoelectronic level in the light emitting layer and the quantum level in the barrier layer will fulfill the resonance conditions.

Abstract: A logical operation circuit in which wiring as generally performed between transistors is made unnecessary to improve reliability, stability and integration degree of a logical circuit using a tunnel phenomenon, for example, a single-electron tunnel phenomenon, or a flight phenomenon of a particle group. Conducting materials are arranged in a two-dimensional plane or three-dimensional space in the logical circuit. When two conducting materials are arranged to be nearest each other, the two conducting materials are connected, for example, by a single-electron tunnel phenomenon. When two conducting materials are arranged to be not nearest, there is no connection between the conducting materials by the tunnel phenomenon. Propagation of electrons is controlled by changing the arrangement.

Abstract: By etching, a first groove and a second groove are formed in a silicon substrate. Surfaces of the side walls of these grooves have a surface orientation of (111). The first and second grooves sandwich a silicon thin plate therebetween, which is formed as a part of the silicon substrate. The silicon thin plate is sufficiently thin so as to act as a quantum well. Further, a pair of silicon oxide films acting as tunneling barriers are formed on the surfaces of the side walls of the silicon thin plate, thus forming a double barrier structure. In addition, a pair of polysilicon electrodes are formed and sandwich the double barrier structure. As a result, the structure of a resonance tunneling diode, which utilizes the resonance tunneling effect, is provided. Adding a third electrode to the above structure provides a resonance tunneling transistor.

Abstract: A photo hole burning memory device includes a quantum dot and a quantum well layer cooperating with the quantum dot for storing information and a periodic structure that creates a photonic bandgap, wherein the periodic structure includes a local irregularity that forms a level in the photonic bandgap.

Abstract: A resonant tunneling diode (400) made of a quantum well (406) with tunneling barriers (404, 408) made of two different materials such as calcium fluoride (408) and silicon dioxide (404). The calcium fluoride provides lattice match between the emitter (410) and the quantum well (406). Further resonant tunneling diodes with silicon lattice match barriers may be made of III-V compounds containing nitrogen.

Abstract: A collective element of quantum boxes includes a plurality of the first quantum boxes (QD.sub.1) arranged within the first surface, between which conduction of electrons is allowed, a plurality of the second quantum boxes (QD.sub.2) arranged within the second surface corresponding to the plural first quantum boxes (QD.sub.1) between which conduction of electrons and holes is not substantially allowed, and a plurality of the third quantum boxes (QD.sub.3) arranged within the third surface corresponding to the plural second quantum boxes (QD.sub.2), between which conduction of holes is allowed.

Abstract: Excellent negative resistance characteristics are attained in a resonant bipolar transistor (RBT) while improving current gain. A first conduction type collector layers and the opposite conduction type base layer are sequentially formed on a semiconductor substrate. A quantum well structure in which a quantum level of electrons or holes is generated, and a contact layer of the same conduction type as the base layer are sequentially formed on a part of the base layer. An emitter layer of the same conduction type as the collector layer is formed directly on another part of the base. Since good negative resistance characteristics can be attained by utilizing the resonant tunneling effect of base majority carriers, and the quantum well structure causing carrier accumulation can be eliminated from the path of carriers flowing between the emitter and the collector, it is possible to reduce the recombination current at the emitter-base interface and in the quantum well structure, thereby improving current gain.

Abstract: A carrier transport media is doped with impurities or includes barrier structures within or on the carrier transport media and a sinusoidally alternating external electric field(s) with frequencies equal to the Bloch frequency divided by an integer is applied to the carrier transport media to alter the effective barriers of the impurities or barrier structures to an arbitrarily large potential compared to the zero field barrier potential. The various impurities or barrier structures are band engineered and deposited, grown or implanted in the carrier transport media and can take any form such as barrier layers in or on the transport media, laterally induced barriers, and impurities or defects in the carrier transport media. The application of time-dependent external fields across a length of nanoscale or mesoscopic structure leads to an effective renominalization of the barrier potential strengths when the frequency of the applied electric field multiplied by an integer is equal to the Bloch frequency.

Abstract: The present invention relates to a light-controlled semiconductor heterostructure component for generating microwave frequency oscillations, wherein the heterostructure comprises at least two semiconductor materials: at least one of them absorbing light by creating electron-hole pairs; and the other one of them having majority carriers with a relationship of velocity as a function of electric field that presents a region of negative slope.

Abstract: A semiconductor device according to the invention is characterized by comprising a stacked structure which has a plurality of layers for providing rear barrier confinement potentials, an oblique side surface intersecting edges of the plurality of layers, at least one layer overlying the oblique side such that carriers can flow in a plane parallel to the oblique side surface, and narrowing means for causing carriers to flow over the edges of the plurality of layers, only in a direction of the oblique side surface.

Abstract: A tunnel transistor including source and drain and a silicon oxide tunneling layer overlying the source. A polysilicon quantum well layer positioned on the tunneling layer and in contact with the drain. The quantum well layer having a thickness which places the ground state above the Fermi level. A silicon oxide insulating layer positioned on the quantum well layer and a gate electrode positioned on the insulating layer overlying the quantum well layer and the source terminal. The tunneling layer being thin enough to allow tunneling between the source and the quantum well layer, and the insulating layer being thick enough to prevent tunneling therethrough.

Abstract: An electronic part is disclosed which is furnished with an artificial super lattice obtained by alternately superposing a substance of good conductivity formed of a compound between one element selected from among the elements belonging to the transition elements of Groups 3A to 6A and the rare earth elements and an element selected from among boron, carbon, nitrogen, phosphorus, selenium, and tellurium or a compound between oxygen and a transition metal element selected from among the elements of Group 7A and Group 8 and an insulating substance formed of a compound between a simple metal element selected from among the elements belonging to Group 1A, Group 2A, and Groups 1B to 4B and an element selected from among carbon, nitrogen, oxygen, phosphorus, sulfur, selenium, tellurium, and halogen elements in thicknesses fit for obtaining a quantum size effect.

Abstract: According to the present invention, there is provided a correlation tunnel device capable of achieving a low power consumption without decreasing a drive force when a large-scale-integrated circuit is constituted.

Abstract: A semiconductor device includes a semi-insulating semiconductor substrate, a semiconductor layer structure including at least an undoped layer of a first semiconductor, an undoped spacer layer of a second semiconductor having an electron affinity smaller than that of the first semiconductor, and an n type electron supply layer of the second semiconductor successively laminated on the substrate, the undoped layer having a flat top surface and a flat rear surface on the flat top surface of the undoped spacer layer, having, at a top surface, a concavo-convex periodic structure, and a flat rear surface, the n-type electron supply layer of the second semiconductor having a flat top surface and a rear surface that buries concavities of the concavo-convex structure of the undoped spacer layer, and a plurality of periodically arranged Schottky electrodes on the flat top surface of the n type electron supply layer, arranged in a direction perpendicular to the concavo-convex periodic structure of the undoped spacer lay

Abstract: An n-type diffusion layer, an insulating layer and a first aluminum electrode are formed on a p-type silicon substrate. Fe.sup.2+ (divalent Fe) having a vacant orbit not filled with an electron is implanted into a region of the insulating layer to form an impurity atom layer. A second aluminum electrode is formed which is in contact with the n-type diffusion layer. A voltage that increases the potential of the first aluminum electrode is applied between the first and second aluminum electrodes. The voltage is increased. In this situation, when the fermi level of the n-type diffusion layer and an impurity level which is the energy level for filling the vacant orbit of the Fe.sup.2+ are matched, a resonance tunnelling current flows. Thereafter, when there is a change to the state of non-resonance state, a negative-resistance characteristic is exhibited in which the current decreases as the voltage is increased.

Abstract: An optical functional semiconductor element which performs ultrafast, high-contrast logic operation through utilization of the high speed of light velocity. A resonant-tunneling diode having a negative resistance characteristic is provided apart from a light absorbing layer formed by one of i-type layers of what is called a triangular barrier diode of an nipin or pinip structure, by which as the quantity of incident light increases, the quantity of transmitted current is switched from increase to decrease, the amount of change is made high-contrast and an ultrafast logic operation can be performed.

Abstract: A quantum memory has memory cells, each of the memory cells includes three-stage quantum dots stacked in sequence. A memory cell array is constructed by two-dimensionally arranging the memory cells. The quantum dots are made of heterojunctions of compound semiconductors. Writing and reading to and from a memory cell are executed by bringing a needle electrode close to the memory cell to apply an external electric field while irradiating laser light to an area including the memory cell.

Abstract: Ultra-small semiconductor devices and a method of fabrication including patterning the planar surface of a substrate to form a pattern edge (e.g. a mesa) and consecutively forming a plurality of layers of semiconductor material in overlying relationship to the pattern edge so that a discontinuity is produced in the layers and a first layer on one side of the pattern edge is aligned with and in electrical contact with a different layer on the other side of the pattern edge.

Abstract: A heterojunction tunnel diode with first and second barrier layers, the first barrier layer including aluminum antimonide arsenide. A quantum well formation is sandwiched between the first and second barrier layers, and includes first and second quantum well layers with a barrier layer sandwiched therebetween, the first quantum well layer being adjacent the first barrier layer. The first quantum well layer is gallium antimonide arsenide which produces a peak in hole accumulations therein. The second quantum well layer produces a peak in electron accumulations therein. A monolayer of gallium antimonide is sandwiched in the first quantum well layer at the peak in hole accumulations and a monolayer of indium arsenide is sandwiched in the second quantum well layer at the peak in electron accumulations.

Abstract: This invention describes a nanometer scale interband lateral resonant tunneling transistor, and the method for producing the same, with lateral geometry, good fanout properties and suitable for incorporation into large-scale integrated circuits. The transistor is of a single gate design and operation is based on resonant tunneling processes in narrow-gap nanostructures which are highly responsive to quantum phenomena. Such quantum-effect devices can have very high density, operate at much higher temperatures and are capable of driving other devices.

Abstract: The single electron transistor can be operated at room temperature. The distance between the electrodes 5, 5 can be adjusted by the length of the protein and/or the wideness of the lipid bilayer and the distance between the quantum dot 4 and one of the electrodes 5 can be adjusted in units of 1.5 .ANG. by means of .alpha.-helix confirmation of a G segment of the protein.

Abstract: An optically addressed spatial light modulator includes top and bottom conductive layers sandwiching an intrinsic semiconductor multilayer structure. A cladding layer having a high trapping density is sandwiched between at least one of the electrodes and the intrinsic semiconductor layer structure. Typically, one cladding layer will be sandwiched between the top conductive layer and the intrinsic semiconductor multilayer structure and another cladding layer will be sandwiched between the bottom conductive layer and the intrinsic semiconductor structure. The cladding layer or layers laterally confine the photocarriers generated within the intrinsic semiconductor multilayer structure.