Abstract: An insulating gate type semiconductor device has a plurality of trench gate electrodes provided substantially in parallel. In this semiconductor device, among the trench gate electrodes, a thinning-out trench gate electrode excluding a channel-forming trench gate electrode is insulated from a gate wire and is connected to an emitter electrode or to a predetermined electric potential generating device for generating a negative electric potential with respect to an emitter potential. With this construction, a gate capacitance is decreased without drawbacks such as a decline of manufacturing yield and an increase in gate wire resistance, there are decreased oscillations of waveforms of voltage and current when in switching in the case of an element having a large area and operating the elements in parallel.

Abstract: A controllable field-effect semiconductor component has a semiconductor body including a first surface, a first layer of a first conduction type, and a second layer of the first conduction type lying above the first layer. The semiconductor component also has a first terminal zone that can be contact-connected at the first surface of the semiconductor body. The first terminal zone is formed in the second layer. A channel zone of a second conduction type surrounds the first terminal zone. Compensation zones of the second conduction type that are formed in the second layer are provided. Additionally, the semiconductor component has a second terminal zone of the first conduction type that can be contact-connected at the first surface of the semiconductor body. The second terminal zone is formed in the second layer.

Abstract: A high power unipolar FET switch has an N− drift layer; a layer of metal contacts the drift layer via an ohmic contact to provide a drain connection for the FET. Each switch cell has a pair of trenches recessed into the drift layer and separated by a mesa region. Oxide layers line the walls and bottom of each trench, which are each filled with a conductive material; the conductive material in each trench is connected together to provide a gate connection for the FET. A shallow P region extends from the bottom of each trench into the drift layer and around the trench corners. A layer of metal contacts the mesa region via an ohmic contact to provide a source connection for the FET. The structure preferably operates as a “normally-off” device, with the potentials created by the work function difference between the conductive material and the N− mesa region completely depleting the mesa region.

Abstract: A MOSgated device with a minimum overlap between the gate and drain electrodes is comprised of an N+ substrate which receives an epitaxial layer of silicon. The body of the epitaxial layer has an N- lower layer for an accumulation device or a P− drift lower layer. In each case the top of the epitixial layer is N+. Both can be operated in an a-c mode. A trench gate consists of a trench through the epitaxial layer which has a thin gate oxide layer on its walls and bottom and a conductive polysilicon gate body filling the trench. The thin oxide on the bottom of the trench may be thicker than the oxide on the walls to reduce gate capacitance. A thick isolation oxide which is about 10 times as thick as the gate oxide overlies the top of the polysilicon. A planar drain electrode overlies the N+ top layer and the laterally spaced isolation oxide; and a planar source electrode contacts the bottom of the substrate.

Abstract: A VD (vertical diffusion) MOSFET device for use in RF power applications has a split gate structure and an additional, dummy gate is provided between the spaced apart gates and, in operation of the device, is electrically coupled to source electrodes provided outside of the gates. The split gate structure reduces gate overlap capacitance and the dummy gate induces depletion in the semiconductor body of the device and reduces the substrate capacitance. The gate overlap capacitance and the substrate capacitance both contribute to the feedback capacitance of the device which has to be as low as possible for high frequency operation. By reducing both of these components, the invention provides advantageous high frequency operation.

Abstract: A semiconductor memory cell comprising (1) a first transistor of a first conductivity type for read-out having source/drain regions composed of a surface region of a third region and a second region and a channel forming region composed of a surface region of a first region, (2) a second transistor of a second conductivity type for write-in having source/drain regions composed of the first region and a fourth region and a channel forming region composed of a surface region of the third region, and (3) a junction-field-effect transistor of a first conductivity type for current control having gate regions composed of the fourth region and a portion of the first region facing the fourth region, a channel region composed of the third region sandwiched by the fourth region and the first region and source/drain regions composed of the third region.

Abstract: A transistor (30) uses a single continuous base region (40) with an undulating structure. The semiconductor device is an insulated gate field effect transistor having a semiconductor substrate with a plurality of doped base branches, which extend into the semiconductor substrate, form into a single base region for the entire transistor. Each of the plurality of base branches (82) is undulating and of substantially constant width, and each of the base branches undulates in-phase with the immediately adjacent base branches. A continuous gate layer (34) overlies the semiconductor substrate and is self-aligned to the plurality of base branches. The undulating structure of the base region improves channel density, and thus lowers on-resistance, and the use of a single base region ensures that all portions of the base region throughout the device will be at a substantially constant electric potential.

Abstract: There is disclosed a semiconductor device in which a device isolating insulating film is formed in a periphery of a device region of a semiconductor silicon substrate device region. A side wall insulating film formed of a silicon nitride film is formed to cover the periphery of a channel region on the silicon substrate. A Ta2O5 film, and a metal gate electrode are formed inside a trench whose side wall is formed of the side wall insulating film. An interlayer insulating film is formed on the device isolating insulating film. A Schottky source/drain formed of silicide is formed on the silicon substrate in a bottom portion of the trench whose side wall is formed of the side wall insulating film and interlayer insulating film. A source/drain electrode is formed on the Schottky source/drain.

Abstract: A high voltage device prevents or minimizes the lowering of a maximum operating voltage range. Bulk resistances of the drift regions are reduced by forming trenches within the drift regions and filling the trenches with conductive polysilicon layers. The polysilicon layers reduce the bulk resistances and prevents or minimizes the operation of parasitic bipolar junction transistors typically formed when the high voltage device is manufactured.

Abstract: In a method of fabricating a semiconductor device, a plurality of MOS devices are formed on a semiconductor substrate each with a source, a drain, and a gate electrode. A first insulating layer is formed on the semiconductor substrate with the MOS devices. A moat pattern is formed on the first insulating layer such that the portions of the first insulating layer placed at device isolation areas are exposed to the outside. Trenches are formed at the semiconductor substrate through etching the first insulating layer and the underlying semiconductor substrate using the moat pattern as a mask. The semiconductor substrate is partially etched by a predetermined depth. The trenches are filled up through forming a second insulating layer on the etched portions of the semiconductor substrate, and on the first insulating layer.

Abstract: A circuit (20) includes a resistor (26) and a current source (32) for raising the voltage of the source of the N-channel transistor in order to keep the base-emitter voltage of the parasitic bipolar device from forward biasing to prevent conduction in the parasitic bipolar device. In one embodiment, a relatively small resistor (26) is coupled between the source of an N-channel transistor (24) and ground. The current source (32) is used to direct some of the ESD current from a positive ESD event through the small source resistor (26) so that the source of the N-channel transistor (24) is elevated during the event, thus preventing snapback of the parasitic bipolar device.

Abstract: A method for forming a field effect vertical bipolar transistor that includes a semiconductive body that has at its top surface a plurality of emitter zones of one conductivity type, each surrounded by a base zone of the opposite conductivity type, and gate electrodes for creating a channel at the surface through the base zone into the bulk inner portion of the one conduction type and at a bottom surface a collector zone that includes a collector electrode overlying a collector layer of the opposite conduction type overlying a field stop layer heavily doped of the opposite conduction type overlying the inner portion lightly doped of the one conduction type. Each of the collector layer and the field stop layer is less than 2 microns in thickness and the collector layer is used to inject minority carriers into the inner zone when appropriately biased.

Abstract: Junction Field Effect Transistor (JFET) offers fast switching speed than bipolar transistor since JFET is a majority carrier device. This invention comprises two normally “off” JFETs, one in N-channel and one in P-channel to form Complementary Junction Field Effect Transistors for high speed, low voltage and/or high current applications. The discrete device structure is disclosed in this invention. The integrated Complementary Junction Field Effect Transistors structure processed in standard CMOS process is disclosed in this invention. A vertical gate structure of Complementary Junction Field Effect Transistors is disclosed. Complementary Junction Field Effect Transistors structure is also disclosed in SOI substrate.

Abstract: The invention concerns a controllable semiconductor structure comprising a base region (101, 201, 301, 401), a source region (106, 212, 312, 412) and a drain region (107, 213, 313, 413) a conductive duct being provided in the base region between the source and drain. According to the invention, the duct can be constricted by regions lying parallel thereto, an active control region (102, 202, 302, 402) and an opposite passive control region (103, 203, 303, 403) which each form a blockable passage with the base region (101, 201, 301, 401). Further provided is a conductive connection (108, 209, 309, 409) between the passive control region (103, 203, 303, 403) and the source region (106, 212, 312, 412), the semiconductor material of the base region (101, 201, 301, 401) having an energy gap of more than 1.2 eV.

Abstract: In a channel well of a semiconductive substrate, source, drain and gate electrodes are formed. Below the gate electrode region, a plurality of partial regions of the second conductive type are arranged next to each other in the direction of the extension of the gate electrode region and in a mutually spaced relationship, said partial regions bordering on the gate electrode region and extending through the channel well region into the region of the substrate bordering on the channel well region from below.

Abstract: A system and method for detecting a type of a short of a plurality of types of shorts in a circuit in a semiconductor device is disclosed. The circuit includes a plurality of power supply lines and a plurality of ground lines. The short is between at least one of the plurality of power supply lines and at least one of the plurality of ground lines. In one aspect, the method and system include providing a library including a plurality of sets of current-voltage characteristics. Each of the plurality of sets of current-voltage characteristics is for a particular type of short of the plurality of types of shorts. In this aspect, the method and system further include measuring a particular set of current-voltage characteristics of the semiconductor device and comparing the particular set of current-voltage characteristics to the plurality of sets of current-voltage characteristics in the library.

Abstract: A MOS type semiconductor apparatus is provided that includes a first MOS type semiconductor device through which main current flows, and a second MOS type semiconductor device through which current that is smaller than the main current flows. The first and second MOS type semiconductor devices provided on the same semiconductor substrate have substantially the same structure, and have a common drain electrode. A gate electrode of the second MOS type semiconductor device is connected to the common drain electrode. The semiconductor apparatus further includes a plurality of pairs of Zener diodes which are connected in series and provided between the source electrode of the second MOS type semiconductor device and the gate electrode of the first MOS type semiconductor device. Each pair of Zener diodes are reversely connected to each other.

Abstract: A semiconductor configuration, in particular based on silicon carbide, is specified which rapidly limits a short-circuit current to an acceptable current value. For this purpose, when a predetermined saturation current is exceeded, a lateral channel region is pinched off, and the current is limited to a value below the saturation current.

Abstract: A controllable conduction device in the form of a transistor comprises source and drain regions 5, 2 between which extends a conduction path P for charge carriers, a gate 4 for controlling charge carrier flow along the conduction path and a multiple layer structure 3 providing a multiple tunnel junction configuration in the conduction path, with the result that current leakage is blocked by the multiple tunnel junction configuration when the transistor is in its off state. Vertical and lateral transistor configurations are described, together with use of the transistor in complimentary pairs and for a random access memory cell. Improved gate structures are described which are also applicable to memory devices that incorporate the tunnel barrier configuration to store charge on the memory node.

Abstract: A vertical semiconductor component has an integrated switching device, which delivers an electric value correlating with the rear potential. The semiconductor component includes a doping region with a hole, which is free of the doping atoms of the doping region. The hole, when properly sized and contacted, can supply an electric current correlating with the rear potential.

Abstract: A bit line of a semiconductor device capable of obtaining low line resistance and low contact resistance, thereby achieving an improvement in the operating speed and reliability of the semiconductor device. The bit line has a multilayer structure including a Ti film, an MOCVD-TiN film and a W film sequentially formed over the semiconductor substrate. The MOCVD-TiN film serves as a diffusion barrier to suppress a reaction of tungsten, which forms the bit line, with silicon existing on a contact region during a thermal process at a high temperature such as a BPSG reflow.

Abstract: A transistor having a source/drain metal silicide in close proximity to the channel region may be formed according to the following process. A masking structure is formed upon a semiconductor substrate, and a metal is deposited self-aligned to sidewall surfaces of the masking structure. The metal is then annealed to form a metal silicide. Following formation of lightly doped drain impurity areas self-aligned to the sidewall surfaces of the masking structure, spacers may be formed adjacent the sidewall surfaces and source and drain impurity areas may be formed self-aligned to sidewall surfaces of the spacers. Fill structures are then formed adjacent the spacers and the masking structure is removed to form an opening between the spacers. A gate dielectric is formed upon the exposed upper surface of the semiconductor substrate within the opening, and a gate conductor is formed within the opening.

Abstract: A MOSFET wherein the formation of a channel in a channel formation region is controlled by a voltage applied to an insulated gate, comprising: a semiconductor substrate; a first semiconductor layer (drain region) of a first conductivity type formed on a surface of the semiconductor substrate; a second semiconductor layer (body region) of a second conductivity type provided within the first semiconductor layer, where a part thereof forms the channel formation region; a third semiconductor layer (source region) of the first conductivity type provided selectively in the second semiconductor layer; and a body contact region in electrical contact with the second semiconductor layer. The body contact region is formed in an area that is separated from an active region by a non-active region. With this structure, parasitic bipolar transistors operate simultaneously throughout the entire device so that a uniform breakdown current is generated, thus preventing element destruction due to current concentrations.

Abstract: An integrated transistor device operates with a linear triode vacuum tube like characteristic with a very low output impedance and a large interaction between the gate and drain potentials. The drain current of a first transistor is connected directly to the source of a second transistor which has a low input impedance matching the output impedance of the first transistor. The gate of the second transistor is held at a positive potential and functions to provide isolation of the varying drain signal from the drain of the first transistor and to provide a high impedance at the output terminal. This device structure provides high input impedance, high current gain, high output impedance and a linear operating characteristic.

Abstract: A semiconductor configuration includes a first semiconductor region which has a predetermined conductivity type and a first surface. There is a contact region disposed on the first surface of the first semiconductor region. There is a second semiconductor region disposed within the first semiconductor region underneath the contact region which has a conductivity type opposite the predetermined conductivity type of the first semiconductor region. A first p-n junction having a first depletion zone is formed between the first semiconductor region and the second semiconductor region. The second semiconductor region extends further than the contact region in all directions parallel to the first surface of the first semiconductor region to form at least one lateral channel region with a bottom in the first semiconductor region. The at least one lateral channel region is bounded toward its bottom by the first depletion zone of the first p-n junction.

Abstract: A vertical transistor (70) comprising a first semiconductor layer (14) of a first conductive type. A gate structure (32) of a second conductive type disposed on the first semiconductor layer (14). The gate structure (32) may include a plurality of gates (38) separated by channels (40). A second semiconductor layer (50) of the first conductive type may be disposed over the gate structure (32) and in the channels (40). An arresting element (36) may be disposed between and upper surface of the gates (38) and the second semiconductor layer (50). A void (52) may be formed in the second semiconductor layer (50) over the gate (38).

Abstract: The invention provides a trench isolation structure comprising a semiconductor region, a first insulation film formed on a top surface of the semiconductor region, a trench groove extending vertically from the first insulation film into the semiconductor region so that a bottom of the trench groove lies below an interface between the first insulation film and the semiconductor region, and an inter-layer insulator being formed which resides not only on the first insulation film but also within the trench groove so that the inter-layer insulator fills up the trench groove.The present invention still further provides a method for forming a trench isolation in a semiconductor region. The method comprises the following steps. A first insulation film is formed on a top surface of a semiconductor region.

Abstract: An n-semiconductor layer is arranged on a low-resistance n-substrate. A drain electrode is in ohmic contact with the n-substrate. A source electrode forms a Schottky junction with the n-semiconductor layer. A gate electrode is arranged adjacent to the source electrode on the n-semiconductor layer through a gate insulating film. When a voltage is applied to the gate electrode to lower the Schottky barrier height at the interface between the source electrode and the n-semiconductor layer, electrons are injected from the source electrode into the n-semiconductor layer, and a current flows in the semiconductor device. A diffusion layer which prevents a decrease in manufacturing time is not required to form in the n-semiconductor layer, and a channel which causes an increase in ON state voltage is not present.

Abstract: A static induction transistor having source, drain and gate regions. Channel regions are defined between adjacent gates and a drift region is defined from the ends of the channel regions to the drain. The channel and drift regions have predetermined doping concentrations with the doping concentration of the channel regions being greater than the doping concentration of the drift region.

Abstract: A load device for an MOS transistor, such as that of a memory cell, includes a differentially doped vertical JFET structure that contains two separate and distinct opposite conductivity type regions. The interior region has the same conductivity as the well in which the JFET is formed, and is surrounded by the JFET channel region which has a generally annular shape. The pinch-off voltage of the annular vertical JFET channel is established by its cross-sectional thickness and doping profile. This reduced thickness, annular-shaped, vertical JFET channel provides a limited current flow path that can be very precisely tailored to restrict current flow to what is essentially a leakage current path, and thereby provide a very high load impedance.

Abstract: A structure and method for fabricating an ESD device for FET transistors by forming a silicon germanium region 40 under a channel region 44 of a field effect transistor (FET). The silicon germanium region 40 comprises the base of a parasitic bipolar 200 transistor that increases the turn on speed. The method comprises:a) forming a gate dielectric layer 20 over a substrate 10;b) forming a gate 30 over the gate 30; the substrate having a channel region under the gate; the channel region extending from the surface of the substrate to a channel depth below the substrate surface;c) forming a silicon germanium region 40 under the channel region 44 using a tilt angle ion implant of Germanium ions;d) forming source and drain doped regions 50 70 adjacent to the channel region and the silicon germanium region whereby the silicon germanium region comprises a base of a parasitic bipolar transistor 40.

Abstract: A vertical field effect transistor (700) and fabrication method with buried gates (704) having gate sidewall crystal orientation the same as the substrate surface and a low index substrate crystal orientation without tilt to a higher index direction. The gate (704) may have modulated doping along the channel (706), and the drain (708) may have a lighter doping level than the channel which may be accomplished by an epitaxial overgrowth of the gates (704) to form the channels (706).

Abstract: A trench power MOSFET includes a body region which is not shorted to the source region and which is entirely covered by the source region within each cell of the MOSFET. The body region within each MOSFET cell is brought to the surface of the substrate (or epitaxial layer overlying the substrate) in an area outside of the MOSFET cell, and is connected to a body contact bus which is electrically insulated from the source bus. A deep diffusion of the same conductivity type as the body region may be formed adjacent the trench gate but outside of a MOSFET cell to protect the gate oxide from excessive field potentials at the corners of the gate. The deep diffusion is also connected to the body contact bus, which may include a metal layer, a submerged region of the second conductivity, or both.

Abstract: A semiconductor device and a method of manufacturing the same are provided which comprises a metal interconnection consisting of a titanium-aluminum film with (111) orientation formed on a semiconductor substrate via an insulating film, and an aluminum film or an aluminum alloy film with (111) orientation formed on the titanium-aluminum film by virtue of epitaxial growth. With such structure, electromigration endurance of an aluminum interconnection is improved and a wiring structure of a semiconductor is achieved with high reliability.

Abstract: A JFET device is formed on a semiconductor body comprising an active region for the junction field effect device. A drain region layer is formed below the lower portion of the active region. The top surface of the body is doped to provide a source region layer on the device. Gate trenches extend through the source region layer forming source regions therein. The gate trenches also extend partially through the epitaxial layer. The gate trenches have sidewalls and bottoms. Dielectric spacer layers cover the sidewalls of the gate trenches upon surfaces of the source layer and the epitaxial layer in the gate trenches. Self-aligned gate regions are formed at the bottoms of the gate trenches in doped portions of the active region.

Abstract: A normally-off semiconductor device with gate regions formed in a high-quality base is manufactured by forming a P.sup.+ layer in a lower surface of an N.sup.- substrate, selectively forming P.sup.+ gate regions in an upper surface of the N.sup.- substrate, forming intergate P.sup.+ regions in the upper surface of the N.sup.- substrate between the P.sup.+ gate regions, forming an N.sup.+ layer in an upper surface of an N.sup.- substrate, joining the N.sup.- substrate and the N.sup.- substrate to each other by heating them at about 800.degree. C. in a hydrogen atmosphere while the upper surface of the N.sup.- substrate and a lower surface of the N.sup.- substrate are being held against each other, and forming an anode electrode and a cathode electrode.

Abstract: A vertical semiconductor device incorporates a semiconductor laminar structure including a semiconductor substrate of a first conductive type having a relatively high impurity concentration, a first semiconductor layer of the first conductive type laminated on the semiconductor substrate and having a relatively low impurity concentration, and a second semiconductor layer of the first conductive type laminated on the first semiconductor layer and having an even lower impurity concentration. A trench is formed in the semiconductor laminar structure to extend through the second semiconductor layer into the first semiconductor layer. A source region of the first conductive type is formed in a surface layer of the second semiconductor layer and the trench is filled with a gate electrode. A source electrode is formed on the source region and a drain electrode is formed on a rear surface of the semiconductor substrate.

Abstract: Disclosed is a method of producing an electron-absorption modulator having a reverse mesa structure. In the electron-absorption modulator, a first clad of a first conductivity type, an active layer of the first conductivity type, a second clad layer of a second conductivity type and an ohmic contact layer of the second conductivity type are formed on a semiconductor substrate of the first conductivity type. Then, a predetermined mask pattern is formed on the ohmic contact layer. Afterwards, the ohmic contact layer is etched by using the mask pattern. Then, the second clad layer and the active layer below the ohmic contact layer are etched in the form of the reverse mesa structure to expose the first clad layer. Then, the first clad layer is etched at a predetermined depth in the form of a mesa structure.

Abstract: A field effect transistor comprising source and drain regions, a channel region composed of a semiconductor layer formed between the source and drain regions and gate electrodes disposed to at least three surfaces surrounding the channel region. The structure can increase the number of carriers induced in the channel region and enhance the current driving performance and mutual conductance as compared with the single gate structure or double gate structure.

Abstract: A parasitic transistor of an insulated gate semiconductor device does not easily turn on, so that an SOA of the insulated gate semiconductor device is improved. P.sup.+ semiconductor layers (45) having a higher impurity concentration than that N.sup.+ emitter layers (44) are disposed so that the P.sup.+ semiconductor layers (45) overlap adjacent edges of the N.sup.+ emitter layers (44) of a U-type IGBT and so that bottom portions of the P.sup.+ semiconductor layers (45) contact P base layers (43). An emitter electrode (51) contacts the P base layers (43) through the P.sup.+ semiconductor layers (45). A trench pitch is small, and therefore, a parasitic transistor which is formed by an N.sup.+ emitter region (4), a P base layer (3) and an N.sup.- layer (2) does not easily turn on.

Abstract: A trench isolation structure includes a semiconductor region, a first insulation film on a top surface of the semiconductor region, a trench groove extending vertically from the first insulation film into the semiconductor region so that a bottom of the trench groove lies below an interface between the first insulation film and the semiconductor region, and an inter-layer insulator on the first insulation film and within the trench groove so that the inter-layer insulator fills up the trench groove.

Abstract: A circuit arrangement for comparatively high powers, for example, for gas discharge lamps is protected against high currents, which may be caused inter alia by inrush effects or transients, by a semiconductor current limiter element V. The current limiter element comprises a semiconductor body of substantially a given conductivity type, for example the n-type. The main electrodes are provided at the upper and the lower surface of the semiconductor body and comprise two metal electrodes which are connected to the semiconductor body via highly doped contact zones. The doping of the interposed region is such that current saturation occurs from a certain voltage upon a rise in voltage between the main electrodes. In a first embodiment, buried floating p-type zones are formed in the interposed region, so that the element is a junction field effect transistor with floating gate.

Abstract: A power MOSFET having a groove for forming a channel improved for shortening the switching time and increasing the dielectric breakdown strength of the gate oxide film is disclosed. The power MOSFET includes a concave structure in which a gate oxide film at a groove bottom is thickened. Namely, since the gate oxide film between a gate electrode and a first conductivity type semiconductor layer is thick, the capacitance of the oxide film therebetween is reduced. Therefore, the input and output capacitance of the gate oxide film can be reduced, and switching loss can be also reduced since the switching time can be shortened. Further, greater dielectric breakdown strength of the gate oxide film can be obtained as a result of the thickened gate oxide film at the groove bottom.

Abstract: A junction field effect transistor and method for making is described incorporating horizontal semiconductor layers within an opening to form a channel and a semiconductor layer through which the opening was made which forms a gate electrode surrounding the channel. The horizontal semiconductor layers may be a SiGe alloy with graded composition near the source and drain. The invention overcomes the problem of forming low resistance JFET's and provides a gate length that is easily scaleable to submicron dimensions for rf, microwave, millimeter and logic circuits without short channel effects.

Abstract: In IGBTs or, respectively, MOSFETs a parasitic junction-FET effect can be nearly avoided on the basis of an insulation layer introduced between the two base zones and into which an electrode is additionally embedded. The on-resistance is lowered as a result thereof. In an advantageous development, a potential activation of the parasitic bipolar structure (latch-up) can also be prevented.

Abstract: A vertical double-gate field effect transistor includes a source layer, an epitaxial channel layer and a drain layer arranged in a stack on a bulk or SOI substrate. The gate oxide is thermally grown on the sides of the stack using differential oxidation rates to minimize input capacitance problems. The gate wraps around one end of the stack, while contacts are formed on a second end. An etch-stop layer embedded in the second end of the stack enables contact to be made directly to the channel layer.

Abstract: A field effect transistor has the property that the product of its series resistance and its true transconductance is less than one throughout the entire range of drain voltage in the operative state of the transistor, the series resistance being the sum of the resistance from source to channel and the resistance of this channel. In order to prevent an excessive increase in the active resistance of the channel, the channel is made to have an impurity concentration as low as less than 10.sup.15 atoms/cm.sup.3, preferably less than 10.sup.14 atoms/cm.sup.3, so that the depletion layers extending from the gates grow extensively to become contiguous in response to a small increase in the reverse gate voltage applied. As a result, the field effect transistor of this invention has an unsaturated drain current versus drain voltage characteristic.

Abstract: A multiple output, vertical MOSFET device (11) with improved electrical performance and thermal dissipation is integrated with an additional semiconductor device or semiconductor circuit (18) on a single semiconductor substrate (34). The method of making the vertical MOSFET device (11) involves thinning the semiconductor substrate (34) after fabricating the vertical MOSFET device (11) and the semiconductor circuit (18) to reduce the vertical component of electrical and thermal resistance and to increase the thermal dissipation efficiency. Electrical performance is improved by thinning the semiconductor substrate (34) and by providing a low resistivity, patterned metal buried layer. Thermal management is enhanced by using flip chip bumps (24) to dissipate heat from a top surface (31) of the semiconductor substrate (34) and by using the patterned buried metal layer (26) to dissipate heat from a bottom surface (32) of the semiconductor substrate (34).

Abstract: A field effect transistor has the property that the product of its active total series resistance and its true transconductance is less than one throughout the entire range of drain voltage in the operative state of this transistor, the active total series resistance being the sum of the active resistance from source to channel, the active resistance of this channel and the active resistance from channel to drain. In order to prevent an excessive increase in the active resistance of the channel, the channel is made to have an impurity concentration as low as less than 10.sup.15 atoms/cm.sup.3, preferably less than 10.sup.14 atoms/cm.sup.3, so that the depletion layers extending from the gates grow extensively to become contiguous in such fashion in response to a small increase in the reverse gate voltage applied, that no narrow lengthy path is formed between the depletion layers. As a result, the field effect transistor of this invention has an unsaturated drain current versus drain voltage characteristic.

Abstract: A semiconductor device includes a substrate crystal of a type for epitaxial growth thereon. The substrate crystal has a (111)A face and a (111)B face. Also provided are at least two semiconductor regions of different conductivity types deposited by way of epitaxial growth on the (111)A face of the substrate crystal according to metal organic chemical vapor deposition, thereby providing a structure having a source and a drain. A gate side includes the (111)B face of the substrate crystal. A gate insulating layer is deposited by way of epitaxial growth on the gate side according to molecular layer epitaxy. Alternatively, the at least two semiconductor regions may be deposited on the (111)B face of the substrate crystal according to molecular layer epitaxy, and the gate insulating layer may be deposited on the (111)A face of the substrate crystal according to metal organic chemical vapor deposition.