Abstract: A semiconductor device includes a gate structure on a semiconductor substrate, an impurity region at a side of the gate structure and the impurity region is within the semiconductor substrate, an interlayer insulating layer covering the gate structure and the impurity region, a contact structure extending through the interlayer insulating layer and connected to the impurity region, and an insulating region. The contact structure includes a first contact structure that has a side surface surrounded by the interlayer insulating layer and a second contact structure that has a side surface surrounded by the impurity region. The insulating region is under the second contact structure.

Abstract: Provided are a method of forming a contact and a method of manufacturing a phase change memory device using the same. The method of forming a contact includes forming on a substrate an insulating layer pattern having first sidewalls extending in a first direction and second sidewalls extending in a second direction perpendicular to the first direction and which together delimit contact holes, forming semiconductor patterns in lower parts of the contact holes, forming isolation spacers on the semiconductor pattern and side surfaces of the first sidewalls to expose portions of the semiconductor patterns, and etching the exposed portions of the semiconductor patterns using the isolation spacers as a mask to divide the semiconductor patterns into a plurality of finer semiconductor patterns.

Abstract: A method for forming semiconductor contacts comprises forming a germanium fin structure over a silicon substrate, depositing a doped amorphous silicon layer over the first drain/source region and the second drain/source region at a first temperature, wherein the first temperature is lower than a melting point of the germanium fin structure and performing a solid phase epitaxial regrowth process on the amorphous silicon layer at a second temperature, wherein the second temperature is lower than the melting point of the germanium fin structure.

Abstract: Provided is a semiconductor device in which on-resistance is largely reduced based on a new principle of operation. In the semiconductor device, if an embedded electrode is at negative potential, a depletion layer is formed from a trench to a neighboring trench so that a channel is turned off. If the embedded electrode is at a positive potential, the depletion layer is not formed in every region between the neighboring trenches so that the channel is turned on.

Abstract: The leakage current generated in a pn junction region between a gate and a source is reduced in a junction FET using a silicon carbide substrate. In a trench junction FET using a silicon carbide substrate, nitrogen is introduced into a sidewall and a bottom surface of a trench, thereby forming an n type layer and an n+ type layer on a surface of the trench. In this manner, the pn junction region corresponding to the junction region between a p+ type gate region and an n+ type source region is exposed on a main surface of a semiconductor substrate instead of on the damaged sidewall of the trench, and also the exposed region thereof is narrowed. Accordingly, the leakage current in the pn junction region can be reduced.

Abstract: A semiconductor device with minimized current flow differences and method of fabricating same are disclosed. The method includes forming a semiconductor stack including a plurality of layers that include a first layer having a first conductivity type and a second layer having a first conductivity type, in which the second layer is on top of the first layer, forming a plurality of mesas in the semiconductor layer stack, and forming a plurality of gates in the semiconductor layer stack having a second conductivity type and situated partially at a periphery of the mesas, in which the plurality of gates are formed to minimize current flow differences between a current flowing from the first layer to the plurality of mesas at a first applied gate bias and a current flowing from the first layer to the plurality of mesas at a second applied gate bias when voltage is applied to the semiconductor device.

Abstract: A power semiconductor device of the present invention has an active region and an electric field reduction region and includes: an emitter region of a first conductivity type; a base region of a second conductivity type in contact with the emitter region; an electrical strength providing region of the first conductivity type in contact with the base region; a collector region of the second conductivity type in contact with the electrical strength providing region; and a collector electrode in contact with the collector region; wherein the collector region is disposed on both a active region and a electric field reduction region each containing a dopant of the second conductivity type, and the collector region disposed on the electric field reduction region includes a region having a lower density of carriers of the second conductivity type than the collector region disposed on the active region.

Abstract: A solid state circuit breaker includes a first terminal; a second terminal; a first wide-band gap field effect transistor coupled to the first terminal; a second wide-band gap field effect transistor coupled to the second terminal, wherein the first wide-band gap field effect transistor and the second wide-band gap field effect transistor are common-source connected to one another; and a bi-directional snubber device coupled to the first wide-band gap field effect transistor and the second wide-band gap field effect transistor. Such a solid state circuit breaker may also include a gate drive circuit coupled to the first wide-band gap field effect transistor and the second wide-band gap field effect transistor, where the gate drive circuit may comprise a voltage regulation stage and a drive stage.

Abstract: A gallium nitride (GaN)-based junction field-effect transistor (JFET) can include a GaN drain region having a top surface extending in a lateral dimension, a source region, and a GaN channel region of a first conductivity type coupled between the source region and the GaN drain region and operable to conduct electrical current between the source region and the GaN drain region. The JFET can also include a blocking layer disposed between the source region and the GaN drain region such that the GaN channel region is operable to conduct the electrical current substantially along the lateral dimension in a laterally-conductive region of the GaN channel region, and a GaN gate region of a second conductivity type coupled to the GaN channel region such that the laterally-conductive region of the GaN channel region is disposed between at least a portion of the blocking layer and the GaN gate region.

Abstract: A semiconductor device includes a III-nitride substrate and a first III-nitride epitaxial layer coupled to the III-nitride substrate and comprising a drift region, a channel region, and an extension region. The channel region is separated from the III-nitride substrate by the drift region. The channel region is characterized by a first width. The extension region is separated from the drift region by the channel region. The extension region is characterized by a second width less than the first width. The semiconductor device also includes a second III-nitride epitaxial layer coupled to a top surface of the extension region, a III-nitride gate structure coupled to a sidewall of the channel region and laterally self-aligned with respect to the extension region, and a gate metal structure in electrical contact with the III-nitride gate structure and laterally self-aligned with respect to the extension region.

Abstract: A junction field-effect transistor (JFET) includes a substrate having a first-type semiconductor surface including a topside surface, and a top gate of a second-type formed in the semiconductor surface. A first-type drain and a first-type source are formed on opposing sides of the top gate. A first deep trench isolation region has an inner first trench wall and an outer first trench wall surrounding the top gate, the drain and the source, and extends vertically to a deep trench depth from the topside surface. A second-type sinker formed in semiconductor surface extends laterally outside the outer first trench wall. The sinker extends vertically from the topside surface to a second-type deep portion which is both below the deep trench depth and laterally inside the inner first trench wall to provide a bottom gate.

Abstract: A vertical junction field effect transistor (VJFET) having a self-aligned pin, a p+/n/n+ or a p+/p/n+ gate-source junction is described. The device gate can be self-aligned to within 0.5 ?m to the source in order to maintain good high voltage performance (i.e. low DIBL) while reducing gate-source junction leakage under reverse bias. The device can be a wide-bandgap semiconductor device such as a SiC vertical channel junction field effect. Methods of making the device are also described.

Abstract: A method for fabricating an electronic device includes providing an engineered substrate structure comprising a III-nitride seed layer, forming GaN-based functional layers coupled to the III-nitride seed layer, and forming a first electrode structure electrically coupled to at least a portion of the GaN-based functional layers. The method also includes joining a carrier substrate opposing the GaN-based functional layers and removing at least a portion of the engineered substrate structure. The method further includes forming a second electrode structure electrically coupled to at least another portion of the GaN-based functional layers and removing the carrier substrate.

Abstract: An electronic device can include a first layer having a primary surface, a well region lying adjacent to the primary surface, and a buried doped region spaced apart from the primary surface and the well region. The electronic device can also include a trench extending towards the buried doped region, wherein the trench has a sidewall, and a sidewall doped region along the sidewall of the trench, wherein the sidewall doped region extends to a depth deeper than the well region. The first layer and the buried region have a first conductivity type, and the well region has a second conductivity type opposite that of the first conductivity type. The electronic device can include a conductive structure within the trench, wherein the conductive structure is electrically connected to the buried doped region and is electrically insulated from the sidewall doped region. Processes for forming the electronic device are also described.

Abstract: Provided are a data selection circuit, a data transmission circuit, a ramp wave generation circuit, and a solid-state imaging device. A delay section delays signals input to delay units of n (n is a natural number equal to or more than 3) stages that are connected to each other and have the same configuration and outputs delayed signals from the delay units. A delay control section controls a delay amount of the delay units. An output section performs a logical operation on signals output from i-th and j-th (i and j are natural numbers that are different from each other and equal to or more than 1 and equal to or less than n) delay units to generate a signal and outputs the signal to a k-th (k is a natural number equal to or more than 1 and equal to or less than m) first data selection pulse input terminal of a functional circuit having m (m is a natural number equal to or more than 2) first data selection pulse input terminals.

Abstract: Semiconductor devices are described that include a dual-gate configuration. In one or more implementations, the semiconductor devices include a substrate having a first surface and a second surface. The substrate includes a first and a second body region formed proximal to the first surface. Moreover, each body region includes a source region formed therein. The substrate further includes a drain region formed proximal to the second surface and an epitaxial region that is configured to function as a drift region between the drain region and the source regions. A dual-gate is formed over the first surface of the substrate. The dual-gate includes a first gate region and a second gate region that define a gap there between to reduce the gate to drain capacitance. A conductive layer may be formed over the first gate region and the second gate region to lower the effective resistance of the dual-gate.

Abstract: A method for making a semiconductor device is provided. The method includes forming a first transistor with a vertical active region and a horizontal active region extending on both sides of the vertical active region. The method further includes forming a second transistor with a vertical active region. The method further includes forming a third transistor with a vertical active region and a horizontal active region extending on only one side of the vertical active region.

Abstract: A solid-state imaging device includes a substrate, a through-hole, a vertical gate electrode, and a charge fixing film. A photoelectric conversion unit generating signal charges in accordance with the amount of received light is formed in the substrate. The through-hole is formed from a front surface side through a rear surface side of the substrate. The vertical gate electrode is formed through a gate insulating film in the through-hole and reads out the signal charges generated by the photoelectric conversion unit to a reading-out portion. The charge fixing film has negative fixed charges formed to cover a portion of the inner circumferential surface of the through-hole at the rear surface side of the substrate while covering the rear surface side of the substrate.

Abstract: A vertical conduction electronic power device includes respective gate, source and drain areas in an epitaxial layer arranged on a semiconductor substrate. The respective gate, source and drain metallizations may be formed by a first metallization level. Corresponding gate, source and drain terminals or pads may be formed by a second metallization level. The power device is configured as a set of modular areas extending parallel to each other, each having a rectangular elongate source area perimetrically surrounded by a narrow gate area. The modular areas are separated from each other by regions with the drain area extending parallel and connected at the opposite ends thereof to a second closed region with the drain area forming a device outer peripheral edge.

Abstract: A trench Schottky rectifier device includes a substrate having a first conductivity type, a plurality of trenches formed in the substrate, and an insulating layer formed on sidewalls of the trenches. The trenches are filled with conductive structure. There is an electrode overlying the conductive structure and the substrate, and thus a Schottky contact forms between the electrode and the substrate. A plurality of embedded doped regions having a second conductivity type are formed in the substrate and located under the trenches. Each doped region and the substrate form a PN junction to pinch off current flowing toward the Schottky contact so as to suppress current leakage.

Abstract: A semiconductor arrangement includes a MOSFET having a source region, a drift region and a drain region of a first conductivity type, a body region of a second conductivity type arranged between the source region and the drift region, a gate electrode arranged adjacent the body region and dielectrically insulated from the body region by a gate dielectric, and a source electrode contacting the source region and the body region. The semiconductor arrangement further includes a normally-off JFET having a channel region of the first conductivity type that is coupled between the source electrode and the drift region and extends adjacent the body region so that a p-n junction is formed between the body region and the channel region.

Abstract: A semiconductor device includes a III-nitride substrate and a channel structure coupled to the III-nitride substrate. The channel structure comprises a first III-nitride epitaxial material and is characterized by one or more channel sidewalls. The semiconductor device also includes a source region coupled to the channel structure. The source region comprises a second III-nitride epitaxial material. The semiconductor device further includes a III-nitride gate structure coupled to the one or more channel sidewalls, a gate metal structure in electrical contact with the III-nitride gate structure, and a dielectric layer overlying at least a portion of the gate metal structure. A top surface of the dielectric layer is substantially co-planar with a top surface of the source region.

Abstract: In accordance with the present techniques, there is provided a JFET device structures and methods for fabricating the same. Specifically, there is provided a transistor including a semiconductor substrate having a source and a drain. The transistor also includes a doped channel formed in the semiconductor substrate between the source and the drain, the channel configured to pass current between the source and the drain. Additionally, the transistor has a gate comprising a semiconductor material formed over the channel and dielectric spacers on each side of the gate. The source and the drain are spatially separated from the gate so that the gate is not over the drain and source.

Abstract: A first region is interposed between a drain electrode and a source electrode in a thickness direction, and has first conductivity type. The first region includes a drift layer and a channel layer. The drift layer faces the drain electrode. The channel layer is provided on the drift layer and faces the source electrode. The drift layer has an impurity concentration higher than that of the channel layer. A second region has second conductivity type different from the first conductivity type. The second region has a charge compensation portion and a gate portion. The drift layer is interposed in the charge compensation portion in an in-plane direction that crosses the thickness direction. The channel layer is interposed in the gate portion in the in-plane direction.

Abstract: A semiconductor layer has a second impurity concentration. First trenches are formed in the semiconductor layer to extend downward from an upper surface of the semiconductor layer. Each of insulation layers is formed along each of the inner walls of the first trenches. Each of conductive layers is formed to bury each of the first trenches via each of the insulation layers, and extends downward from the upper surface of the semiconductor layer to a first position. A first semiconductor diffusion layer reaches a second position from the upper surface of the semiconductor layer, is positioned between the first trenches, and has a third impurity concentration lower than the second impurity concentration. A length from the upper surface of the semiconductor layer to the second position is equal to or less than half a length from the upper surface of the semiconductor layer to the first position.

Abstract: A semiconductor device (10) comprising a bipolar transistor and a field effect transistor within a semiconductor body (1) comprising a projecting mesa (5) within which are at least a portion of a collector region (22d and 22e) and a base region (33d) of the bipolar transistor. The bipolar transistor is provided with a first insulating cavity (92) provided in the collector region (22d and 22e). The base region (33d) is narrower in the plane of the substrate than the collector region (22d and 22e) due to a second insulating cavity (94) provided around the base region (33d) and between the collector region (22d and 22e) and the emitter region (4). By blocking diffusion from the base region the first insulating cavity (92) provides a reduction in the base collector capacitance and can be described as defining the base contact.

Abstract: Described herein are embodiments of a vertical power transistor having drain and gate terminals located on the same side of a semiconductor body and capable of withstanding high voltages in the off-state, in particular voltages of more than 100V.

Abstract: In one general aspect, an apparatus can include a polarity insensitive input coupled to a gate of a metal-oxide-semiconductor field effect transistor (MOSFET) device. The MOSFET device can have a gate dielectric rating greater than twenty-five volts. The apparatus can also include a fixed polarity output coupled to a source of the MOSFET device.

Abstract: A vertical-sidewall dual-mesa static induction transistor (SIT) structure includes a silicon carbide substrate having a layer arrangement formed thereon. Laterally spaced ion implanted gate regions are defined in the layer arrangement. Source regions are defined in the layer arrangement. Each of the source regions can include a channel mesa having a source mesa disposed thereon. The source mesa includes upright sidewalls relative to a principal plane of the substrate defining a horizontal dimension thereof. The channel mesa includes upright sidewalls relative to the source mesa and the principal plane of the substrate. Also disclosed is a method of fabricating a vertical-sidewall dual-mesa SiC transistor device. The method includes implanting ions at an angle relative to a principal plane of the substrate to form gate junctions in upper portions of the substrate and lateral portions of the upright channel mesas.

Abstract: An integrated circuit and component is disclosed. In one embodiment, the component is a compensation component, configuring the compensation regions in the drift zone in V-shaped fashion in order to achieve a convergence of the space charge zones from the upper to the lower end of the compensation regions is disclosed.

Abstract: A semiconductor device (10) comprising a bipolar transistor and a field 5 effect transistor within a semiconductor body (1) comprising a projecting mesa (5) within which are at least a portion of a collector region (22c and 22d) and a base region (33c) of the bipolar transistor. The bipolar transistor is provided with an insulating cavity (92b) provided in the collector region (22c and 22d). The insulating cavity (92b) may be provided by providing a layer (33a) in the collector region (22c), creating an access path, for example by selectively etching polysilicon towards monocrystalline, and removing a portion of the layer (33a) to provide the cavity using the access path. The layer (33a) provided in the collector region may be of SiGe:C. By blocking diffusion from the base region the insulating cavity (92b) provides a reduction in the base collector capacitance and can be described as defining the base contact.

Abstract: A semiconductor device 100 includes: a body region 105 of a first conductivity type placed on a principal surface of a substrate 101; a silicon carbide layer 102 including a drift region 107 of a second conductivity type; a channel layer 115 of the second conductivity type formed by silicon carbide and placed on the body region 105 and the drift region 107 on a surface of the silicon carbide layer 102; a gate insulating film 111 placed on the channel layer 115; a gate electrode 113 insulated from the silicon carbide layer 102 by the gate insulating film 111; a source electrode 116 provided on the silicon carbide layer 102; and a drain electrode 114 provided on a reverse surface of the substrate 101, wherein the source electrode 116 is in contact with the body region 105 and the channel layer 115; and a second conductivity type impurity concentration on a surface of the silicon carbide layer 102 that is in contact with the source electrode 116 is less than or equal to a second conductivity type impurity concen

Abstract: A semiconductor device includes a III-nitride substrate, a first III-nitride epitaxial layer coupled to the III-nitride substrate and having a mesa, and a second III-nitride epitaxial layer coupled to a top surface of the mesa. The semiconductor device further includes a III-nitride gate structure coupled to a side surface of the mesa, and a spacer configured to provide electrical insulation between the second III-nitride epitaxial layer and the III-nitride gate structure.

Abstract: The invention relates to a structure comprising an n-type substrate (1) having a bottom surface (10) and a top surface (11), a drain (D) contacting the bottom surface (10) of the substrate (1), a first n-type semiconductor region (2) having a top surface (21) provided with a contact area (210), a source (S) contacting the contact area (210), and a second p-type semiconductor region (3) arranged inside the first semiconductor region (2) and defining first and second conduction channels (C1, C2) between the drain and the source, characterized in that said structure comprises first and second metal gratings (G1, G2), each of which has a portion (40, 71) contacting the first semiconductor region (2) so as to form a Schottky junction.

Abstract: A semiconductor device includes a high-breakdown-voltage transistor having a semiconductor layer. The semiconductor layer has an element portion and a wiring portion. The element portion has a first wiring on a front side of the semiconductor layer and a backside electrode on a back side of the semiconductor layer. The element portion is configured as a vertical transistor that causes an electric current to flow in a thickness direction of the semiconductor layer between the first wiring and the backside electrode. The backside electrode is elongated to the wiring portion. The wiring portion has a second wiring on the front side of the semiconductor layer. The wiring portion and the backside electrode provide a pulling wire that allows the electric current to flow to the second wiring.

Abstract: A semiconductor structure includes a III-nitride substrate with a first side and a second side opposing the first side. The III-nitride substrate is characterized by a first conductivity type and a first dopant concentration. The semiconductor structure further includes a III-nitride epitaxial layer of the first conductivity type coupled to the first surface of the III-nitride substrate, a first metallic structure electrically coupled to the second surface of the III-nitride substrate, and a III-nitride epitaxial structure of a second conductivity type coupled to the III-nitride epitaxial layer. The III-nitride epitaxial structure comprises at least one edge termination structure.

Abstract: A semiconductor device, a method of forming the same, and a power converter including the semiconductor device. In one embodiment, the semiconductor device includes a heavily doped substrate, a source/drain contact below the heavily doped substrate, and a channel layer above the heavily doped substrate. The semiconductor device also includes a heavily doped source/drain layer above the channel layer and another source/drain contact above the heavily doped source/drain layer. The semiconductor device further includes pillar regions through the another source/drain contact, the heavily doped source/drain layer, and portions of the channel layer to form a vertical cell therebetween. Non-conductive regions of the semiconductor device are located in the portions of the channel layer. The semiconductor device still further includes a gate above the non-conductive regions in the pillar regions. The semiconductor device may also include a Schottky diode including the channel layer and a Schottky contact.

Abstract: A vertical III-nitride field effect transistor includes a drain comprising a first III-nitride material, a drain contact electrically coupled to the drain, and a drift region comprising a second III-nitride material coupled to the drain. The field effect transistor also includes a channel region comprising a third III-nitride material coupled to the drain and disposed adjacent to the drain along a vertical direction, a gate region at least partially surrounding the channel region, having a first surface coupled to the drift region and a second surface on a side of the gate region opposing the first surface, and a gate contact electrically coupled to the gate region. The field effect transistor further includes a source coupled to the channel region and a source contact electrically coupled to the source.

Abstract: A method of growing a III-nitride-based epitaxial structure includes providing a substrate in an epitaxial growth reactor and heating the substrate to a predetermined temperature. The method also includes flowing a gallium-containing gas into the epitaxial growth reactor and flowing a nitrogen-containing gas into the epitaxial growth reactor. The method further includes flowing a gettering gas into the epitaxial growth reactor. The predetermined temperature is greater than 1000° C.

Abstract: A vertical III-nitride field effect transistor includes a drain comprising a first III-nitride material, a drain contact electrically coupled to the drain, and a drift region comprising a second III-nitride material coupled to the drain and disposed adjacent to the drain along a vertical direction. The field effect transistor also includes a channel region comprising a third III-nitride material coupled to the drift region, a gate region at least partially surrounding the channel region, and a gate contact electrically coupled to the gate region. The field effect transistor further includes a source coupled to the channel region and a source contact electrically coupled to the source. The channel region is disposed between the drain and the source along the vertical direction such that current flow during operation of the vertical III-nitride field effect transistor is along the vertical direction.

Abstract: A semiconductor device. The semiconductor comprises a substrate, a VDMOS, a JFET, a first electrode, a second electrode, a third electrode and a fourth electrode. The VDMOS is formed in the substrate. The JFET is formed in the substrate. The first electrode, the second electrode and a third electrode are connected to the VDMOS and used as a first gate electrode, a first drain electrode and a first source electrode of the VDMOS respectively. The second electrode, the third electrode and the fourth electrode are connected to the JFET and used as a second drain electrode, a second gate electrode and a second source electrode of the JFET respectively.

Abstract: Some embodiments relate to an apparatus that exhibits vertical diode activity to occur between a semiconductive body and an epitaxial film that is disposed over a doping region of the semiconductive body. Some embodiments include an apparatus that causes both vertical and lateral diode activity. Some embodiments include a gated vertical diode for a finned semiconductor apparatus. Process embodiments include the formation of vertical-diode apparatus.

Abstract: A vertical junction field-effect transistor in a CMOS base-technology. The vertical junction field-effect transistor includes a semiconductor substrate having a source region and a drain region, a main-channel region formed between the source region and the drain region, a well region formed on the main-channel region between the source region and the drain region, vertical pinch-off regions formed at both source and drain ends or only on the source-end of the well region on the main-channel region in the source region and the drain region respectively, a source contact on the vertical pinch-off region in the source region, a drain contact on the vertical pinch-off region in the drain region, a gate contact on the well region between the source contact and the drain contact and shallow trench isolations formed on the well region.

Abstract: Junction field-effect transistors with vertical channels and self-aligned regrown gates and methods of making these devices are described. The methods use techniques to selectively grow and/or selectively remove semiconductor material to form a p-n junction gate along the sides of the channel and on the bottom of trenches separating source fingers. Methods of making bipolar junction transistors with self-aligned regrown base contact regions and methods of making these devices are also described. The semiconductor devices can be made in silicon carbide.

Abstract: The present invention relates to a semiconductor device, which includes a junction region formed in an active area of a semiconductor substrate; a trench defining a buried gate predetermined area within the semiconductor substrate; a gate electrode buried in an lower portion of the trench; an ion implantation region formed in a sidewall of the trench; and a capping insulation layer formed in an upper portion of the gate electrode.

Abstract: A semiconductor device as described herein includes a body region of a first conductivity type adjoining a channel region of a second conductivity at a first side of the channel region. A gate control region of the first conductivity type adjoins the channel region at a second side of the channel region opposed to the first side, the channel region being configured to be controlled in its conductivity by voltage application between the gate control region and the body region. A source zone of the second conductivity type is arranged within the body region and a channel stop zone of the second conductivity type is arranged at the first side, the channel stop zone being arranged at least partly within at least one of the body region and the channel region. The channel stop zone includes a maximum concentration of dopants lower than a maximum concentration of dopants of the source zone.

Abstract: A junction field effect transistor includes a channel region, a gate region coupled to the channel region, a well tap region coupled to the gate region and the channel region, and a well region coupled to the well tap region and the channel region. A double gate operation is achieved by this structure as a voltage applied to the gate region is also applied to the well region through the well tap region in order to open the channel from both the gate region and the well region.

Abstract: A normally-off JFET is provided. The normally-off JFET includes a channel region of a first conductivity type, a floating semiconductor region of a second conductivity type adjoining the channel region, and a contact region of the first conductivity type adjoining the floating semiconductor region. The floating semiconductor region is arranged between the contact region and the channel region. Further, a normally-off semiconductor switch is provided.

Abstract: Methods, devices and systems for a FinFET are provided. One method embodiment includes forming a FinFET by forming a relaxed silicon germanium (Si1-XGeX) body region for a fully depleted Fin field effect transistor (FinFET) having a body thickness of at least 10 nanometers (nm) for a process design rule of less than 25 nm. The method also includes forming a source and a drain on opposing ends of the body region, wherein the source and the drain are formed with halo ion implantation and forming a gate opposing the body region and separated therefrom by a gate dielectric.

Abstract: The present technology is related generally to vertical discrete devices with a trench at the topside of the vertical discrete devices. The trench is filled with a conducting material. In this approach, a drain or cathode of the vertical discrete devices is electrically connected to the topside to result in a small area with low RON*AREA.