Abstract: A low on-state resistance power semiconductor device has a shape and an arrangement that increase the channel density and the breakdown voltage The power semiconductor device comprises a plurality of individual cells formed on a semiconductor substrate (62). Each individual cell comprises a plurality of radially extending branches (80) having source regions (37) within base regions (36). The plurality of individual cells are arranged such that at least one branch of each cell extends towards at least one branch of an adjacent cell and wherein the base region (36) of the extending branches merge together to form a single and substantially uniformly doped base region (36) surrounding drain islands (39) at the surface of the semiconductor substrate (62).

Abstract: A structure for use in a static induction transistor includes a semiconductor body having first and second semiconductor layers on a substrate, with the second layer having a dopant concentration of around an order of magnitude higher than the dopant concentration of the first layer. A plurality of sources are located on the second layer. A plurality of gates are ion implanted in the second layer, an end one of the gates being connected to all of the plurality of gates and constituting a gate bus. The gate bus has an extension connecting the gate bus in the second layer of higher dopant concentration to the first layer of lower dopant concentration. The extension is ion implanted in either a series of steps or a sloping surface which is formed in the first and second layers.

Abstract: A semiconductor device according to one embodiment of the present invention includes: a semiconductor substrate having an operation layer on the top surface thereof; a source electrode and a drain electrode disposed on the operation layer; a gate electrode disposed between the source electrode and the drain electrode; and a field plate electrode disposed on an insulating film deposited between the gate electrode and the drain electrode. At least a part of the gate electrode is disposed in a gate recess formed in the operation layer, the field plate electrode is apart from the gate electrode by a predetermined distance, and at least a part of the field plate electrode is disposed in a field plate recess formed in the operation layer.

Abstract: A microelectronic product and the method for manufacturing the product are provided. A source and drain are spaced from one another in a first direction and are connected to opposing ends of a channel to provide a set voltage. First and second gates are spaced from one another in a second direction surrounding a portion of the channel to allow for application and removal of a gate voltage. Application of the gate voltage repels majority carriers in the channel to reduce the current that conducts between the source and drain.

Abstract: The invention is directed to a memory cell on a substrate having a plurality of shallow trench isolations form therein, wherein top surfaces of the shallow trench isolations are lower than a top surface of the substrate and the shallow trench isolations together define a vertical fin structure of the substrate. The memory cell comprises a straddle gate, a carrier trapping structure and at least two source/drain regions. The straddle gate is located on the substrate and straddles over the vertical fin structure. The carrier trapping structure is located between the straddle gate and the substrate, wherein the carrier trapping structure comprises a trapping layer directly in contact with the straddle gate and a tunnel layer located between the trapping layer and the substrate. The source/drain regions are located in a portion of the vertical fin structure of the substrate exposed by the straddle gate.

Abstract: A vertical-conduction and planar-structure MOS device having a double thickness gate oxide includes a semiconductor substrate including spaced apart active areas in the semiconductor substrate and defining a JFET area therebetween. The JFET area also forms a channel between the spaced apart active areas. A gate oxide is on the semiconductor substrate and includes a first portion having a first thickness on the active areas and at a periphery of the JFET area, and a second portion having a second thickness on a central area of the JFET area. The second thickness is greater than the first thickness. The JFET area also includes an enrichment region under the second portion of the gate oxide.

Abstract: The invention is directed to a memory cell on a substrate having a plurality of shallow trench isolations form therein, wherein top surfaces of the shallow trench isolations are lower than a top surface of the substrate and the shallow trench isolations together define a vertical fin structure of the substrate. The memory comprises a straddle gate, a carrier trapping layer and at least two source/drain regions. The straddle gate is located on the substrate and straddles over the vertical fin structure. The carrier trapping layer is located between the straddle gate and the substrate. The source/drain regions are located in a portion of the vertical fin structure of the substrate exposed by the straddle gate.

Abstract: A vertical thin-film transistor (V-TFT) is provided along with a method for forming the V-TFT. The method comprises: providing a substrate made from a material such as Si, quartz, glass, or plastic; conformally depositing an insulating layer overlying the substrate; forming a gate, having sidewalls and a thickness, overlying a substrate insulation layer; forming a gate oxide layer overlying the gate sidewalls, and a gate insulation layer overlying the gate top surface; etching the exposed substrate insulation layer; forming a first source/drain region overlying the gate insulation layer; forming a second source/drain region overlying the substrate insulation layer, adjacent a first gate sidewall; and, forming a channel region overlying the first gate sidewall with a channel length about equal to the thickness of the gate, interposed between the first and second source/drain regions.

Abstract: A method and structure for a composite trench fill for silicon electronic devices. On a planar silicon substrate having a first deposited layer of oxide and a second deposited layer of polysilicon, a trench is etched. Deposition and etch processes using a combination of oxide and polysilicon are used to fabricate a composite trench fill. The trench bottom and a lower portion of the walls are covered with oxide. The remaining portion of the trench volume is filled with polysilicon. The method may be used for junction field effect transistors (JFETs) and metal oxide semiconductor field effect transistors (MOSFETs).

Abstract: A semiconductor device includes: a gate electrode that is provided on a semiconductor layer; a source electrode and a drain electrode that are provided on the semiconductor layer so as to interpose the gate electrode; a source wall that extends from the source electrode to a point between the gate electrode and the drain electrode through the region above the gate electrode, the source wall having a joining portion in the extending region; and an electrode portion that is joined to the joining portion and has a region extending closer to the drain electrode than the joining portion.

Abstract: A junction field effect transistor is described. The transistor is made from a wide bandgap semiconductor material. The device comprises source, channel, drift and drain semiconductor layers, as well as p-type implanted or Schottky gate regions. The source, channel, drift and drain layers can be epitaxially grown. The ohmic contacts to the source, gate, and drain regions can be formed on the same side of the wafer. The devices can have different threshold voltages depending on the vertical channel width and can be implemented for both depletion and enhanced modes of operation for the same channel doping. The devices can be used for digital, analog, and monolithic microwave integrated circuits. Methods for making the transistors and integrated circuits comprising the devices are also described.

Abstract: Vertical field effect transistors having a channel region defined by at least one semiconducting nanotube and methods for fabricating such vertical field effect transistors by chemical vapor deposition using a spacer-defined channel. Each nanotube is grown by chemical vapor deposition catalyzed by a catalyst pad positioned at the base of a high-aspect-ratio passage defined between a spacer and a gate electrode. Each nanotube grows in the passage with a vertical orientation constrained by the confining presence of the spacer. A gap may be provided in the base of the spacer remote from the mouth of the passage. Reactants flowing through the gap to the catalyst pad participate in nanotube growth.

Abstract: A multiple doped channel in a multiple doped gate junction field effect transistor. In accordance with a first embodiment of the present invention, a junction field effect transistor (JFET) circuit structure comprises a vertical channel. The vertical channel comprises multiple doping regions. The vertical channel may comprise a first region for enhancement mode operation and a second region for depletion mode operation.

Abstract: A silicon carbide semiconductor device that includes J-FETs has a drift layer of epitaxially grown silicon carbide having a lower impurity concentration level than a substrate on which the drift layer is formed. Trenches are formed in the surface of the drift layer, and first gate areas are formed on inner walls of the trenches. Second gate areas are formed in isolation from the first gate areas. A source area is formed on channel areas, which are located between the first and second gate areas in the drift layer. A method of manufacturing the device ensures uniform channel layer quality, which allows the device to have a normally-off characteristic, small size, and a low likelihood of defects.

Abstract: The invention relates to an avalanche radiation detector comprising a semiconductor substrate (HK) with a front side (VS) and a back side (RS), an avalanche region (AB) which is arranged in the semiconductor substrate (HK) on the front side (VS) of the semiconductor substrate (HK) and a control electrode (R) for adjusting the electric field strength in the avalanche region (AB). It is proposed that the control electrode (R) is also arranged on the front side of the semiconductor substrate (HK).

Abstract: A programmable junction field effect transistor (JFET) with multiple independent gate inputs. A drain, source and a plurality of gate regions for controlling a conductive channel between the source and drain are fabricated in a semiconductor substrate. A first portion the gate regions are coupled to a first gate input and a second portion of the gate regions are coupled to a second gate input. The first and second gate inputs are electrically isolated from each other. The JFET may be programmed by applying a programming voltage to the first gate input and operated by applying a signal to the second gate input.

Abstract: A vertical-conduction and planar-structure MOS device having a double thickness gate oxide includes a semiconductor substrate including spaced apart active areas in the semiconductor substrate and defining a JFET area therebetween. The JFET area also forms a channel between the spaced apart active areas. A gate oxide is on the semiconductor substrate and includes a first portion having a first thickness on the active areas and at a periphery of the JFET area, and a second portion having a second thickness on a central area of the JFET area. The second thickness is greater than the first thickness. The JFET area also includes an enrichment region under the second portion of the gate oxide.

Abstract: A lateral drift vertical metal-insulated field effect transistor (LDVMISFET) with an optimum conducting channel formed in Silicon Carbide, is provided as a power transistor with a voltage rating of greater than 200 V. The lateral drift region achieves a better on-resistance/breakdown voltage trade-off than the conventional vertical drift region design of power MOSFETs. This is achieved by using an optimal doping and thickness for the voltage blocking and current conduction. The drain and backside terminal is able to support at least the rated blocking voltage of the device. A vertical MIS channel may be formed on the favorable 11-20 plane to achieve a higher MIS channel mobility as compared to the conventional 0001 or 000-1 planes resulting in a much lower on-resistance for the same blocking voltage as compared to conventional vertical MOSFET with similar blocking voltage.

Abstract: A structure is provided that ensures a low on-resistance and a better blocking effect. In a lateral type SIT (Static Induction Transistor) in which a first region is used as a p+ gate and a gate electrode is formed on the bottom of the first region, the structure is built such that the p+ gate and an n+ source are contiguous. An insulating film is formed on the surface of an n? channel, and an auxiliary gate electrode is formed on the insulating film. In addition, the auxiliary gate electrode and the source electrode are shorted.

Abstract: A MOS semiconductor device includes n?-type surface regions, which are extended portions of an n?-type drift layer 12 extended to the surface of the semiconductor chip. Each n?-type surface region 14 is shaped with a stripe surrounded by a p-type well region. The surface area ratio between n?-type surface regions 14 and p-type well region 13 including an n+-type region 15 is from 0.01 to 0.2. The MOS semiconductor device further includes, in the breakdown withstanding region thereof, a plurality of guard rings, the number of which is equal to or more than the number n calculated from the following equation n=(Breakdown voltage Vbr (V))/100, and the spacing between the adjacent guard rings is set at 1 ?m or less.

Abstract: A circuit isolation technique that uses implanted ions in embedded portions of a wafer substrate to lower the resistance of the substrate under circuits formed on the wafer or portions of circuits formed on the wafer to prevent the flow of injected currents across the substrate. The embedded ions provide low resistance regions that allow injected currents from a circuit to flow directly to a ground potential in the same circuit rather than flowing across the substrate to other circuits. High energy implantation processes on the order of 1 MeV to 3 MeVs can be used to implant the ions in embedded regions. Multiple energy levels can be used to provide thick embedded layers either prior to or after application of an epitaxial layer. Various masking materials can be used to mask the isolation regions during the implantation process, including hard masking materials such as silicon dioxide or silicon nitride, poly-silicon or an amorphous silicon layer, and a photoresist layer.

Abstract: A junction field effect transistor (JFET) is provided that is capable of a high voltage resistance, high current switching operation, that operates with a low loss, and that has little variation. This JFET is provided with a gate region (2) of a second conductivity type provided on a surface of a semiconductor substrate, a source region (1) of a first conductivity type, a channel region (10) of the first conductivity type that adjoins the source region, a confining region (5) of the second conductivity type that adjoins the gate region and confines the channel region, a drain region (3) of the first conductivity type provided on a reverse face, and a drift region (4) of the first conductivity type that continuously lies in a direction of thickness of the substrate from a channel to a drain.

Abstract: A high power MOSFET semiconductor having a high breakdown voltage. The new power device concept that reaches an area of a lower specific on-resistance, higher breakdown voltage and reduced device silicon area. This device architecture is built on the concepts of charge compensation in the drift region of the device. Where, the doping of the vertical drift region is increased by one order of magnitude. To counterbalance the added charges, fine-structured wells of opposite doping type to the drift region are introduced as part of the device structure. The charge compensation wells do not contribute to the on-state current conduction, therefore, this novel new generation of high voltage device architecture breaks the limit line of silicon. This architecture may extend to higher material resistivity and larger geometry to increase the voltage to 1kv plus.

Abstract: An insulated gate bipolar transistor includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type formed on a top surface of the first semiconductor layer, a base layer of the first conductivity type formed on a top surface of the second semiconductor layer, a plurality of gate electrodes each of which is buried in a trench with a gate insulation film interposed therebetween, the trench being formed in the base layer to a depth reaching said second semiconductor layer from a surface of the base layer, each the gate electrode having an upper surface of a rectangular pattern with different widths in two orthogonal directions, the gate electrodes being disposed in a direction along a short side of the rectangular pattern, and emitter layers of the second conductivity type formed in the surface of the base layer to oppose both end portions of each the gate electrode in a direction along a long side of the rectangular pattern.

Abstract: In a semiconductor device, a variable-potential insulated electrode and a gate region are kept at the same potential through an aluminum layer. This device is mainly used as a voltage-driving type semiconductor device. By varying the voltage applied to the variable-potential insulated electrode through a gate electrode, a conductive path is formed in a channel region to switch on the device. The channel region turns into an N-type region when a positive potential is applied to the gate electrode, and turns into a pseudo P-type region when a ground potential or negative potential is applied to the gate electrode.

Abstract: A semiconductor device includes: a semiconductor substrate of a first conductivity type; a semiconductor layer of a first conductivity type formed on a first main surface of the semiconductor substrate, the semiconductor layer including a first region for a cell portion and a second region for a terminating portion, the second region being positioned in an outer periphery of the first region, the terminating portion maintaining breakdown voltage by extending a depletion layer to relieve an electric field; junction pairs of semiconductor layers periodically arranged so as to form a line from the first region to the second region in a first direction parallel to the first main surface in the semiconductor layer and having mutually opposite conductivity types of impurities, each of the junction pair being composed of a first impurity diffusion layer of a second conductivity type formed from a surface of the semiconductor layer toward the semiconductor substrate and a second impurity diffusion layer of a first co

Abstract: A controllable field-effect semiconductor component has a semiconductor body including a first surface, a first layer of a first conduction type, and a second layer of the first conduction type lying above the first layer. The semiconductor component also has a first terminal zone that can be contact-connected at the first surface of the semiconductor body. The first terminal zone is formed in the second layer. A channel zone of a second conduction type surrounds the first terminal zone. Compensation zones of the second conduction type that are formed in the second layer are provided. Additionally, the semiconductor component has a second terminal zone of the first conduction type that can be contact-connected at the first surface of the semiconductor body. The second terminal zone is formed in the second layer.

Abstract: An integrated circuit includes an output buffer operable to drive an output node. The output buffer may comprise a MOSFET having a JFET integrated within a portion of a drain region of the MOSFET. The JFET may comprise a gate of second conductivity formed in semiconductor material of first conductivity type, which is contiguous with the drain region for the MOSFET. A voltage shaping circuit may control a bias of the JFET gate in accordance with the voltage levels of an output node and a predetermined output impedance.

Abstract: The present invention provides a wide bandgap semiconductor device encompassing: (a) a drift layer of a first conductivity type made of a wide bandgap semiconductor material; (b) a body region of a second conductivity type made of the wide bandgap semiconductor material, disposed at the top surface of and in the drift layer; (c) a source region of the first conductivity type disposed in the body region; (d) a channel layer of the first conductivity type, disposed in the body region neighboring to the source region and further disposed in the drift layer; and (e) a gate electrode including semiconductor layer at the bottom so that the semiconductor layer directly contact with the top surface of the channel layer, the semiconductor layer made of a semiconductor material having a different bandgap energy from that of the wide bandgap semiconductor material.

Abstract: A vertical field effect transistor includes an N.sup.+semiconductor substrate and an N.sup.−epitaxial layer deposited thereon and having lower dopant concentration than the semiconductor substrate, and is configured to have a plurality of unit cell transistors formed in the N.sup.−epitaxial layer and arranged in the epitaxial layer in longitudinal and lateral directions. The unit cell transistor includes a trench formed to have a depth X.sub.a and a width W, and further a gate electrode 25 formed within the trench and interposing a gate insulating film that has a thickness T.sub.OX and formed between the gate electrode and the surface of the trench. Moreover, the unit cell transistor includes a P-type base region having a depth X.sub.b, a source region, a heavily doped P-type base region formed in a central portion of the cell transistor and having a depth X.sub.

Abstract: A power semiconductor device includes a substrate of first conductivity having a dopant concentration of a first level. The substrate is a group III-V compound material. A transitional layer of first conductivity is epitaxially grown over the substrate. The transitional layer has a dopant concentration of a second level and is a group III-V compound material. An epitaxial layer of first conductivity is grown over the transitional layer and has a dopant concentration of a third level. Electrical currents flow through the transitional and epitaxial layers when the device is operating.

Abstract: A withstand voltage region of a second conductivity type is formed in a drain layer of a first conductivity type in a semiconductor substrate, and a conductive region of the first conductivity type is partly formed in the withstand voltage region by being diffused from the surface of the withstand voltage region. The conductive region has a bottom held in contact with the drain layer. A base region and a source region are formed in the surface of semiconductor substrate, with a region between the source region and the conductive region serving as a channel region, thus producing a transistor. When a voltage is applied to a gate electrode film on the channel region to form an inverted layer, the source region and the drain layer are connected to each other by the inverted layer and the conductive region.

Abstract: A junction field-effect transistor containing a semiconductor region with an inner region is described. In addition, a first and a second connecting region, respectively, are disposed within the semiconductor region. The first connecting region has the same conductivity type as the inner region, but in a higher doping concentration. The second connecting region has the opposite conductivity type to that of the inner region. This reduces the forward resistance while at the same time maintaining a high reverse voltage strength.

Abstract: A vertical JFET architecture. Generally, an integrated circuit structure includes a semiconductor area with a major surface formed along a plane and a first source/drain doped region formed in the surface. A second doped region forming a channel of different conductivity type than the first region is disposed over the first region. A third doped region is formed over the second doped region having an opposite conductivity type with respect to the second doped region, and forming a source/drain region. A gate is formed over the channel to form a vertical JFET.

Abstract: A GaN-based semiconductor device made of GaN-based semiconductor materials includes a bank made of a first undoped material and formed on a base layer, a thin layer made of a second undoped material having higher band-gap energy than the first undoped material and formed on a side wall surface of the bank, the thin layer having a heterojunction with the first undoped material, a source electrode formed on the bank so as to extend beyond the heterojunction between the bank and the thin layer, and a drain electrode formed on the reverse surface of the base layer, wherein a two-dimensional electron gas layer is formed between the source and drain electrodes in parallel with the heterojunction.

Abstract: A normally “off” enhancement mode junction field effect transistor (JFET) is disclose. The JFET has a low threshold voltage in the range of 0.2 to 0.3 volts and a low on resistance. The Drain-to-Source voltage drop is less than 0.1 volt at a drain current of 100 amperes.

Abstract: A flip-chip MOSFET structure has a vertical conduction semiconductor die in which the lower layer of the die is connected to a drain electrode on the top of the die by a diffusion sinker or conductive electrode. The source and gate electrodes are also formed on the upper surface of the die and have coplanar solder balls for connection to a circuit board. The structure has a chip scale package size. The back surface of the die, which is inverted when the die is mounted may be roughened or may be metallized to improve removal of heat from the die. Several separate MOSFETs can be integrated side-by-side into the die to form a series connection of MOSFETs with respective source and gate electrodes at the top surface having solder ball connectors. Plural solder ball connectors may be provided for the top electrodes and are laid out in respective parallel rows. The die may have the shape of an elongated rectangle with the solder balls laid out symmetrically to a diagonal to the rectangle.

Abstract: A semiconductor device is disclosed, which includes a semiconductor substrate, drain and source regions of a MOS transistor, a gate electrode formed on a surface of a channel region of the MOS transistor trench type element isolation regions in each of which an insulating film is formed on a surface of a trench formed in the surface of the semiconductor substrate, the element isolation regions sandwiching the channel region from opposite sides thereof in a channel width direction, and a conductive material layer for a back gate electrode, which is embedded in a trench of at least one of the element isolation regions, configured to be supplied with a predetermined voltage to make an depletion layer in a region of the semiconductor substrate under the channel region of the MOS transistor or to voltage-control the semiconductor substrate region.

Abstract: A method of providing a Transient Voltage Suppression (TVS) device is described utilizing a Metal Oxide Semiconductor (MOS) structure and an Insulated Gate Bipolar Transistor (IGBT) structure. The MOS based TVS devices offer reduced leakage current with reduced clamp voltages between 0.5 and 5 volts. Trench MOS based TVS device (72) provides an enhanced gain operation, while device (88) provides a top side drain contact. The high gain MOS based TVS devices provide increased control over clamp voltage variation.

Abstract: Various methods for forming semiconductor devices are provided that include the step of implanting dopants into the devices to achieve doping concentrations that allow complementary n- and p-channel SJT behavior with devices of substantially equal gate length and gate width. Moreover, complementary SJT devices are provided that include n- and p-channel devices that have approximately equal gate lengths and widths. SJT devices may be appropriately doped and configured such that input current and the output current both vary substantially exponentially with a gate-source voltage in the sub-threshold mode, and such that the drain current varies substantially linearly with the gate current through a substantially constant current gain that is given by a ratio of the drain current to the gate current.

Abstract: A method of manufacturing a unipolar component of vertical type in a substrate of a first conductivity type, including the steps of: forming trenches in a silicon layer of the first conductivity type; coating the lateral walls of the trenches with a silicon oxide layer; filling the trenches with polysilicon of the second conductivity type; and annealing to adjust the doping level of the polysilicon, the excess dopants being absorbed by the silicon oxide layer.

Abstract: Openings are formed in a laminate of a polycrystalline silicon film and an LTO film on a channel layer. While the laminate is used as a mask, impurities are implanted into a place in the channel layer which is assigned to a source region. Also, impurities are implanted into another place in the channel layer which is assigned to a portion of a second gate region. A portion of the polycrystalline silicon film which extends from the related opening is thermally oxidated. The LTO film and the oxidated portion of the polycrystalline silicon film are removed. While a remaining portion of the polycrystalline silicon film is used as a mask, impurities are implanted into a place in the channel layer which is assigned to the second gate region. Accordingly, the source region and the second gate region are formed on a self-alignment basis which suppresses a variation in channel length.

Abstract: An architecture for creating a vertical JFET. Generally, an integrated circuit structure includes a semiconductor area with a major surface formed along a plane and a first source/drain doped region formed in the surface. A second doped region forming a channel of different conductivity type than the first region is positioned over the first region. A third doped region is formed over the second doped region having an opposite conductivity type with respect to the second doped region, and forming a source/drain region. A gate is formed over the channel to form a vertical JFET.

Abstract: The invention relates to a vertical transistor and an oxidation process that achieves a substantially curvilinear recess bottom. The recess serves as the gate receptacle that may facilitate a more uniform gate oxide layer. One embodiment relates to a storage cell that is disposed in the recess along with an electrode. Another embodiment relates to a system that includes the vertical transistor or the vertical storage cell.

Abstract: A semiconductor integrated circuit device includes a plurality of internal circuits formed in a circuit forming region; a plurality of power lines separately connected to the internal circuits; a signal wire routed between the internal circuits; and a protection circuit connected to the power lines, the protection circuit including a parallel circuit having a first rectifying element formed in a p-type semiconductor region and a second rectifying element formed in an n-type semiconductor region.

Abstract: A MOSFET includes a dielectric, preferably in the form of a metal thick oxide that extends alongside the MOSFET's drift region. A voltage across this dielectric between its opposing sides exerts an electric field into the drift region to modulate the drift region electric field distribution so as to increase the breakdown voltage of a reverse biased semiconductor junction between the drift region and body region. This allows for higher doping of the drift region, for a given breakdown voltage when compared to conventional MOSFETs.

Abstract: The present invention relates to a collector pin and a trench in an integrated circuit intended for high speed communication, and to a manufacturing method for these items. The collector pin is achieved by creating an area which is implantation damaged or made amorphous and at least partially doped (139) by means of ion implantation from an upper silicon surface comprised in a semiconductor structure (144) down to a depth lower than the depth of the surrounding field oxide (120), and that the semiconductor structure (144) is then heat treated.

Abstract: A semiconductor component includes a semiconductor body having a substrate of a first conduction type and a first layer of a second conduction type that is located above the substrate. A channel zone of the first conduction type is formed in the first layer. A first terminal zone of the second conduction type is configured adjacent the channel zone. A second terminal zone of the first conduction type is formed in the first layer. Compensation zones of the first conduction type are formed in the first layer. A second layer of the second conduction type is configured between the substrate and the compensation zones.

Abstract: The semiconductor configuration is formed with a lateral channel region and an adjoining vertical channel region in an n-conductive first semiconductor region. When a predetermined saturation current is exceeded, the lateral channel region is pinched off and the current is limited to a value below the saturation current.

Abstract: Semiconductor diodes are diode connected cylindrical junction field effect devices having one diode terminal as the common connection between a top gate, a back gate and a first channel terminal of the cylindrical junction field effect devices. The second diode terminal of the semiconductor diodes being the second channel terminal of the diode connected cylindrical junction field effect devices. The method of processing the cylindrical junction field effect devices provide very short channels, shallow diffused regions and trench terminated junctions at the edges of the active device for low forward voltage turn-on and high reverse bias breakdown. The trench terminated junctions spread the breakdown energy over the entire active device region rather than just device edges.