Abstract: An insulated gate bipolar transistor has a reverse conducting function built therein. A semiconductor layer of a first conduction type is formed on the side of a drain, a semiconductor layer of a second conduction type for causing conductivity modulation upon carrier injection is formed on the semiconductor layer of the first conduction type, a semiconductor layer of the second conduction type for taking out a reverse conducting current opposite in direction to a drain current is formed in the semiconductor layer of the second conduction type which is electrically connected to a drain electrode, and a semiconductor layer of the second conduction type is formed at or in the vicinity of a pn junction, through which carriers are given and received to cause conductivity modulation, with a high impurity concentration resulting in a path for the reverse conducting current into a pattern not impeding the passage of the carriers.

Abstract: This is a vertical field-effect resonant tunneling transistor device comprising: a semi-conducting substrate 46; a drain region 48 above the semi-conducting substrate; a multiple-barrier multi-well resonant tunneling diode 52, 54, 56, 58, 60 above the drain layer; a two dimensional electron gas heterostructure 64 above the multiple-barrier multi-well resonant tunneling diode; a source region 72 extending through the two dimensional electron gas and above the multiple-barrier multi-well resonant tunneling diode; ohmic contacts 70 on the source region, wherein the source region provides an ohmic connection to the two dimensional electron gas; and gate s! 68, 74 besides the source region.

Abstract: This invention describes a device structure and a method of forming the device structure using a polysilicon spacer formed on the edges of the gate electrode forming a gate structure with a cavity. The channel area is self aligned through this cavity. A fully overlapped Lightly-Doped-Drain structure is used to improve device characteristics for submicron devices. A deep boron implant region, self aligned through the gate structure, is used to improve punch through voltage.

Abstract: A vertical insulated gate transistor such as a UMOSFET is manufactured. A source region of first conductivity type is formed on the bottom surface of a substrate. A base region of second conductivity type is formed on the source region. A low-impurity-concentration drift region is formed on the base region. On the top surface of this multilayer structure, a truncated U groove is formed. A buried gate electrode is formed inside the truncated U groove. This structure is effective to reduce gate-drain capacitance Cgd, gate-source capacitance Cgs, and drain resistance r.sub.d, thereby realizing a high-frequency high-output device. A distance between the gate and the drain is determined in a self-aligning manner, so that a fine structure and a high-frequency operation are easily realized and production yield is improved.

Abstract: A superconducting device has a stacked structure including a first superconducting layer, a first insulating layer, a second superconducting layer, a second insulating layer and a third superconducting layer stacked on a substrate in this given order. The stacked structure has an end surface portion extending from the first insulating layer to the second insulating layer. A fourth superconducting layer is formed to cover the end surface of the stacked structure. A third insulating layer separates the stacked structure end surface and the fourth superconducting layer. The fourth superconducting layer is electrically connected to the first and third superconducting layers but is isolated from the second superconducting layer by the third insulating layer. The first through fourth superconducting layers are formed of an oxide superconductor thin film.

Abstract: A double diamond mesa vertical field effect transistor includes a diamond layer, a first diamond mesa on a diamond layer, and a second diamond mesa on the first diamond mesa, opposite the diamond layer. A source contact is formed on the second diamond mesa, opposite the first diamond mesa, and a gate is formed on the first diamond mesa opposite the diamond layer. The drain contact may be formed on the diamond layer adjacent the first diamond mesa, or the diamond layer itself may be formed on a nondiamond substrate and a drain contact may be provided on the nondiamond substrate. An integrated array of field effect transistors may be formed, including a plurality of second mesas on the first mesa, with a plurality of gates formed on the first mesa between the second mesas and a source formed on each second mesa, opposite the first mesa. The second mesas may also extend over the multiple gate contacts on the first mesa to form a common source region with a common source contact.

Abstract: A junction field effect transistor, specifically a static induction transistor. The N-type source regions are formed as two zones. First, relatively lightly doped first zones are formed by ion-implanting doping material relatively deeply into the semiconductor material. Then relatively heavily doped second zones are formed by ion-implanting doping material to a relatively shallow depth within the first zones to leave portions of the first zones interposed between the second zones and the remainder of the semiconductor material. The resulting devices exhibit reduced gate-drain junction capacitance at low drain bias voltages thereby improving device capacitance linearity.

Abstract: A semiconductor device comprises a first electrode buried in one main face of a substrate and surrounded by a first insulator, a field oxide film covering the surface of the first electrode, a semiconductor layer connected with the first electrode, a second insulator covering the surface of the semiconductor layer, a second electrode connected with the semiconductor layer, a gate electrode connected with the semiconductor layer between the second insulator and the field oxide film, and an outgoing electrode connected with the first electrode.

Abstract: The vertical junction field-effect transistor comprises a semiconductor structure including an internal semiconductor layer (23, 26) extending within the channel region (7) between the gate region (4, 31), this internal layer being produced in a semiconductor material, having an energy gap (Eg.sup.2) smaller than that of the material forming the channel and gate regions, and the same type of conductivity (N) as that of the channel region, and the heterojunction formed between this internal layer and the channel region exhibits a band discontinuity situated in the valence band in the case of a N-type channel, or in the conduction band in the case of a P-type channel.

Abstract: A field effect transistor device constructed in accordance with the present invention includes a channel of semiconductive material such as silicon having at least one row of pores extending therethrough. Internal pn junctions are fabricated within the porous region, such that the inside of each pore is coated with a layer of opposite conductivity type semiconductive material. When voltage is applied to the internal pn-junctions, the space charge around the pores widens or contracts, depending upon the direction of the bias, thereby permitting the modulation of current flow through the channel.

Abstract: In a high side switching circuit for switching, an inductive load with a power MOSFET on and off, whose drain is connected with a power source and whose source is connected with the inductive load, a short-circuiting means for preventing undesired turn-on of the power MOSFET by establishing a short circuit between the gate and source of the power MOSFET when the source potential of the power MOSFET becomes lower than the ground potential. Preferably, the short-circuiting means comprises a field-effect or bipolar transistor whose control electrode is grounded.

Abstract: A selective sidewall diffusion process using doped SOG. A substrate is processed to form raised portions or pedestals, having sidewalls, and trenches. A first layer, either a doped SOG layer or undoped oxide layer, may be deposited onto the substrate adjacent the sidewalls. The first layer is densified. A second layer may be deposited on the first layer. The second layer is a doped SOG layer. The second layer is densified and the dopant is driven into the sidewalls to form shallow junctions.

Abstract: A semiconductor device including a bipolar transistor, has a collector region including a first semiconductor region of the first conductivity type and a second semiconductor region of the first conductivity type having higher resistance than the first semiconductor region, a base region including a semiconductor region of the second conductivity type, and an emitter region including a semiconductor region of the first conductivity type. The semiconductor device further comprises a metal layer region for connecting the first semiconductor region and the collector electrode on the collector region provided within the second semiconductor region layer of the collector region.

Abstract: An application-type solid state imaging device which includes a plurality of picture elements arranged in a two-dimensional matrix. A sensor region is surrounded by a substrate and a gate region is positioned laterally substantially about the sensor region. A source region is formed through one surface of the substrate and aligned vertically with the sensor region, while a drain is formed at an opposing surface of the substrate and is likewise aligned with the sensor region. The sensor region and the gate region together define a channel through which source-drain current flows. Light incident on the substrate passes therethrough to the sensor region where charge accumulates photoelectrically for producing an image signal by controlling the source-drain current in proportion to the magnitude of the photoelectrically accumulated charge. The device is reset after reading by removing charge accumulated in the sensor region through the gate region.

Abstract: A vertical diamond field effect transistor includes a nondiamond substrate, preferably a heavily doped silicon substrate, having a diamond layer on one face thereof, a source contact on the diamond layer, a gate contact on the diamond layer adjacent the source contact, and a drain contact on the back face of the substrate. The diamond layer is preferably a single layer of large polycrystalline diamond grains, having a heavily doped region adjacent the silicon substrate. The gate and source contacts may extend across many polycrystalline diamond grains in the single layer of polycrystalline diamond grains. Alternatively, the source and gate contacts may be narrower than the average grain size of the polycrystalline diamond grains. Interdigitated source and gate fingers, narrower than the average polycrystalline diamond grain size, may also be provided. The single layer of polycrystalline grains may be formed on the silicon substrate.

Abstract: A dynamic random access memory includes a memory cell including a junction field effect transistor and a capacitor. A first conductivity-type semiconductor layer is formed on a main surface of a semiconductor substrate. The semiconductor layer includes a columnar part extending from the main surface of the semiconductor substrate and having a top surface and a sidewall surface. The junction field effect transistor is formed in the columnar part, and the capacitor is formed on the top surface of the columnar part. The junction field effect transistor includes a second conductivity-type impurity region and a gate electrode. The second conductivity-type impurity region is formed on the sidewall surface of the columnar part. The gate electrode is formed to surround the sidewall surface of the columnar part to be electrically in contact with the second conductivity-type impurity, region. The capacitor includes a storage node, a dielectric film, and a cell plate electrode.