Field Effect Transistor Patents (Class 257/27)
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Patent number: 8901666Abstract: A semiconducting graphene structure may include a graphene material and a graphene-lattice matching material over at least a portion of the graphene material, wherein the graphene-lattice matching material has a lattice constant within about ±5% of a multiple of the lattice constant or bond length of the graphene material. The semiconducting graphene structure may have an energy band gap of at least about 0.5 eV. A method of modifying an energy band gap of a graphene material may include forming a graphene-lattice matching material over at least a portion of a graphene material, the graphene-lattice matching material having a lattice constant within about ±5% of a multiple of the lattice constant or bond length of the graphene material.Type: GrantFiled: July 30, 2013Date of Patent: December 2, 2014Assignee: Micron Technology, Inc.Inventors: Roy E. Meade, Sumeet C. Pandey
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Patent number: 8890118Abstract: The present disclosure relates to the field of microelectronic transistor fabrication and, more particularly, to the fabrication of a tunnel field effect transistor having an improved on-current level without a corresponding increasing the off-current level, achieved by the addition of a transition layer between a source and an intrinsic channel of the tunnel field effect transistor.Type: GrantFiled: December 17, 2010Date of Patent: November 18, 2014Assignee: Intel CorporationInventors: Benjamin Chu-Kung, Gilbert Dewey, Marko Radosavljevic, Niloy Mukherjee
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Patent number: 8890121Abstract: A technique is provided for base recognition in an integrated device is provided. A target molecule is driven into a nanopore of the integrated device. The integrated device includes a nanowire separated into a left nanowire part and a right nanowire part to form a nanogap in between, a source pad connected to the right nanowire part, a drain pad connected to the left nanowire part, and the nanopore. The source pad, the drain pad, the right nanowire part, the left nanowire part, and the nanogap together form a transistor. The nanogap is part of the nanopore. A transistor current is measured while a single base of the target molecule is in the nanogap of the nanopore, and the single base affects the transistor current. An identity of the single base is determined according to a change in the transistor current.Type: GrantFiled: May 6, 2013Date of Patent: November 18, 2014Assignee: International Business Machines CorporationInventors: Shu-Jen Han, Ajay K. Royyuru, Gustavo A. Stolovitzky, Deqiang Wang
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Patent number: 8890120Abstract: Tunneling field effect transistors (TFETs) for CMOS architectures and approaches to fabricating N-type and P-type TFETs are described. For example, a tunneling field effect transistor (TFET) includes a homojunction active region disposed above a substrate. The homojunction active region includes a relaxed Ge or GeSn body having an undoped channel region therein. The homojunction active region also includes doped source and drain regions disposed in the relaxed Ge or GeSn body, on either side of the channel region. The TFET also includes a gate stack disposed on the channel region, between the source and drain regions. The gate stack includes a gate dielectric portion and gate electrode portion.Type: GrantFiled: November 16, 2012Date of Patent: November 18, 2014Assignee: Intel CorporationInventors: Roza Kotlyar, Stephen M. Cea, Gilbert Dewey, Benjamin Chu-Kung, Uygar E. Avci, Rafael Rios, Anurag Chaudhry, Thomas D. Linton, Jr., Ian A. Young, Kelin J. Kuhn
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Patent number: 8884345Abstract: The graphene electronic device may include a gate oxide on a conductive substrate, the conductive substrate configured to function as a gate electrode, a pair of first metals on the gate oxide, the pair of the first metals separate from each other, a graphene channel layer extending between the first metals and on the first metals, and a source electrode and a drain electrode on both edges of the graphene channel layer.Type: GrantFiled: September 24, 2013Date of Patent: November 11, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Jin-seong Heo, Hyun-jong Chung, Sun-ae Seo, Sung-hoon Lee, Hee-jun Yang
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Publication number: 20140319467Abstract: The invention is a field-effect transistor with a channel consisting of a thin sheet of one or more atomic layers of lateral heterostructures based on hybridized graphene. The role of lateral heterostructures is to modify the energy gap in the channel so as to enable the effective operation of the transistor in all bias regions. This solution solves the problem of the missing bandgap in single-layer and multi-layer graphene, which does not allow the fabrication of transistors that can be efficiently switched off. The possibility of fabricating lateral heterostructures, with patterns of domains with different energy dispersion relations, enables the realization of field-effect transistors with additional functionalities with respect to common transistors.Type: ApplicationFiled: November 30, 2012Publication date: October 30, 2014Inventors: Giuseppe Iannaccone, Fiori Gianluca
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Patent number: 8872161Abstract: The present disclosure provides an integrated circuit (IC). The IC includes a substrate having a metal-oxide-semiconductor (MOS) region. The IC further includes first gate, source and drain regions, having a first length, and second gate, source and drain regions, having a second length. A first nanowire set is disposed in the first gate region, the first nanowire set including a nanowire having a first diameter and connecting to a feature in the first source region and a feature in the first drain region. A second nanowire set is disposed in the second gate region, the second nanowire set including a nanowire having a second diameter and connecting to a feature in the second source region and a feature in the second drain region. The diameters are such that if the first length is greater than the second length, the first diameter is less than the second diameter, and vice versa.Type: GrantFiled: August 26, 2013Date of Patent: October 28, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuo-Cheng Ching, Jiun-Jia Huang
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Patent number: 8859316Abstract: A Schottky junction silicon nanowire field-effect biosensor/molecule detector with a nanowire thickness of 10 nanometer or less and an aligned source/drain workfunction for increased sensitivity. The nanowire channel is coated with a surface treatment to which a molecule of interest absorbs, which modulates the conductivity of the channel between the Schottky junctions sufficiently to qualitatively and quantitatively measure the presence and amount of the molecule.Type: GrantFiled: June 29, 2010Date of Patent: October 14, 2014Assignee: International Business Machines CorporationInventors: Dechao Guo, Christian Lavoie, Christine Ouyang Qiqing, Yanning Sun, Zhen Zhang
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Publication number: 20140299838Abstract: A transistor, a display device, and associated methods, the transistor including a substrate; an active layer pattern disposed on the substrate, the active layer pattern including silicon and graphene; a gate insulating layer disposed on the active layer pattern; a gate electrode disposed on the gate insulating layer; an insulating interlayer covering the active layer pattern and the gate electrode; and a source electrode and a drain electrode in contact with the active layer pattern.Type: ApplicationFiled: March 12, 2014Publication date: October 9, 2014Applicant: Samsung Display Co., Ltd.Inventors: Jin-Woo LEE, Moo-Jin KIM
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Patent number: 8853666Abstract: In a group III nitride-type field effect transistor, the present invention reduces a leak current component by conduction of residual carriers in a buffer layer, and achieves improvement in a break-down voltage, and enhances a carrier confinement effect (carrier confinement) of a channel to improve pinch-off characteristics (to suppress a short channel effect). For example, when applying the present invention to a GaN-type field effect transistor, besides GaN of a channel layer, a composition-modulated (composition-gradient) AlGaN layer in which aluminum composition reduces toward a top gradually or stepwise is used as a buffer layer (hetero buffer).Type: GrantFiled: October 25, 2006Date of Patent: October 7, 2014Assignee: Renesas Electronics CorporationInventors: Takashi Inoue, Tatsuo Nakayama, Yuji Ando, Yasuhiro Murase, Kazuki Ota, Hironobu Miyamoto, Katsumi Yamanoguchi, Naotaka Kuroda, Akio Wakejima, Yasuhiro Okamoto
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Patent number: 8853674Abstract: A tunneling field effect transistor structure and a method for forming the same are provided. The tunneling field effect transistor structure comprises: a substrate; a plurality of convex structures formed on the substrate, every two adjacent convex structures being separated by a predetermined cavity less than 30 nm in width, the convex structures comprising a plurality of sets, and each set comprising more than two convex structures; a plurality of floated films formed on tops of the convex structures, each floated film corresponding to one set of convex structures, a region of each floated film corresponding to a top of an intermediate convex structure in each set being formed as a channel region, and regions of the each floated film at both sides of the channel region are formed as a source region and a drain region with opposite conductivity types respectively; and a gate stack formed on each channel region.Type: GrantFiled: August 28, 2012Date of Patent: October 7, 2014Assignee: Tsinghua UniversityInventors: Ning Cui, Renrong Liang, Jing Wang, Jun Xu
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Publication number: 20140291616Abstract: Compound tunneling field effect transistors integrated on a silicon substrate are provided with increased tunneling efficiency and an abrupt band slope by forming a source region with a material having a bandgap at least 0.4 electron volts (eV) narrower than that of silicon to increase a driving current (ON current) by forming a channel region with a material having almost no difference in lattice constant from a source region and having a high electron mobility at least 5 times higher than silicon. ON/OFF current ratio simultaneously is increased by forming a drain region with a material having a bandgap at least as wide as a channel region material to restrain OFF current. Tunneling field effect transistors having various threshold voltages according to circuit designs are formed easily by adding a specific material with an electron affinity less than a source region material when forming a channel region.Type: ApplicationFiled: December 30, 2011Publication date: October 2, 2014Applicant: SEOUL NATIONAL UNIVERSITY R&DB FOUNDATIONInventors: Byung-Gook Park, Seongjae Cho, In Man Kang
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Patent number: 8847205Abstract: By reducing a deposition rate and maintaining a low bias power in a plasma atmosphere, a spacer layer, for example a silicon nitride layer, may be deposited that exhibits tensile stress. The amount of tensile stress is controllable within a wide range, thereby providing the potential for forming sidewall spacer elements that modify the charge carrier mobility and thus the conductivity of the channel region of a field effect transistor.Type: GrantFiled: September 11, 2013Date of Patent: September 30, 2014Assignee: GLOBALFOUNDRIES Inc.Inventors: Hartmut Ruelke, Katja Huy, Markus Lenski
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Publication number: 20140260547Abstract: A graphene sensor and method for selective sensing of vapors, gases and biological agents are disclosed. The graphene sensor can include a substrate; a dielectric substrate on an upper layer of the substrate; a layer of graphene on an upper layer of the dielectric substrate; and a source and drain contact on an upper surface of the layer of graphene. The method for detection of vapors, gases and biological objects with low frequency input as a sensing parameter can include exposing a graphene device to at least one vapor, gas, and/or biological object, the graphene device comprising: a substrate; a dielectric substrate on an upper layer of the substrate, a layer of graphene on an upper layer of the dielectric substrate, and a source and drain contact on an upper surface of the layer of graphene; and measuring a change in a noise spectra of the graphene device.Type: ApplicationFiled: March 13, 2014Publication date: September 18, 2014Applicant: The Regents of the University of CaliforniaInventor: Alexander A. BALANDIN
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Publication number: 20140264279Abstract: Selective epitaxy of a semiconductor material is performed on a semiconductor fin to form a semiconductor nanowire. Surfaces of the semiconductor nanowire include facets that are non-horizontal and non-vertical. A gate electrode can be formed over the semiconductor nanowire such that the faceted surfaces can be employed as channel surfaces. The epitaxially deposited portions of the faceted semiconductor nanowire can apply stress to the channels. Further, an additional semiconductor material may be added to form an outer shell of the faceted semiconductor nanowire prior to forming a gate electrode thereupon. The faceted surfaces of the semiconductor nanowire provide well-defined charge carrier transport properties, which can be advantageously employed to provide a semiconductor device with well-controlled device characteristics.Type: ApplicationFiled: March 14, 2013Publication date: September 18, 2014Applicant: International Business Machines CorporationInventors: Kangguo Cheng, Juntao Li, Zhen Zhang, Yu Zhu
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Patent number: 8809837Abstract: A graphene field-effect transistor is disclosed. The graphene field-effect transistor includes a first graphene sheet, a first gate layer coupled to the first graphene sheet and a second graphene sheet coupled to the first gate layer opposite the first gate layer. The first gate layer is configured to influence an electric field within the first graphene sheet as well as to influence an electric field of the second graphene sheet.Type: GrantFiled: August 20, 2013Date of Patent: August 19, 2014Assignee: International Business Machines CorporationInventors: Damon B. Farmer, Aaron D. Franklin, Sataoshi Oida, Joshua T. Smith
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Patent number: 8803131Abstract: An integrated circuit includes a graphene layer, the graphene layer comprising a region of undoped graphene, the undoped graphene comprising a channel of a transistor, and a region of doped graphene, the doped graphene comprising a contact of the transistor; and a gate of the transistor, the gate comprising a carbon nanotube film. A method of fabricating an integrated circuit comprising graphene and carbon nanotubes, includes forming a graphene layer; doping a portion of the graphene layer, resulting in doped graphene and undoped graphene; forming a carbon nanotube film; and etching the carbon nanotube film to form a gate of a transistor, wherein the transistor further comprises a channel comprising the undoped graphene and a contact comprising the doped graphene. A transistor includes a gate, the gate comprising a carbon nanotube film; a channel, the channel comprising undoped graphene; and a contact, the contact comprising doped graphene.Type: GrantFiled: September 5, 2012Date of Patent: August 12, 2014Assignee: International Business Machines CorporationInventors: Yu-Ming Lin, Jeng-Bang Yau
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Patent number: 8796741Abstract: A semiconductor device and methods of making a semiconductor device using graphene are described. A monolithic three dimensional integrated circuit device includes a first layer having first active devices. The monolithic three dimensional integrated circuit device also includes a second layer having second active devices that each include a graphene portion. The second layer can be fabricated on the first layer to form a stack of active devices. A base substrate may support the stack of active devices.Type: GrantFiled: October 4, 2012Date of Patent: August 5, 2014Assignee: QUALCOMM IncorporatedInventors: Shiqun Gu, Yang Du
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Patent number: 8796668Abstract: An integrated circuit includes a graphene layer, the graphene layer comprising a region of undoped graphene, the undoped graphene comprising a channel of a transistor, and a region of doped graphene, the doped graphene comprising a contact of the transistor; and a gate of the transistor, the gate comprising a carbon nanotube film. A method of fabricating an integrated circuit comprising graphene and carbon nanotubes, includes forming a graphene layer; doping a portion of the graphene layer, resulting in doped graphene and undoped graphene; forming a carbon nanotube film; and etching the carbon nanotube film to form a gate of a transistor, wherein the transistor further comprises a channel comprising the undoped graphene and a contact comprising the doped graphene. A transistor includes a gate, the gate comprising a carbon nanotube film; a channel, the channel comprising undoped graphene; and a contact, the contact comprising doped graphene.Type: GrantFiled: November 9, 2009Date of Patent: August 5, 2014Assignee: International Business Machines CorporationInventors: Yu-Ming Lin, Jeng-Bang Yau
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Publication number: 20140151638Abstract: An alternating stack of first and second semiconductor layers is formed. Fin-defining mask structures are formed over the alternating stack. A planarization dielectric layer and first and second gate cavities therein are subsequently formed. The first and second gate cavities are extended downward by etching the alternating stack employing a combination of the planarization layer and the fin-defining mask structures as an etch mask. The second semiconductor material is isotropically etched to laterally expand the first gate cavity and to form a first array of semiconductor nanowires including the first semiconductor material, and the first semiconductor material is isotropically etched to laterally expand the second gate cavity and to form a second array of semiconductor nanowires including the second semiconductor material. The first and second gate cavities are filled with replacement gate structures. Each replacement gate structure laterally can surround a two-dimensional array of semiconductor nanowires.Type: ApplicationFiled: December 3, 2012Publication date: June 5, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventor: INTERNATIONAL BUSINESS MACHINES CORPORATION
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Publication number: 20140151639Abstract: An alternating stack of first and second semiconductor layers is formed. Fin-defining mask structures are formed over the alternating stack. A planarization dielectric layer and first and second gate cavities therein are subsequently formed. The first and second gate cavities are extended downward by etching the alternating stack employing a combination of the planarization layer and the fin-defining mask structures as an etch mask. The germanium-free silicon material is isotropically etched to laterally expand the first gate cavity and to form a first array of semiconductor nanowires including the silicon-germanium alloy, and the silicon-germanium alloy is isotropically etched to laterally expand the second gate cavity and to form a second array of semiconductor nanowires including the germanium-free silicon material. The first and second gate cavities are filled with replacement gate structures. Each replacement gate structure laterally can surround a two-dimensional array of semiconductor nanowires.Type: ApplicationFiled: December 3, 2012Publication date: June 5, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventor: INTERNATIONAL BUSINESS MACHINES CORPORATION
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Patent number: 8729529Abstract: A thin film transistor having a channel region including a nanoconductor layer. The nanoconductor layer can be a dispersed monolayer of nanotubes or nanowires formed of carbon. The thin film transistor generally includes a gate terminal insulated by a dielectric layer. The nanoconductor layer is placed on the dielectric layer and a layer of semiconductor material is developed over the nanoconductor layer to form the channel region of the thin film transistor. A drain terminal and a source terminal are then formed on the semiconductor layer. At low field effect levels, the operation of the thin film transistor is dominated by the semiconductor layer, which provides good leakage current performance. At high field effect levels, the charge transfer characteristics of the channel region are enhanced by the nanoconductor layer such that the effective mobility of the thin film transistor is enhanced.Type: GrantFiled: August 1, 2012Date of Patent: May 20, 2014Assignee: Ignis Innovation Inc.Inventors: Gholamreza Chaji, Maryam Moradi
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Publication number: 20140131661Abstract: Manufacturing a semiconductor structure including: forming a seed material on a sidewall of a mandrel; forming a graphene field effect transistor (FET) on the seed material; and removing the seed material.Type: ApplicationFiled: November 11, 2013Publication date: May 15, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: James W. ADKISSON, Thomas J. DUNBAR, Jeffrey P. GAMBINO, Molly J. LEITCH
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Patent number: 8716695Abstract: A method of fabricating a FET device is provided which includes the following steps. Nanowires/pads are formed in a SOI layer over a BOX layer, wherein the nanowires are suspended over the BOX. A HSQ layer is deposited that surrounds the nanowires. A portion(s) of the HSQ layer that surround the nanowires are cross-linked, wherein the cross-linking causes the portion(s) of the HSQ layer to shrink thereby inducing strain in the nanowires. One or more gates are formed that retain the strain induced in the nanowires. A FET device is also provided wherein each of the nanowires has a first region(s) that is deformed such that a lattice constant in the first region(s) is less than a relaxed lattice constant of the nanowires and a second region(s) that is deformed such that a lattice constant in the second region(s) is greater than the relaxed lattice constant of the nanowires.Type: GrantFiled: June 21, 2013Date of Patent: May 6, 2014Assignee: International Business Machines CorporationInventors: Guy Cohen, Michael A. Guillorn, Conal E. Murray
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Patent number: 8703558Abstract: The invention provides a graphene device structure and a method for manufacturing the same, the device structure comprising a graphene layer; a gate region in contact with the graphene layer; semiconductor doped regions formed in the two opposite sides of the gate region and in contact with the graphene layer, wherein the semiconductor doped regions are isolated from the gate region; a contact formed on the gate region and contacts formed on the semiconductor doped regions. The on-off ratio of the graphene device is increased through the semiconductor doped regions without increasing the band gap of the graphene material, i.e., without affecting the mobility of the material or the speed of the device, thereby increasing the applicability of the graphene material in CMOS devices.Type: GrantFiled: February 24, 2011Date of Patent: April 22, 2014Assignee: Institute of Microelectronics, Chinese Academy of SciencesInventors: Qingqing Liang, Zhi Jin, Wenwu Wang, Huicai Zhong, Xinyu Liu, Huilong Zhu
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Publication number: 20140097403Abstract: According to example embodiments, a tunneling field-effect transistor (TFET) includes a first electrode on a substrate, a semiconductor layer on a portion of the first electrode, a graphene channel on the semiconductor layer, a second electrode on the graphene channel, a gate insulating layer on the graphene channel, and a gate electrode on the gate insulating layer. The first electrode may include a portion that is adjacent to the first area of the substrate. The semiconductor layer may be between the graphene channel and the portion of the first electrode. The graphene channel may extend beyond an edge of at least one of the semiconductor layer and the portion of the first electrode to over the first area of the substrate.Type: ApplicationFiled: May 31, 2013Publication date: April 10, 2014Inventors: Jin-seong HEO, Seong-jun PARK, Kyung-eun BYUN, David SEO, Hyun-jae SONG, Jae-ho LEE, Hyun-jong CHUNG
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Publication number: 20140091279Abstract: Non-planar semiconductor devices having germanium-based active regions with release etch-passivation surfaces are described. For example, a semiconductor device includes a vertical arrangement of a plurality of germanium-rich nanowires disposed above a substrate. Each nanowire includes a channel region having a sulfur-passivated outer surface. A gate stack is disposed on and completely surrounds the channel region of each of the germanium-rich nanowires. The gate stack includes a gate dielectric layer disposed on and surrounding the sulfur-passivated outer surface and a gate electrode disposed on the gate dielectric layer. Source and drain regions are disposed on either side of the channel regions of the germanium-rich nanowires.Type: ApplicationFiled: September 28, 2012Publication date: April 3, 2014Inventors: Jessica S. Kachian, Willy Rachmady, Robert B. Turkot, Jr.
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Patent number: 8680507Abstract: A DBR/gallium nitride/aluminum nitride base grown on a silicon substrate includes a Distributed Bragg Reflector (DBR) positioned on the silicon substrate. The DBR is substantially crystal lattice matched to the surface of the silicon substrate. A first layer of III-N material is positioned on the surface of the DBR, an inter-layer of aluminum nitride (AlN) is positioned on the surface of the first layer of III-N material and an additional layer of III-N material is positioned on the surface of the inter-layer of aluminum nitride. The inter-layer of aluminum nitride and the additional layer of III-N material are repeated n-times to reduce or engineer strain in a final III-N layer.Type: GrantFiled: January 16, 2013Date of Patent: March 25, 2014Assignee: Translucent, Inc.Inventors: Erdem Arkun, Michael Lebby, Andrew Clark, Rytis Dargis
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Patent number: 8674379Abstract: Provided are a light-emitting device package and a method of manufacturing the same. The light-emitting device package may include a plurality of light-emitting chips on one substrate (board). The plurality of light-emitting chips may produce colors around a target color. The target color may be produced by combinations of the colors of light emitted from the plurality of light-emitting chips. The colors around the target color may have the same hue as the target color and have color temperatures different from that of the target color. The plurality of light-emitting chips may have color temperatures within about ±250K of that of the target color.Type: GrantFiled: July 3, 2013Date of Patent: March 18, 2014Assignee: Samsung Electronics Co., Ltd.Inventor: Hyung-kun Kim
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Patent number: 8669163Abstract: A semiconductor device includes a channel region; a gate dielectric over the channel region; a gate electrode over the gate dielectric; and a first source/drain region adjacent the gate dielectric. The first source/drain region is of a first conductivity type. At least one of the channel region and the first source/drain region includes a superlattice structure. The semiconductor device further includes a second source/drain region on an opposite side of the channel region than the first source/drain region. The second source/drain region is of a second conductivity type opposite the first conductivity type. At most, one of the first source/drain region and the second source/drain region comprises an additional superlattice structure.Type: GrantFiled: October 5, 2010Date of Patent: March 11, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Krishna Kumar Bhuwalka, Ching-Ya Wang, Ken-Ichi Goto, Wen-Chin Lee, Carlos H. Diaz
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Publication number: 20140054549Abstract: A semiconductor device and tunnel field-effect transistor, and methods of fabrication thereof are provided. The device includes first and second semiconductor regions, an intermediate region, and an epitaxial layer. The intermediate region separates the first and second semiconductor regions, and the epitaxial layer extends at least partially between the first and second regions over or alongside of the intermediate region. A gate electrode is provided for gating the circuit structure. The epitaxial layer is disposed to reside between the gate electrode and at least one of the first semiconductor region, the second semiconductor region, or the intermediate region. The epitaxial layer includes an epitaxially-grown, ultra-thin body layer of semiconductor material with a thickness less than or equal to 15 nanometers. Where the semiconductor device is a tunneling field-effect transistor, the intermediate region may be a large band-gap semiconductor region, with a band-gap greater than that of the epitaxial layer.Type: ApplicationFiled: August 23, 2012Publication date: February 27, 2014Applicant: SEMATECH, INC.Inventors: Wei-Yip LOH, Wei-E WANG
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Patent number: 8659006Abstract: A nanowire FET device includes a SOI wafer having a SOI layer over a BOX, and a plurality of nanowires and pads patterned in the SOI layer, wherein the nanowires are suspended over the BOX; an interfacial oxide surrounding each of the nanowires; and at least one gate stack surrounding each of the nanowires, the gate stack having (i) a conformal gate dielectric present on the interfacial oxide (ii) a conformal first gate material on the conformal gate dielectric (iii) a work function setting material on the conformal first gate material, and (iv) a second gate material on the work function setting material. A volume of the conformal first gate material and/or a volume of the work function setting material in the gate stack are/is proportional to a pitch of the nanowires.Type: GrantFiled: August 29, 2012Date of Patent: February 25, 2014Assignee: International Business Machines CorporationInventors: Josephine B. Chang, Isaac Lauer, Chung-Hsun Lin, Jeffrey W. Sleight
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Publication number: 20140048773Abstract: A nanowire FET device includes a SOI wafer having a SOI layer over a BOX, and a plurality of nanowires and pads patterned in the SOI layer, wherein the nanowires are suspended over the BOX; an interfacial oxide surrounding each of the nanowires; and at least one gate stack surrounding each of the nanowires, the gate stack having (i) a conformal gate dielectric present on the interfacial oxide (ii) a conformal first gate material on the conformal gate dielectric (iii) a work function setting material on the conformal first gate material, and (iv) a second gate material on the work function setting material. A volume of the conformal first gate material and/or a volume of the work function setting material in the gate stack are/is proportional to a pitch of the nanowires.Type: ApplicationFiled: August 29, 2012Publication date: February 20, 2014Applicant: International Business Machines CorporationInventors: Josephine B. Chang, Isaac Lauer, Chung-Hsun Lin, Jeffrey W. Sleight
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Publication number: 20140034908Abstract: Techniques for increasing effective device width of a nanowire FET device are provided. In one aspect, a method of fabricating a FET device is provided. The method includes the following steps. A SOI wafer is provided having an SOI layer over a BOX, wherein the SOI layer is present between a buried nitride layer and a nitride cap. The SOI layer, the buried nitride layer and the nitride cap are etched to form nanowire cores and pads in the SOI layer in a ladder-like configuration. The nanowire cores are suspended over the BOX. Epitaxial sidewalls are formed over the sidewalls of the nanowires cores. The buried nitride layer and the nitride cap are removed from the nanowire cores. A gate stack is formed that surrounds at least a portion of each of the nanowire cores and the epitaxial sidewalls.Type: ApplicationFiled: August 28, 2012Publication date: February 6, 2014Applicant: International Business Machines CorporationInventors: Sarunya Bangsaruntip, Guy Cohen, Chung-Hsun Lin, Jeffrey W. Sleight
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Patent number: 8642996Abstract: Semiconductor structures including parallel graphene nanoribbons or carbon nanotubes oriented along crystallographic directions are provided from a template of silicon carbide (SiC) fins or nanowires. The SiC fins or nanowires are first provided and then graphene nanoribbons or carbon nanotubes are formed on the exposed surfaces of the fin or the nanowires by annealing. In embodiments in which closed carbon nanotubes are formed, the nanowires are suspended prior to annealing. The location, orientation and chirality of the graphene nanoribbons and the carbon nanotubes that are provided are determined by the corresponding silicon carbide fins and nanowires from which they are formed.Type: GrantFiled: April 18, 2011Date of Patent: February 4, 2014Assignee: International Business Machines CorporationInventors: Guy Cohen, Christos D. Dimitrakopoulos, Alfred Grill
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Publication number: 20140021445Abstract: The graphene electronic device may include a gate oxide on a conductive substrate, the conductive substrate configured to function as a gate electrode, a pair of first metals on the gate oxide, the pair of the first metals separate from each other, a graphene channel layer extending between the first metals and on the first metals, and a source electrode and a drain electrode on both edges of the graphene channel layer.Type: ApplicationFiled: September 24, 2013Publication date: January 23, 2014Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jin-seong HEO, Hyun-jong CHUNG, Sun-ae SEO, Sung-hoon LEE, Hee-jun YANG
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Patent number: 8633518Abstract: Enhancement mode III-nitride devices are described. The 2DEG is depleted in the gate region so that the device is unable to conduct current when no bias is applied at the gate. Both gallium face and nitride face devices formed as enhancement mode devices.Type: GrantFiled: December 21, 2012Date of Patent: January 21, 2014Assignee: Transphorm Inc.Inventors: Chang Soo Suh, Umesh Mishra
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Patent number: 8629428Abstract: A tunnel field effect transistor (TFET) and method of making the same is provided. The TFET comprises a source-channel-drain structure and a gate electrode. The source region comprises a first source sub-region which is doped with a first doping profile with a dopant element of a first doping type having a first peak concentration and a second source sub-region close to a source-channel interface which is doped with a second doping profile with a second dopant element with the same doping type as the first dopant element and having a second peak concentration. The second peak concentration of the second doping profile is substantially higher than the maximum doping level of the first doping profile close to an interface between the first and the second source sub-regions.Type: GrantFiled: May 17, 2012Date of Patent: January 14, 2014Assignees: IMEC, Katholieke Universiteit Leuven, K.U. Leuven R&DInventors: Anne S. Verhulst, Kuo-Hsing Kao
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Patent number: 8624223Abstract: A graphene-based electrically tunable nanoconstriction device and a non-transitory tangible computer readable medium encoded with a program for fabricating the device that includes a back-gate dielectric layer over a conductive substrate are described. The back-gate dielectric layer may be hexagonal boron nitride, mica, SiOx, SiNx, BNx, HfOx or AlOx. A graphene layer is an AB-stacked bi-layer graphene layer, an ABC-stacked tri-layer graphene layer or a stacked few-layer graphene layer. Contacts formed over a portion of the graphene layer include at least one source contact, at least one drain contact and at least one set of side-gate contacts. A graphene channel with graphene side gates is formed in the graphene layer between at least one source contact, at least one the drain contact and at least one set of side-gate contacts. A top-gate dielectric layer is formed over the graphene layer. A top-gate electrode is formed on the top-gate dielectric layer.Type: GrantFiled: November 5, 2012Date of Patent: January 7, 2014Assignee: International Business Machines CorporationInventors: Ching-tzu Chen, Shu-Jen Han
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Publication number: 20140001440Abstract: A carbon-based semiconductor device includes a substrate, source/drain contacts, a graphene channel, a dielectric layer, and a gate. The source/drain contacts are formed on the substrate. The graphene channel is formed on the substrate connecting the source contact and the drain contact. The dielectric layer is formed on the graphene channel with a molecular beam deposition process. The gate contact is formed over the graphene channel and on the dielectric. The gate contact is in a non-overlapping position with the source and drain contacts leaving exposed sections of the graphene channel between the gate contact and the source and drain contacts.Type: ApplicationFiled: September 13, 2012Publication date: January 2, 2014Applicant: International Business Machines CorporationInventors: Nestor A. BOJARCZUK, Matthew W. COPEL, Yu-ming LIN
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Patent number: 8618534Abstract: A field-effect transistor includes a gate electrode, a source electrode, a drain electrode, a semiconductor active layer, and a dielectric layer. The semiconductor active layer is connected to the source electrode and the drain electrode. The dielectric layer includes denatured albumen and is positioned between the gate electrode and the semiconductor active layer.Type: GrantFiled: February 7, 2012Date of Patent: December 31, 2013Assignee: National Cheng Kung UniversityInventors: Tzung-Fang Guo, Jer-Wei Chang, Ten-Chin Wen
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Patent number: 8617941Abstract: Graphene or carbon nanotube-based transistor devices and techniques for the fabrication thereof are provided. In one aspect, a transistor is provided. The transistor includes a substrate; a carbon-based material on the substrate, wherein a portion of the carbon-based material serves as a channel region of the transistor and other portions of the carbon-based material serve as source and drain regions of the transistor; a patterned organic buffer layer over the portion of the carbon-based material that serves as the channel region of the transistor; a conformal high-k gate dielectric layer disposed selectively on the patterned organic buffer layer; metal source and drain contacts formed on the portions of the carbon-based material that serve as the source and drain regions of the transistor; and a metal top-gate contact formed on the high-k gate dielectric layer.Type: GrantFiled: January 16, 2011Date of Patent: December 31, 2013Assignee: International Business Machines CorporationInventors: Damon Brooks Farmer, Qinghuang Lin, Yu-Ming Lin
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Patent number: 8614435Abstract: A fabrication process for a nanoelectronic device and a device are provided. Channel material is deposited on a substrate to form a channel. A source metal contact and a drain metal contact are deposited on the channel material, and the source metal contact and the drain metal contact are on opposing ends of the channel material. A polyhydroxystyrene derivative is deposited on the channel material. A top gate oxide is deposited on the polymer layer. A top gate metal is deposited on the top gate oxide.Type: GrantFiled: November 3, 2009Date of Patent: December 24, 2013Assignee: International Business Machines CorporationInventors: Phaedon Avouris, Damon B. Farmer, Fengnian Xia
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Patent number: 8614141Abstract: A fabrication process for a nanoelectronic device and a device are provided. Channel material is deposited on a substrate to form a channel. A source metal contact and a drain metal contact are deposited on the channel material, and the source metal contact and the drain metal contact are on opposing ends of the channel material. A polyhydroxystyrene derivative is deposited on the channel material. A top gate oxide is deposited on the polymer layer. A top gate metal is deposited on the top gate oxide.Type: GrantFiled: August 7, 2012Date of Patent: December 24, 2013Assignee: International Business Machines CorporationInventors: Phaedon Avouris, Damon B. Farmer, Fengnian Xia
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Patent number: 8614136Abstract: Electromechanical transistors that employ Janus micro/nano-components and techniques for the fabrication thereof are provided. In one aspect, a method of fabricating an electromechanical transistor includes the following steps. A wafer is provided. A source electrode and a drain electrode are formed opposite one another on a surface of the wafer, wherein a gap is present between the source electrode and the drain electrode. A first gate electrode and a second gate electrode are formed on the surface of the wafer on opposite sides of the gap between the source electrode and the drain electrode. At least one Janus component is placed in the gap between the source electrode and the drain electrode, wherein the Janus component includes a first portion having an electrically conductive material and a second portion having an electrically insulating material.Type: GrantFiled: October 31, 2012Date of Patent: December 24, 2013Assignee: International Business Machines CorporationInventors: Qing Cao, Zhengwen Li, Fei Liu, Zhen Zhang
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Patent number: 8603872Abstract: The field effect device comprises a sacrificial gate electrode having side walls covered by lateral spacers formed on a semiconductor material film. The source/drain electrodes are formed in the semiconductor material film and are arranged on each side of the gate electrode. A diffusion barrier element is implanted through the void left by the sacrificial gate so as to form a modified diffusion area underneath the lateral spacers. The modified diffusion area is an area where the mobility of the doping impurities is reduced compared with the source/drain electrodes.Type: GrantFiled: January 24, 2012Date of Patent: December 10, 2013Assignee: Commissariat a l'Energie Atomique et aux Energies AlternativesInventors: Laurent Grenouillet, Yannick Le Tiec, Nicolas Posseme, Maud Vinet
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Patent number: 8598590Abstract: An organic light emitting diode display device includes: a switching thin film transistor in a pixel region, the switching thin film transistor including a switching semiconductor layer of polycrystalline silicon; a driving thin film transistor connected to the switching thin film transistor, the driving thin film transistor including a driving semiconductor layer of polycrystalline silicon layer; and a light emitting diode connected to the driving thin film transistor, wherein a direction of a channel of the switching thin film transistor is parallel to a first direction, and a direction of a channel of the driving thin film transistor is perpendicular to the first direction.Type: GrantFiled: December 21, 2011Date of Patent: December 3, 2013Assignee: LG Display Co., LtdInventors: Sam-Min Ko, Young-Joo Kim
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Publication number: 20130307513Abstract: Transistors suitable for high voltage and high frequency operation. A nanowire is disposed vertically or horizontally on a substrate. A longitudinal length of the nanowire is defined into a channel region of a first semiconductor material, a source region electrically coupled with a first end of the channel region, a drain region electrically coupled with a second end of the channel region, and an extrinsic drain region disposed between the channel region and drain region. The extrinsic drain region has a wider bandgap than that of the first semiconductor. A gate stack including a gate conductor and a gate insulator coaxially wraps completely around the channel region, drain and source contacts similarly coaxially wrap completely around the drain and source regions.Type: ApplicationFiled: December 19, 2011Publication date: November 21, 2013Inventors: Han Wui Then, Robert Chau, Benjamin Chu-Kung, Gilbert Dewey, Jack Kavalieros, Matthew Metz, Niloy Mukherjee, Ravi Pillarisetty, Marko Radosavljevic
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Patent number: 8581233Abstract: The present invention provides a single-electron transistor device 100. The device comprises a source 105 and drain 110 located over a substrate 115 and a quantum island 120 situated between the source and drain, to form tunnel junctions 125, 130 between the source and drain. The device further includes a fixed-gate electrode 135 located adjacent the quantum island 120. The fixed-gate electrode has a capacitance associated therewith that varies as a function of an applied voltage to the fixed-gate electrode. The present invention also includes a method of fabricating a single-electron device 300, and a transistor circuit 800 that include a single-electron device 810.Type: GrantFiled: October 7, 2009Date of Patent: November 12, 2013Assignee: Texas Instruments IncorporatedInventor: Christoph Wasshuber
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Patent number: 8575663Abstract: The present invention generally relates, in some aspects, to nanoscale wire devices and methods for use in determining analytes suspected to be present in a sample. Certain embodiments of the invention provide a nanoscale wire that has improved sensitivity, as the carrier concentration in the wire is controlled by an external gate voltage, such that the nanoscale wire has a Debye screening length that is greater than the average cross-sectional dimension of the nanoscale wire when the nanoscale wire is exposed to a solution suspected of containing an analyte. This Debye screening length (lambda) associated with the carrier concentration (p) inside nanoscale wire is adjusted, in some cases, by adjusting the gate voltage applied to an FET structure, such that the carriers in the nanoscale wire are depleted.Type: GrantFiled: November 19, 2007Date of Patent: November 5, 2013Assignee: President and Fellows of Harvard CollegeInventors: Charles M. Lieber, Xuan Gao, Gengfeng Zheng