Abstract: An electronic component includes an insulating layer that has a principal surface, a passive device that includes a low voltage pattern that is formed in the insulating layer and a high voltage pattern that is formed in the insulating layer such as to oppose the low voltage pattern in a normal direction to the principal surface and to which a voltage exceeding a voltage to be applied to the low voltage pattern is to be applied, and a shield conductor layer that is formed in the insulating layer such as to be positioned in a periphery of the high voltage pattern in plan view, shields an electric field formed between the low voltage pattern and the high voltage pattern, and suppresses electric field concentration with respect to the high voltage pattern.

Abstract: A semiconductor device includes transistors and a resistor. The transistors are connected in series between a power terminal and a ground terminal, and gate terminals of the transistors being connected together. The resistor is overlaid above the transistors. The resistor is connected between a source terminal of the transistors and the ground terminal.

Abstract: A method of making an integrated circuit (IC) includes forming circuitry over a top surface of a semiconductor substrate having the top surface and an opposite bottom surface. An antenna is formed in an interconnect layer formed above the semiconductor substrate, where the antenna is coupled to circuitry. A seal ring is formed around a periphery of the interconnect layer. The seal ring is disposed around the antenna and the circuitry. A trench with a solid-state insulating material is formed. The trench extends vertically into the semiconductor substrate and extends laterally across the IC.

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a semiconductor substrate including a front surface and a back surface; a backside metallization layer formed over the semiconductor substrate, the backside metallization layer being closer to the back surface than to the front surface of the semiconductor substrate, at least a portion of the backside metallization layer forming an inductor structure; and an electrically non-conductive material formed in the semiconductor substrate, the electrically non-conductive material at least partially overlapping the inductor structure from a top view, and the electrically non-conductive material including a top surface, a bottom surface, and sidewalls, the top surface being adjacent to the back surface of the semiconductor substrate. A method for manufacturing a semiconductor structure is also disclosed.

Abstract: A process for making a low-profile choke includes steps of: providing an etchable substrate; applying a masking layer on the etchable substrate; etching the etchable substrate through perforated patterns of the masking layer to permit the etchable substrate to be formed with an array of recessed patterns, each of which includes a core recess portion and a coil-patterned recess portion; filling a magnetic material and a conductive material respectively into the core recess portion and the coil-patterned recess portion of each of the recessed patterns to form in the etchable substrate a plurality of magnetic cores and a plurality of conductive coils; and slicing the etchable substrate to obtain a plurality of choke bodies.

Abstract: A resistive environmental sensor including an electrode stack and a sensing layer is provided. The electrode stack includes a first electrode layer, a second electrode layer, and a dielectric layer disposed between the first and second electrode layers, wherein the electrode stack includes a side surface, and the first and second electrode layers are exposed on the side surface of the electrode stack. The sensing layer is disposed on the side surface of the electrode stack, and the sensing layer s in contact with the first and second electrode layers. An environmental variation is inspected by sensing a resistance variation of the sensing layer that is between the first and second electrode layers. The above-mentioned sensor is capable of sensing gases, light, humidity, temperature, and so on. The above-mentioned sensor has advantages of low resistivity and good sensitivity.

Abstract: A semiconductor device that provides a pad electrically connected to the metal layer and a capacitor connected to the pad is disclosed. The semiconductor device provides an insulating film between the lower electrode of the capacitor and the pad. Because the insulating film protects and isolates the lower electrode from etching of the substrate via and deposition of the via metal, the lower electrode avoids voids or vacancies during formation of the via and the via metal.

Abstract: This invention discloses an integrated inductor structure, including a first metal trace, a second metal trace, and a connecting metal trace. Tow terminals of the connecting metal trace are respectively connected to the first metal trace and the second metal trace through at least a connecting structure. The connected first metal trace, the connecting metal trace and the second metal trace together form an inductor structure. The connecting structure is connected to a connecting area of the first metal trace. The connecting area of the first metal trace has a first width. A smallest width of the first metal trace is a second width. The second width is smaller than the first width.

Abstract: An RF switching device having distributed shunt switches distributed along transmission lines to improve RF bandwidth as well as the signal isolation of the device. The shunt switches may be physically positioned on both sides of the transmission lines to keep an integrated circuit (IC) design essentially symmetrical so as to provide predictable and reliable operational characteristics. Some embodiments include stacked FET shunt switches and series switches to tolerate high voltages. In some embodiments, the gate resistor for each FET shunt switch is divided into two or more portions.

Abstract: A Single-Pole-Single-Throw (SPST) switch for RF application is disclosed that can include a semiconductor MOSFET transistor T, wherein its drain terminal can be connected to a resistor R3 and capacitor C2. It can have a source terminal connected to a resistor R1 and capacitor C1, a gate terminal connected to resistor R2, a body connected by resistor R4 to GND, and the body can be connected to the anode of a diode DE The Cathode of diode D1 can be connected to a power supply Vdd through a resistor R6. The Cathode of diode D1 can also be connected to the cathode of another diode D2. The anode of D2 can be connected to GND through resistor R5. Capacitor C1 can be connected to an I/O port P1, and capacitor C2 can be connected to an I/O port P2. Inductor L1 can connect to ports P1 and P2, while inductor L2 can connect the source terminal and drain terminal of MOSPET T.

Abstract: A novel and useful radio frequency (RF) front end module (FEM) circuit that provides high linearity and power efficiency and meets the requirements of modern wireless communication standards such as 802.11 wireless local area network (WLAN), third generation (3G) and fourth generation (4G) cellular standards, BLUETOOTH™, ZIGBEE™, etc. The configuration of the FEM circuit permits the use of common, relatively low cost semiconductor fabrication techniques such as standard Complementary metal-oxide-semiconductor (CMOS) processes. The FEM circuit includes a power amplifier made up of one or more sub-amplifiers having high and low power circuits and whose outputs are combined to yield the total desired power gain. An integrated multi-tap transformer having primary and secondary windings arranged in a novel configuration provide efficient power combining and transfer to the antenna of the power generated by the individual sub-amplifiers.

Abstract: A coil with variable inner diameter is disclosed. The coil includes a coil body consisting of a plurality of turns of winding, and a connecting terminal configured to be connected to an external device, wherein the winding is wound to form at least two different inner diameters. And an electronic module made from the coil with variable inner diameter is also disclosed. The electronic module includes: electronic components including at least an integrated circuit chip; a coil with variable inner diameter, including a coil body having at least two different inner diameters and a connecting terminal; a connector, configured to be electrically connected with the electronic component and the coil; and a magnetic conductor, configured to enclose in and around the coil body and the electronic component.

Abstract: An attenuation circuit comprises a signal propagation path and a plurality of shorting units (e.g., devices) sequentially attached to the signal propagation path. In some embodiments, each of one or more initial shorting units of the plurality of shorting units have a dominant intermodulation product term for a full amplitude signal that is less than that of each of one or more subsequent shorting units of the plurality of shorting units. In some embodiments, each of one or more initial shorting units are less sensitive to control voltage changes than each of one or more subsequent shorting units. In some embodiments, each of one or more initial shorting units provide higher levels of attenuation than each of one or more subsequent shorting units. A method includes providing the above attenuation circuit and controlling a level of attenuation provided by each shorting unit of the plurality of shorting units.

Abstract: An integrated circuit is provided. The integrated circuit includes a pad, a core circuit, an impedance matching component, a first switch and a second switch. The pad is configured to transmit a communication signal. A communication terminal of the core circuit is coupled to the pad, and a power terminal of the core circuit is coupled to a system voltage rail. A first terminal of the impedance matching component is coupled to the pad. A first terminal of the first switch is coupled to the system voltage rail, and a second terminal of the first switch is coupled to a second terminal of the impedance matching component. A first terminal of the second switch is coupled to a control terminal of the first switch, and a second terminal of the second switch is coupled to the second terminal of the impedance matching component.

Abstract: An RF switching device having distributed shunt switches distributed along transmission lines to improve RF bandwidth as well as the signal isolation of the device. The shunt switches may be physically positioned on both sides of the transmission lines to keep an integrated circuit (IC) design essentially symmetrical so as to provide predictable and reliable operational characteristics. Some embodiments include stacked FET shunt switches and series switches to tolerate high voltages. In some embodiments, the gate resistor for each FET shunt switch is divided into two or more portions.

Abstract: A microelectronic package includes a packaging substrate having a chip mounting surface; a chip mounted on the chip mounting surface of the packaging substrate with the chip's active surface facing down to the chip mounting surface; a plurality of input/output (I/O) pads distributed on the active surface of the chip; and a discrete passive element mounted on the active surface of the chip. The discrete passive element may be a decoupling capacitor, a resistor, or an inductor.

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor substrate having an integrated circuit (IC) device; an interconnect structure disposed on the semiconductor substrate and coupled with the IC device; and a transformer disposed on the semiconductor substrate and integrated in the interconnect structure. The transformer includes a first conductive feature; a second conductive feature inductively coupled with the first conductive feature; a third conductive feature electrically connected to the first conductive feature; and a fourth conductive feature electrically connected to the second conductive feature. The third and fourth conductive features are designed and configured to be capacitively coupled to increase a coupling coefficient of the transformer.

Abstract: A decoupling capacitor cell includes: a first decoupling capacitor formed by only a pMOS transistor; and a second decoupling capacitor formed by two metal layers. The decoupling capacitor cell is arranged in an unused region not occupied by basic cells in a cell-based IC and is connected to a power wiring and a ground wiring.

Abstract: One or more embodiments relate to a semiconductor structure, comprising: a conductive feature; an outer guard ring; and an inner guard ring between the outer guard ring and the conductive feature, the inner guard ring being electrically coupled to the conductive feature.

Abstract: A bypass capacitor circuit for an integrated circuit (IC) comprises one or more capacitive devices, each arranged in a segment of a seal ring area of a die, which comprises the IC. A method of providing a bypass capacitance for an IC comprises providing a semiconductor wafer device comprising a plurality of dies, each comprising an IC; arranging one or more capacitive devices in a seal ring area of at least one of the IC; dicing the semiconductor wafer device; in a test mode, for each of the one or more capacitive devices, enabling the capacitive device, determining an operability parameter value indicative of an operability of the capacitive device, and storing the operability parameter in a memory device; and in a normal operation mode, providing a bypass capacitance to the IC depending on a capacitance of one or more of the capacitive devices having an associated operability parameter value indicative of a non-defectiveness of the corresponding capacitive device.

Abstract: RF attenuator circuitry includes an RF attenuator and a control system. The RF attenuator is configured to provide an attenuation response between an input node and an output node. The control system is coupled to the RF attenuator and configured to adjust one or more control signals provided to the RF attenuator based on either the temperature of the circuitry or an externally applied test signal provided to the control system. The control signals are provided such that the attenuation response of the RF attenuator is substantially linear-in-dB with respect to either the temperature or the test signal provided to the control system. Because the control system is configured to adjust the control signals based either on a temperature of the circuitry or the test signal, the response of the RF attenuator can be easily and quickly tested to ensure linear-in-dB operation thereof.

Abstract: A semiconductor device is disclosed. One embodiment provides a semiconductor chip. The semiconductor chip includes a first electrode of a capacitor. An insulating layer is arranged on top of the first electrode. A second electrode of the capacitor is applied over the insulating layer, wherein the second electrode is made of a conductive layer arranged over the semiconductor chip.

Abstract: An organic light emitting film package structure includes an organic light emitting unit and a film structure covering the organic light emitting unit. The film structure includes a first film as a bottom layer, a second film as a top layer, and a transition layer disposed between the first second films. The first film is SiX or SiXY, the second film is SiY or SiXY, and the transition layer includes multiple SiXnYm layers. The first and second films have different materials. A difference in atomic ratio of X or Y between two adjacent SiXnYm layers in the transition layer is greater than a difference in atomic ratio of X or Y between the first film and its adjacent SiXnYm layer or a difference in atomic ratio of X or Y between the second film and its adjacent SiXnYm. The value of m and n ranges from 0 to 1, inclusive.

Abstract: A full bridge rectifier includes four bipolar transistors, each of which has an associated parallel diode. A first pair of inductors provides inductive current splitting and thereby provides base current to/from one pair of the bipolar transistors so that the collector-to-emitter voltages of the bipolar transistors are low. A second pair of inductors similarly provides inductive current splitting to provide base current to/from the other pair of bipolar transistors. In one embodiment, all components are provided in a four terminal full bridge rectifier module. The module can be used as a drop-in replacement for a conventional four terminal full bridge diode rectifier. When current flows through the rectifier module, however, the voltage drop across the module is less than one volt. Due to the reduced low voltage drop, power loss in the rectifier module is reduced as compared to power loss in a conventional full bridge diode rectifier.

Abstract: A rolled-up transmission line structure for a radiofrequency integrated circuit (RFIC) comprises a multilayer sheet in a rolled configuration comprising multiple turns about a longitudinal axis, where the multilayer sheet comprises a conductive pattern layer on a strain-relieved layer. The conductive pattern layer comprises a first conductive film and a second conductive film separated from the first conductive film in a rolling direction. In the rolled configuration, the first conductive film surrounds the longitudinal axis, and the second conductive film surrounds the first conductive film. The first conductive film serves as a signal line and the second conductive film serves as a conductive shield for the rolled-up transmission line structure.

Abstract: Merged active devices on a common substrate are presented. Methods for operating and fabricating such merged active devices are also presented.

Abstract: An embodiment of a vertical power device includes a III-nitride substrate, a drift region coupled to the III-nitride substrate and comprising a III-nitride material of a first conductivity type, and a channel region coupled to the drift region and comprising a III-nitride material of the first conductivity type. The vertical power device also includes a source region coupled to the channel region and comprising a III-nitride material of the first conductivity type, and a gate region coupled to the channel region. The gate region includes a III-nitride material of a second conductivity type. The vertical power device further includes a source-coupled region coupled to the drift region and electrically connected with the source region. The source-coupled region includes a III-nitride material of the second conductivity type.

Abstract: A semiconductor device includes: a package; an input matching circuit and an output matching circuit in the package; and transistor chips between the input matching circuit and the output matching circuit in the package. Each transistor chip includes a semiconductor substrate having long sides and short sides that are shorter than the long sides, and a gate electrode, a drain electrode and a source electrode on the semiconductor substrate. The gate electrode has gate fingers arranged along the long sides of the semiconductor substrate and a gate pad commonly connected to the gate fingers and connected to the input matching circuit via a first wire. The drain electrode is connected to the output matching circuit via a second wire. The long sides of the semiconductor substrates of the transistor chips are oblique with respect to an input/output direction extending from the input matching circuit to the output matching circuit.

Abstract: A semiconductor device structure a semiconductor substrate having a first conductivity type and a top surface. A plurality of first doped regions is at a first depth below the top surface arranged in a checkerboard fashion. The first doped regions are of a second conductivity type. A dielectric layer is over the top surface. An inductive element is over the dielectric layer, wherein the inductive element is over the first doped regions.

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a substrate having a surface that is defined by a first axis and a second axis perpendicular to the first axis; and a capacitor disposed on the substrate, the capacitor having an anode component that includes a plurality of first conductive features and a cathode component that includes a plurality of second conductive features. The first conductive features and the second conductive features each include two metal lines extending along the first axis. At least one metal via extending along a third axis that is perpendicular to the surface of the substrate and interconnecting the two metal lines. The first conductive features are interdigitated with the second conductive features along both the second axis and the third axis.

Abstract: One or more embodiments related to a semiconductor structure, comprising: a conductive feature; an outer guard ring; and an inner guard ring between the outer guard ring and the conductive feature, the inner guard ring being electrically coupled to the conductive feature.

Abstract: An active matrix substrate (30) of the present invention includes a substrate, a gate line (50) formed on the substrate, and an interlayer insulating layer (90) for insulating a layer formed on the gate line (50) from the gate line (50). In a region of the substrate, the interlayer insulating layer (90) is not provided on an upper surface of the gate line (50), and therefore, the upper surface is exposed. On the other hand, the insulating layer (90) is provided on the substrate so as to have contact with at least an edge face of the gate line (50) which edge face is on an extension of a longitudinal direction of the gate line (50).

Abstract: Through substrate features in semiconductor substrates are described. In one embodiment, the semiconductor device includes a through substrate via disposed in a first region of a semiconductor substrate. A through substrate conductor coil is disposed in a second region of the semiconductor substrate.

Abstract: According to one embodiment, an acoustic semiconductor device includes an element unit, and a first terminal. The element unit includes an acoustic resonance unit. The acoustic resonance unit includes a semiconductor crystal. An acoustic standing wave is excitable in the acoustic resonance unit and is configured to be synchronously coupled with electric charge density within at least one portion of the semiconductor crystal via deformation-potential coupling effect. The first terminal is electrically connected to the element unit. At least one selected from outputting and inputting an electrical signal is implementable via the first terminal. The electrical signal is coupled with the electric charge density. The outputting the electrical signal is from the acoustic resonance unit, and the inputting the electrical signal is into the acoustic resonance unit.

Abstract: A Reverse Bipolar Junction Transistor (RBJT) integrated circuit comprises a bipolar transistor and a parallel-coupled distributed diode. The bipolar transistor involves many N-type collector regions. Each N-type collector region has a central hole so that P-type material from an underlying P-type region extends up into the hole. A collector metal electrode covers the central hole forming a diode contact at the top of the hole. When the distributed diode conducts, current flows from the collector electrode, down through the many central holes in the many collector regions, through corresponding PN junctions, and to an emitter electrode disposed on the bottom side of the IC. The RBJT and distributed diode integrated circuit has emitter-to-collector and emitter-to-base reverse breakdown voltages exceeding twenty volts. The collector metal electrode is structured to contact the collector regions, and to bridge over the base electrode, resulting in a low collector-to-emitter voltage when the RBJT is on.

Abstract: An electrostatic discharge (ESD) protection device is provided. The ESD protection device includes an epitaxy layer disposed on a semiconductor substrate. An isolation pattern is disposed on the epitaxy layer to define a first active region and a second active region, which are surrounded by a first well region. A gate is disposed on the isolation pattern. A first doped region and a second doped region are disposed in the first active region and the second active region, respectively. A drain doped region is disposed in the first doped region. A source doped region and a first pick-up doped region are disposed in the second doped region. A source contact plug having an extended portion connects to the source doped region. A ratio of an area of the extended portion covering the first pick-up doped region to an area of first pick-up doped region is between zero and one.

Abstract: An object is to provide a memory device which does not need a complex manufacturing process and whose power consumption can be suppressed, and a semiconductor device including the memory device. A solution is to provide a capacitor which holds data and a switching element which controls storing and releasing charge in the capacitor in a memory element. In the memory element, a phase-inversion element such as an inverter or a clocked inverter includes the phase of an input signal is inverted and the signal is output. For the switching element, a transistor including an oxide semiconductor in a channel formation region is used. In the case where application of a power supply voltage to the phase-inversion element is stopped, the data is stored in the capacitor, so that the data is held in the capacitor even when the application of the power supply voltage to the phase-inversion element is stopped.

Abstract: A semiconductor structure having an in situ chip-level ferrite bead inductor and method for forming the same. Embodiments include a substrate, a first dielectric layer formed on the substrate, a lower ferrite layer formed on the first dielectric layer, and an upper ferrite layer spaced apart from the lower ferrite layer in the structure. A first metal layer may be formed above the lower ferrite layer and a second metal layer formed below the upper ferrite layer, wherein at least the first or second metal layer has a coil configuration including multiple turns. At least one second dielectric layer may be disposed between the first and second metal layers. The ferrite bead inductor has a small form factor and is amenable to formation using BEOL processes.

Abstract: Provided is a semiconductor device having an ESD protection MOS transistor including a plurality of transistors combined together, in which a plurality of drain regions and a plurality of source regions disposed alternately and a gate electrode disposed between each pair of adjacent regions constituted of one of the plurality of drain regions and one of the plurality of source regions, in which a distance between a salicide metal region, which is formed on each of the plurality of drain regions, and the gate electrode is determined according to contact holes in the plurality of drain regions and a distance of the contact holes from substrate contacts.

Abstract: An inductor structure implemented within a semiconductor integrated circuit (IC) can include a coil of conductive material that includes a center terminal located at a midpoint of a length of the coil. The coil can be symmetrical with respect to a centerline bisecting the center terminal. The coil can include a first differential terminal and a second differential terminal each located at an end of the coil and opposite the center terminal. The inductor structure can include an isolation ring surrounding the coil. In some cases, the inductor structure can include a return line of conductive material positioned on the center line.

Abstract: A semiconductor device is presented here. The semiconductor device includes an integrated inductor formed on a semiconductor substrate, a transistor arrangement formed on the semiconductor substrate to modulate loop current induced by the integrated inductor, dielectric material to insulate the integrated inductor from the transistor arrangement, and a controller coupled to the transistor arrangement. The controller is used to select conductive and nonconductive operating states of the transistor arrangement. A conductive operating state of the transistor arrangement allows formation of induced loop current in the transistor arrangement, and a nonconductive operating state of the transistor arrangement inhibits formation of induced loop current in the transistor arrangement.

Abstract: Provided is a sensing device, which includes a reactive material layer (260) responding to a specific functional group in a fluid, a sensing capacitor (B) including first and second electrodes disposed on and under an insulating layer (230), the first electrode being disposed under the reactive material layer (260), and a field effect transistor including a gate electrode connected with the first electrode of the sensing capacitor. Here, the reactive material layer (260) is formed in a conductive three-dimensional structure to widen a surface area. Thus, the sensing device may have high sensitivity by maximizing a capacitor sharing effect and a change in voltage amount applied to a gate, which may be caused by widening a surface area of the conductive three-dimensional structure with respect to the fluid flow.

Abstract: An inductor is formed on a wafer by attaching a first core structure to the wafer with a pick and place operation, forming a coil with one or more thick metal layers over the first core structure, and then attaching a second core structure to the first core structure with the pick and place operation after the coil has been formed. In addition, the pick and place operation can also be used to attach one or more integrated circuits to the wafer to form an integrated inductive device.

Abstract: An inexpensive variable inductor has inductance value continuously changeable without reducing a Q value. When a control voltage is applied to a control terminal of a MOS transistor from a power supply, a continuity region is formed in a channel, and a region between main terminals becomes conductive. When the control voltage is changed, length of the continuity region in the channel is changed. This changes length of a path area of an induced current, flowing in an induced current film. Thus, the amount of induced current is increased or decreased. Therefore, when the control voltage of the MOS transistor is changed, the inductance value of the coil is continuously changed.

Abstract: A galvanic die has signal structures and a transformer structure that provide galvanically-isolated signal and power paths for a high-voltage die and a low-voltage die, which are both physically supported by the galvanic die and electrically connected to the signal and transformer structures of the galvanic die.

Abstract: The present invention relates to a semiconductor package and a method for making the same. The semiconductor package includes a base material, a first metal layer, a first dielectric layer, a first upper electrode and a first protective layer. The first metal layer is disposed on a first surface of the base material, and includes a first inductor and a first lower electrode. The first dielectric layer is disposed on the first lower electrode. The first upper electrode is disposed on the first dielectric layer, and the first upper electrode, the first dielectric layer and the first lower electrode form a first capacitor. The first protective layer encapsulates the first inductor and the first capacitor. Whereby, the first inductor and the first lower electrode of the first capacitor are disposed on the same layer, so that the thickness of the product is reduced.

Abstract: When letters are written with a ballpoint pen, pen pressure is greater than or equal to 10 MPa. The IC tag embedded in the paper base material is required to withstand such pen pressure. An integrated circuit including a functional circuit which transmits and receive, performs arithmetic of, and stores information is thinned, and also, when the integrated circuit and a structural body provided with an antenna or a wiring are attached, a second structural body formed of ceramics or the like is also attached to at the same time. When the second structural body formed of ceramics or the like is used, resistance to pressing pressure or bending stress applied externally can be realized. Further, a part of passive elements included in the integrated circuit can be transferred to the second structural body, which leads to reduction in area of the semiconductor device.

Abstract: An integrated circuit includes a first integrated circuit die having a first circuit and a first inductive interface and a second integrated circuit die having a second circuit and a second inductive interface. A substrate is coupled to support the first integrated circuit die and the second integrated circuit die, the substrate including a magnetic communication path aligned with the first inductive interface and the second inductive interface, to magnetically communicate signals between the first circuit and the second circuit.

Abstract: A semiconductor device is provided that forms a three-dimensional semiconductor device having semiconductor devices stacked on one another. In this semiconductor device, a hole is formed in a silicon semiconductor substrate that has an integrated circuit unit and an electrode pad formed on a principal surface on the outer side. The hole is formed by etching, with the electrode pad serving as an etching stopper layer. An embedded electrode is formed in the hole. This embedded electrode serves to electrically lead the electrode pad to the principal surface on the bottom side of the silicon semiconductor substrate.

Abstract: This patent pertains to a new technique of increasing the amount of energy absorbed by an antenna. It accomplishes this by broadcasting a spike that attracts the signal when the fields of its oscillating charge are at their strongest.