Abstract: A Self-Synchronized Radio Frequency RF-Interconnect (SSRFI), based on capacitor coupling and peak detection, for vertically interconnecting active device layers in three-dimensional (3D) integrated circuits (IC), as well as wireless communication and RF signal transmission/receiving.

Abstract: A capacitor insulating film for use as an insulating film sandwiched between two electrodes is made of a crystal containing a hafnium element in a titanium site in place of a part of titanium elements contained in a crystal of a strontium titanate or barium strontium titanate.

Abstract: A semiconductor device which has low input inductance is provided.

Abstract: A 4-Terminal JFET includes a substrate having a first conduction type and an upper layer having a second, opposite, conduction type over the substrate. A gate and a source are embedded in the upper layer. A gate pad is electrically connected to the gate. A region, which has a first conduction type, is formed in the upper layer and separates the upper layer into two sections. This region reduces the overall capacitance between the gate pad and the source. Reduced overall gate to source capacitance can result in reduced noise amplification in the JFET.

Abstract: An inexpensive variable inductor has inductance value continuously changeable without reducing a Q value. When a control voltage is applied to a control terminal of a MOS transistor from a power supply, a continuity region is formed in a channel, and a region between main terminals becomes conductive. When the control voltage is changed, length of the continuity region in the channel is changed. This changes length of a path area of an induced current, flowing in an induced current film. Thus, the amount of induced current is increased or decreased. Therefore, when the control voltage of the MOS transistor is changed, the inductance value of the coil is continuously changed.

Abstract: A switching circuit. The novel switching circuit includes an active device and a first circuit for providing a reactive inductive load in shunt with the active device. In an illustrative embodiment, the first circuit is implemented using a transmission line coupled between an output of the active device and ground, in parallel with the device, to minimize the parasitic effects of the device drain to source capacitance. In a preferred embodiment, the active device includes a silicon-germanium NFET optimized for operation at high frequencies (e.g. up to 20 GHz). The optimization process includes coupling a compact, low-parasitic polysilicon resistor to a gate of the NFET to provide gate RF isolation, and designing the gate manifold, drain manifold, and drain to source spacing of the NFET for optimal high frequency operation.

Abstract: An MMIC 100 is a semiconductor device which includes an FET formed on a GaAs substrate 10 and an MIM capacitor having a dielectric layer 20b arranged between a lower electrode 18b and an upper electrode 22b. A method for manufacturing the MMIC 100 is provided, in which a source electrode 16a and a drain electrode 16b of the FET are formed and then a gate electrode 18a of the FET and a lower electrode 18b of the MIM capacitor are formed simultaneously by the lift-off method.

Abstract: An inductor utilizing a pad metal layer. The inductor comprises a metal spiral, a metal bridge, and a metal interconnect. The metal bridge is formed with the pad metal layer and a plurality of vias and has one end connected to the metal spiral. The metal interconnect is connected to the other end of the metal bridge. In addition, resistivity of the pad metal layer is lower than that of the metal spiral.

Abstract: A bond wire circuit includes bond wires arranged relatively to provide a selected inductance. In connection with various example embodiments, respective bond wire loops including forward and return current paths are arranged orthogonally. Each loop includes a forward bond wire connecting an input terminal with an intermediate terminal, and a return bond wire connecting the intermediate terminal to an output terminal. The return bond wires generally mitigate return current flow from the intermediate terminal in an underlying substrate. In some implementations, the loops are arranged such that current flowing in each of the respective loops generates equal and self-cancelling current in the other of the respective loops.

Abstract: In a particular embodiment, a method of forming a field effect transistor (FET) device having a reduced peak current density is disclosed. The method includes forming a field effect transistor (FET) device on a substrate. The FET device includes a drain terminal, a source terminal, a gate terminal, and a body terminal. The method further includes depositing a plurality of metal contacts along a width of a gate terminal of the FET device and forming a wire trace to contact each of the plurality of metal contacts to reduce a gate resistance along the width of the gate terminal.

Abstract: A method for forming a structure on a surface of a semiconductor. The method includes: forming the material as a lower layer of the structure using a first deposition process to provide the lower layer with a first etch rate to a predetermined etchant; forming the upper layer of the structure with the material on the lower using a second deposition process to provide the upper layer with a second etch rate to the predetermined etchant higher than the first etch rate; and applying the predetermined etchant to upper layer to selectively remove the upper while leaving the lower layer.

Abstract: A semiconductor device is provided that forms a three-dimensional semiconductor device having semiconductor devices stacked on one another. In this semiconductor device, a hole is formed in a silicon semiconductor substrate that has an integrated circuit unit and an electrode pad formed on a principal surface on the outer side. The hole is formed by etching, with the electrode pad serving as an etching stopper layer. An embedded electrode is formed in the hole. This embedded electrode serves to electrically lead the electrode pad to the principal surface on the bottom side of the silicon semiconductor substrate.

Abstract: A semiconductor device includes a semiconductor substrate including an active element or an integrated circuit and a plurality of connection electrodes to be electrically connected to the integrated circuit; a first resin layer formed on a surface of the semiconductor substrate on which the connection electrodes are formed in such a manner avoiding the connection electrodes; a connection wiring layer formed between the semiconductor substrate and the first resin layer and connected to one of the plurality of connection electrodes; a Cu wiring layer connected at one end thereof to the connection wiring layer and formed on the surface of the first resin layer; a passive element composed of the connection wiring layer and the Cu wiring layer; a second resin layer for covering a surface of the Cu wiring layer; and an external terminal electrically connected to some of the plurality of connection electrodes and formed such that a portion of the second resin layer protrudes from the second resin layer.

Abstract: The inductor for a semiconductor device includes at least one dielectric pattern selectively formed on a top of the interlayer dielectric, at least one first metal wire formed on a top of the interlayer dielectric, at least one second metal wire formed on a top of the dielectric pattern, and an upper protective film formed on the top of the interlayer dielectric to completely cover the first and second metal wires, wherein the first and second metal wires are alternately arranged at different vertical locations and are formed in a spiral configuration.

Abstract: The invention provides an electronic component which has an improved breakdown limit value of withstand voltage and improved insulation properties and which can be made compact and provided with a multiplicity of layers and a great capacity. The electronic component includes a first conductor having a bottom conductor formed on a substrate and a raised conductor formed to protrude from the bottom conductor, a dielectric film formed on the raised conductor, and a second conductor formed on the dielectric film to constitute a capacitor element in combination with the raised conductor and the dielectric film.

Abstract: An integrated circuit includes a first integrated circuit die having a first circuit and a first inductive interface and a second integrated circuit die having a second circuit and a second inductive interface. A substrate is coupled to support the first integrated circuit die and the second integrated circuit die, the substrate including a magnetic communication path aligned with the first inductive interface and the second inductive interface, to magnetically communicate signals between the first circuit and the second circuit.

Abstract: A method for manufacturing a high-frequency signal transmission circuit includes the steps of forming a groove to surround a first region on a semiconductor substrate, filling the groove with a stopper material, forming a high-frequency transmission line on the semiconductor substrate so that the transmission line extends over the first region, and etching the first region of the semiconductor substrate using the stopper material as an etching stopper to form a recess in the first region.

Abstract: A spiral inductor, which is formed of a spiral wiring pattern, is formed in an inductor formation region which is assigned within an IC chip. A plurality of dummy wiring lines are formed according to a given design rule on an inside region surrounded by the spiral inductor within the inductor formation region and on an outside region of the spiral inductor within the inductor formation region. Each of the plurality of dummy wiring lines is formed to have such a shape that at least one side of a closed loop is opened, and the plurality of dummy wiring lines are disposed to have regularity and/or uniformity at a given distance from the spiral inductor.

Abstract: Disclosed are embodiments of a circuit (e.g., an electrostatic discharge (ESD) circuit), a design methodology and a design system. In the circuit, an ESD device is wired to a first metal level (e.g., M1). An inductor is formed in a second metal level (e.g., M5) above the first metal level and is aligned over and electrically connected in parallel to the ESD device by a single vertical via stack. The inductor is configured to nullify, for a given application frequency, the capacitance value of the ESD device. The quality factor of the inductor is optimized by providing, on a third metal level (e.g., M3) between the second metal level and the first metal level, a shield to minimize inductive coupling. An opening in the shield allows the via stack to pass through, trading off Q factor reduction for size-scaling and ESD robustness improvements.

Abstract: A microelectronic assembly and a method for forming the same are provided. The method includes forming first and second lateral etch stop walls (44, 46) in a semiconductor substrate (20) having first and second opposing surfaces (22, 24). An inductor (56) is formed on the first surface (22) of the semiconductor substrate (20) and a hole (60) is formed through the second surface (24) of the substrate (20) to expose the substrate (20) between the first and second lateral etch stop walls (44, 46). The substrate (20) is isotropically etched between the first and second lateral etch stop walls (44, 46) through the etch hole (60) to create a cavity 62) within the semiconductor substrate (20). A sealing layer (70) is formed over the etch hole (60) to seal the cavity (62).

Abstract: An inductor with plural coil layers includes a base wafer; a plurality of insulating layers sequentially laminated on one surface of the base wafer; and a plurality of coil layers built in the plurality of insulating layers, respectively, and having different magnetic flux passage areas.

Abstract: It is an object of the present invention to provide a semiconductor device capable of additionally recording data at a time other than during manufacturing and preventing forgery due to rewriting and the like. Moreover, another object of the present invention is to provide an inexpensive, nonvolatile, and highly-reliable semiconductor device. A semiconductor device includes a first conductive layer, a second conductive layer, and an organic compound layer between the first conductive layer and the second conductive layer, wherein the organic compound layer can have the first conductive layer and the second conductive layer come into contact with each other when Coulomb force generated by applying potential to one or both of the first conductive layer and the second conductive layer is at or over a certain level.

Abstract: A multilayer winding inductor. The inductor at least includes multi-level interconnect and single-level interconnect structures. The multi-level interconnect structure includes a plurality of conductive plugs and a plurality of looped conductive traces overlapping and separated from each other. Each looped conductive trace has a gap to define first and second ends and at least two conductive plugs disposed between the neighboring looped conductive traces. The single-level interconnect structure is located over the multi-level interconnect structure, comprising an uppermost looped conductive trace and a second conductive plug. The uppermost looped conductive trace has a gap to define first and second ends, and the second conductive plug is disposed between the second end of the uppermost looped conductive trace and the first end of the looped conductive trace adjacent thereto, thereby electrically connecting the multi-level and single-level interconnect structures.

Abstract: A signal transmission arrangement includes a transformer and a receiver circuit. The transformer has at least one primary winding and at least one secondary winding, each having first and second connections. The receiver circuit is connected to the secondary winding, and has an input and at least one output. The receiver circuit also has a differential input resistance approximating a short circuit. The receiver circuit is configured to convert a current pulse received at the input via the secondary winding to a voltage provided at the at least one output.

Abstract: A semiconductor device including inductors with improved reliability and a method of manufacturing the same are provided. The semiconductor device may include a substrate, an insulating film pattern formed on the substrate and having an opening, an amorphous metal nitride film formed inside the opening, a diffusion reducing or preventing film formed on the amorphous metal nitride film, and a conductive film including the diffusion reducing or preventing film filling the inside of the opening.

Abstract: An improved electromagnetic shielding structure has been discovered. In one embodiment of the invention, an apparatus includes an inductor and an electrically conductive enclosure that electromagnetically shields the inductor. The electrically conductive enclosure has an aperture at least as large as the inductor. The aperture is substantially centered around a projected surface of the inductor. The apparatus may include one or more electrically conductive links extending across the aperture and electrically coupled to the electrically conductive enclosure. The electrically conductive links reduce an effect of electromagnetic signals external to the electrically conductive enclosure on the inductor.

Abstract: A semiconductor device includes a capacitor which includes a capacitor insulating film at least including a first insulating film and a ferroelectric film formed in contact with the first insulating film, containing a compound of a preset metal element and a constituent element of the first insulating film as a main component and having a dielectric constant larger than that of the first insulating film, a first capacitor electrode formed of one of Cu and a material containing Cu as a main component, and a second capacitor electrode formed to sandwich the capacitor insulating film in cooperation with the first capacitor electrode.

Abstract: A method for fabricating a circuitry component includes providing a semiconductor substrate, a first coil over said semiconductor substrate, a passivation layer over said first coil; and depositing a second coil over said passivation layer and over said first coil. Said second coil may be deposited by forming a first metal layer over said passivation layer, forming a pattern defining layer over said first metal layer, a first opening in said pattern defining layer exposing said first metal layer, forming a second metal layer over said first metal layer exposed by said first opening, removing said pattern defining layer, and removing said first metal layer not under said second metal layer.

Abstract: The present invention discloses capacitors having via connections and electrodes designed such that they provide a low inductance path, thus reducing needed capacitance, while enabling the use of embedded capacitors for power delivery and other uses. One embodiment of the present invention discloses a capacitor comprising the following: a top capacitor electrode and a bottom capacitor electrode, wherein the top electrode is smaller than the bottom electrode, comprising, on all sides of the capacitor; in an array, a multiplicity of vias located on all sides of the top and bottom capacitor electrodes, wherein the top electrode and the vias connecting to the top electrode act as an inner conductor, and the bottom electrode and the vias connecting to the bottom electrode act as an outer conductor.

Abstract: An MMIC 100 is a semiconductor device which includes an FET formed on a GaAs substrate 10 and an MIM capacitor having a dielectric layer 20b arranged between a lower electrode 18b and an upper electrode 22b. A method for manufacturing the MMIC 100 is provided, in which a source electrode 16a and a drain electrode 16b of the FET are formed and then a gate electrode 18a of the FET and a lower electrode 18b of the MIM capacitor are formed simultaneously by the lift-off method.

Abstract: An integrated microwave transistor amplifier includes a AlGaN/GaN active transistor arrangement on a thinned Si 1-mil heat spreader. Elongated, plated-through vias extend from the source portions of the transistor arrangement through the spreader to a thick gold supporting layer. A matching circuit is defined on a four-mil GaAs substrate, also with a thick gold support layer. A stepped heat sink supports the matching circuit and the active transistor with surfaces coplanar. Bond wires interconnect the matching circuit with the gate or drain connections of the transistor.

Abstract: A fast, reliable, highly integrated memory device formed of a carbon nanotube memory device and a method for forming the same, in which the carbon nanotube memory device includes a substrate, a source electrode, a drain electrode, a carbon nanotube having high electrical and thermal conductivity, a memory cell having excellent charge storage capability, and a gate electrode. The source electrode and drain electrode are arranged with a predetermined interval between them on the substrate and are subjected to a voltage. The carbon nanotube connects the source electrode to the drain electrode and serves as a channel for charge movement. The memory cell is located over the carbon nanotube and stores charges from the carbon nanotube. The gate electrode is formed in contact with the upper surface of the memory cell and controls the amount of charge flowing from the carbon nanotube into the memory cell.

Abstract: A semiconductor display device with an interlayer insulating film in which surface levelness is ensured with a limited film formation time, heat treatment for removing moisture does not take long, and moisture in the interlayer insulating film is prevented from escaping into a film or electrode adjacent to the interlayer insulating film. A TFT is formed and then a nitrogen-containing inorganic insulating film that transmits less moisture compared to organic resin film is formed so as to cover the TFT. Next, organic resin including photosensitive acrylic resin is applied and an opening is formed by partially exposing the organic resin film to light. The organic resin film where the opening is formed, is then covered with a nitrogen-containing inorganic insulating film which transmits less moisture than organic resin film does.

Abstract: An integrated matching network and method for manufacturing an integrated matching network are provided. The method includes forming (405) a first die on a substrate, forming (410) a second die on the substrate, and forming (415) a metallization layer on the first and second dies. The second die has a capacitance, the metallization layer has an inductance, and the capacitance and inductance together provide a shunt impedance from the first die to the substrate. The integrated matching network includes a first die having a PA (101), a second die having a capacitor (102), and a metal interconnect (108) coupled to the PA and the first capacitor. The metal interconnect (108) has an inductance. The capacitor (102) and metal interconnect (108) form a shunt impedance.

Abstract: A power semiconductor device that includes a passive component, e.g., a capacitor, mechanically and electrically coupled to at least one pole thereof.

Abstract: A field effect transistor (FET) device includes a gate conductor and gate dielectric formed over an active device area of a semiconductor substrate. A drain region is formed in the active device area of the semiconductor substrate, on one side of the gate conductor, and a source region is formed in the active device area of the semiconductor substrate, on an opposite side of the gate conductor. A dielectric halo or plug is formed in the active area of said semiconductor substrate, the dielectric halo or plug disposed in contact between the drain region and a body region, and in contact between the source region and the body region.

Abstract: The semiconductor apparatus includes a pad; a first line layer placed immediately beneath the pad; and a lattice-shaped contact being between the pad and the first line layer.

Abstract: In one embodiment, a filter structure includes first and second filter devices formed using a semiconductor substrate. A vertical ground plane structure prevents cross-coupling between the first and second filter devices.

Abstract: A method for fabricating a thermally stable ultralow dielectric constant film including Si, C, O and H atoms in a parallel plate chemical vapor deposition process utilizing a plasma enhanced chemical vapor deposition (“PECVD”) process is disclosed. Electronic devices containing insulating layers of thermally stable ultralow dielectric constant materials that are prepared by the method are further disclosed. To enable the fabrication of a thermally stable ultralow dielectric constant film, specific precursor materials are used, such as, silane derivatives, for instance, diethoxymethylsilane (DEMS) and organic molecules, for instance, bicycloheptadiene and cyclopentene oxide.

Abstract: According to one aspect of the present invention, a method is provided for forming a microelectronic assembly. The method comprises forming first and second trenches on a semiconductor substrate, filling the first and second trenches with an etch stop material, forming an inductor on the semiconductor substrate, forming an etch hole in at least one of the etch stop layer and the semiconductor substrate to expose the substrate between the first and second trenches, isotropically etching the substrate between the first and second trenches through the etch hole to create a cavity within the substrate, and forming a sealing layer over the etch hole to seal the cavity.

Abstract: The present invention discloses a fabrication method and structure of spiral RF inductor on porous glass substrate. Thick porous silicon layer is natively formed on a silicon wafer by anodic etching the silicon material to a high degree of porosity. The porous silicon is than thermally oxidized at high temperature converting it into porous glass texture. The oxidation rate can be rapid due to open pore character of the etched structure, which allows oxidizing agents to penetrate deeply into the wafer. If the porosity is large enough, the pores will not be sealed by the expansion of oxide during the oxidation, which results a porous structure of glass-and-air mixture of low relative dielectric constant slightly over a value of 2. The final holes appear on the wafer surface can be sealed by CVD coating step, if necessary. This ultra-flat, low-k, silicon-based substrate allows RF spiral inductor to be made on its surface with excellently low loss, or high Q value.

Abstract: Container structures for use in integrated circuits and methods of their manufacture. The container structures have a dielectric cap on the top of a conductive container to reduce the risk of container-to-container shorting by insulating against bridging of conductive debris across the tops of adjacent container structures. The container structures are adapted for use in memory cells and apparatus incorporating such memory cells, as well as other integrated circuits.

Abstract: Plural trench isolation films (4) are provided with portions of an SOI layer (3) interposed therebetween in a surface of the SOI layer (3) in a resistor region (RR) where a spiral inductor (SI) is to be provided. Resistive element (30) are formed on the trench isolation films (4), respectively. Each of the trench isolation films (4) includes a central portion which passes through the SOI layer (3) and reaches a buried oxide film (2) to include a full-trench isolation structure, and opposite side portions each of which passes through only a portion of the SOI layer (3) and is located on the SOI layer 3 to include a partial-trench isolation structure. Thus, each of the trench isolation films (4) includes a hybrid-trench isolation structure.

Abstract: It is an object to obtain a semiconductor device including a capacitance having a great Q-value. In an SOI substrate comprising a support substrate (165), a buried oxide film (166) and an SOI layer (171), an isolating oxide film 167 (167a to 167c) is selectively formed in an upper layer portion of the SOI layer (171) with a part of the SOI layer (171) remaining as a P? well region (169). Consequently, an isolation (partial isolation) structure is obtained. An N+ diffusion region (168) is formed in the SOI layer (171) between the isolating oxide films (167a) and (167b) and a P+ diffusion region (170) is formed in the SOI layer (171) between the isolating oxide films (167b) and (167c). Consequently, there is obtained a junction type variable capacitance (C23) having a PN junction surface of the P? well region (169) provided under the isolating oxide film (167b) and the N+ diffusion region (168).

Abstract: A high frequency switch, has a transmitting terminal, a receiving terminal, an antenna terminal, a first diode having an anode electrically connected to the transmitting terminal and a cathode electrically connected to the antenna terminal, a second diode having an anode connected through a transmission line of ¼ wavelength to the antenna terminal which is electrically connected to the receiving terminal, and having the side of a cathode grounded, and a control terminal provided to a node between the transmitting terminal and the first anode. The first and second diodes have a tradeoff relationship between ON resistance thereof and capacitance between the anode and the cathode, and the ON resistance of the first diode is lower than the ON resistance of the second diode, and the capacitance of the second diode in the OFF state is smaller than the capacitance of the first diode in the OFF state.

Abstract: A method of forming memory circuitry having a memory array having a plurality of memory capacitors and having peripheral memory circuitry operatively configured to write to and read from the memory array, includes forming a dielectric well forming layer over a semiconductor substrate. A portion of the well forming layer is removed effective to form at least one well within the well forming layer. An array of memory cell capacitors is formed within the well. The peripheral memory circuitry is formed laterally outward of the well forming layer memory array well. In one implementation, memory circuitry includes a semiconductor substrate. A plurality of word lines is received over the semiconductor substrate. An insulative layer is received over the word lines and the substrate. The insulative layer has at least one well formed therein. The well has a base received over the word lines. The well peripherally defines an outline of a memory array area.

Abstract: The present invention relates to integrated circuits having symmetric inducting devices with a ground shield. In one embodiment, a symmetric inducting device for an integrated circuit comprises a substrate, a main metal layer and a shield. The substrate has a working surface. The main metal layer has at least one pair of current path regions. Each of the current path region pairs is formed in generally a regular polygonal shape that is generally symmetric about a plane of symmetry that is perpendicular to the working surface of the substrate. The shield is patterned into segments that are generally symmetric about the plane of symmetry. Medial portions of at least some segments of the shield are formed generally perpendicular to the plane of symmetry as the medial portions cross the plane of symmetry.

Abstract: An integrated circuit (10) includes a semiconductor substrate (11) that has a top surface (32) for forming a dielectric region (14) with a trench (40) and one or more adjacent cavities (16). A conductive material such as copper is disposed within the trench to produce an inductor (50). A top surface (49) of the inductor is substantially coplanar with an interconnect surface (31) of the semiconductor substrate, which facilitates connecting to the inductor with standard integrated circuit metallization (57).

Abstract: The present invention relates to integrated circuits having symmetric inducting devices with a ground shield. In one embodiment, a symmetric inducting device for an integrated circuit comprises a substrate, a main metal layer and a shield. The substrate has a working surface. The main metal layer has at least one pair of current path regions. Each of the current path region pairs is formed in generally a regular polygonal shape that is generally symmetric about a plane of symmetry that is perpendicular to the working surface of the substrate. The shield is patterned into segments that are generally symmetric about the plane of symmetry. Medial portions of at least some segments of the shield are formed generally perpendicular to the plane of symmetry as the medial portions cross the plane of symmetry.

Abstract: A semiconductor device comprises a semiconductor substrate and a capacitor provided above the semiconductor substrate, the capacitor comprises a lower electrode containing metal, a dielectric film containing tantalum oxide or niobium oxide, an upper electrode containing metal, and at least one of a lower barrier layer which is provided between the lower electrode and the dielectric film and an upper barrier layer which is provided between the upper electrode and the dielectric film, the lower barrier layer and the upper barrier layer being insulating layers which contain silicon and oxygen and containing the oxygen at least in a portion on a side contacting the dielectric film.