Abstract: Structures and methods for fabricating high speed digital, analog, and combined digital/analog systems using planarized relaxed SiGe as the materials platform. The relaxed SiGe allows for a plethora of strained Si layers that possess enhanced electronic properties. By allowing the MOSFET channel to be either at the surface or buried, one can create high-speed digital and/or analog circuits. The planarization before the device epitaxial layers are deposited ensures a flat surface for state-of-the-art lithography. In accordance with one embodiment of the invention, there is provided a semiconductor structure including a planarized relaxed Si1−xGex layer on a substrate; and a device heterostructure deposited on said planarized relaxed Si1−xGex layer including at least one strained layer.

Abstract: A structure and a process for manufacturing semiconductor devices with improved ESD protection for high voltage applications is described. A thick field gate oxide N channel field effect transistor (FET) device with a tunable threshold voltage (Vt) is developed at the input/output to the internal active circuits for the purpose of providing ESD protection for applications in the 9 volt and higher range. The FET threshold voltage determines the ESD protection characteristics. A N-field implant is used to provide a dopant region under the thick oxide gate element which has the effect of modifying the threshold voltage (Vt) of this device enabling the device turn-on to be “tuned” to more closely match the application requirements of the internal semiconductor circuits. The gate electrical contact is completed by using either a metal gate electrode or polysilicon gate element.

Abstract: An integrated circuit is provided with one or more connectors which allow an opto-electric device to be mounted on the integrated circuit directly on top of or underneath of it. Multiple opto-electric device interface regions can be defined on the integrated circuit such that an opto-electric device can be connected in a variety of directions or such that multiple opto-electric devices can be connected. In addition, an opto-electric device interface may be provided that causes the opto-electric device's leads to be directed to the corresponding integrated circuit lead in the shortest possible distance regardless of how the opto-electric device is positioned. Also disclosed is a substrate-mounted optical transmission system that may be used in connection with the opto-electric device.

Abstract: The present invention provides a memory structure, comprising: a substrate; a gate oxide layer disposed on a portion of the substrate; a gate structure disposed on the gate oxide layer; a buried bit line disposed in the substrate along both sides of the gate structures; a raised line disposed on the burled bit line; an isolating spacer disposed on both sidewalls of the gate structure and a word line disposed over the substrate in a direction perpendicular to the buried bit line; and an insulation layer disposed on a top of the raised line to electrically isolate the raised line and the word line.

Abstract: The present invention relates to a transistor in a semiconductor device and method of manufacturing the same, more particularly to a new dual gate P+ salicide forming technology having an elevated channel and a source/drain using the selective SiGe epi-silicon growth technology. It relates to manufacturing of a high performance surface channel PMOS salicide that has a number of beneficial effects.

Abstract: An electronic device has a plurality of electrically conductive first nanowires, a layer system applied on the first nanowires, and also second nanowires applied on the layer system. The first and second nanowires are arranged skew with respect to one another. The layer system is set up in such a way that charge carriers generated by the nanowires can be stored in the layer system.

Abstract: A semiconductor switching device of mirror logic includes two FETs having a gate width of 600 &mgr;m, a common input terminal, two control terminal and two output terminals. The resistors connecting the control terminals and the gate electrodes of FETs are placed underneath a pad metal layer extending from the common input terminal. Both FETs extend into the space between the control terminals and the output terminals. The device can be housed in the same package as the device of non-mirror logic.

Abstract: An FET (Field Effect Transistor) has an epitaxial wafer including an Al0.2Ga0.8As gate contact layer. A GaAs gate buried layer doped with Si, Al0.2Ga0.8As wide-recess stopper layer doped with Si, an undoped GaAs layer and a GaAs cap layer doped with Si are sequentially formed on the gate contact layer by epitaxial growth. An electron accumulation layer is formed on the undoped GaAs layer and reduces a potential barrier. This allows electrons to pass through the potential barrier of the AlGaAs layer with higher probability. Because the GaAs layer is not doped with an impurity, electrons are scattered little and achieve higher mobility. It is therefore possible to reduce contact resistance from the cap layer to a channel layer. In addition, sheet resistance sparingly increases because the gate contact layer is not exposed to the outside. An ON resistance as low as 1.4 &OHgr;·mm is achievable which is lower than the conventional ON resistance by 0.2 &OHgr;·mm.

Abstract: A MOS transistor and a method for fabricating the same include producing a well doped by a first conductivity type in a semiconductor substrate. An epitaxial layer having a dopant concentration of less than 1017 cm−3 is disposed on a surface of the doped well. Source/drain regions doped by a second conductivity type, opposite to the first conductivity type, and a channel region, are disposed in the epitaxial layer, and their depth is less than or equal to the thickness of the epitaxial layer. A method for fabricating two complementary MOS transistors is also provided.

Abstract: The conventional compound semiconductor switching device is prone to have a large chip size as the gate width needs to be large for achieving a low insertion loss and the separation between the connecting pad and the circuit wiring needs to be larger than 20 &mgr;m for obtaining a proper isolation between them. The overall chip size is reduced, first, by reducing the gate width of the switching FET operating at frequencies above 2.4 GHz to 700 &mgr;m or smaller together with the omission of the shunt FET, and, then, by reducing the separation between the connecting pad and the circuit wiring to 20 &mgr;m or smaller. This reduction of the separation is made possible by the introduction of an insulating film and a impurity region between the outermost portion of the connecting pad and the substrate for preventing the extension of the depletion layer.

Abstract: A semiconductor switching device includes two FETs with different device characteristics, a common input terminal, and two output terminals. A signal transmitting FET has a gate width of 500 &mgr;m and a signal receiving FET has a gate width of 400 &mgr;m. A resistor connecting a gate electrode and a control terminal of the signal transmitting FET is tightly configured to provide expanding space for the FET. Despite the reduced size, the switching device can allow a maximum power of 22.5 dBm to pass through because of the asymmetrical device design. The switching device operates at frequencies of 2.4 GHz or higher without use of shunt FET.

Abstract: A heterojunction bipolar transferred electron tetrode has an anode region providing a first terminal, an active region in which Gunn-Hilsum oscillations are generated, a base region providing a second terminal, a cathode region providing a third terminal, and a fourth terminal which is operable independently of the three terminals. The fourth terminal can take the form of a second cathode-type structure, a second base region or a Schottky gate electrode. The cathode region and fourth terminal are in proximity enough to each other such that one of the cathode region and the fourth terminal is usable as an input terminal and that the other of the cathode region and the fourth terminal is usable as a terminal to which an electrical signal for disturbing an electric field profile or a current density in the active region is applied.

Abstract: Off-current is not compromised in a field effect transistor having a gate length less than 100 nanometers in length by maintaining the conduction channel width one-half to one-quarter of the gate length and locating the gate on at least two sides of the conduction channel and to thus create a full depletion device. Such a narrow conduction channel is achieved by forming a trough at minimum lithographic dimensions, forming sidewalls within the trough and etching the gate structure self-aligned with the sidewalls. The conduction channel is then epitaxially grown from the source structure in the trough such that the source, conduction channel and drain region are a unitary monocrystalline structure.

Abstract: The object of the present invention is to suppress a short channel effect on a threshold voltage. A channel region 5, a pair of source-drain regions and an isolating film 2 having a trench isolation structure are selectively formed in a main surface of a semiconductor substrate 1. An upper surface of the isolating film 2 recedes to be lower than an upper surface of the channel region 5 in a trench portion adjacent to side surfaces of the channel region 5 and to be almost on a level with the upper surface of the channel region 5 in other regions. Consequently, a part of the side surfaces of the channel region 5 as well as the upper surface thereof are covered by a gate electrode 4 with a gate insulating film 3 interposed therebetween. A channel width W of the channel region 5 is set to have a value which is equal to or smaller than a double of a maximum channel depletion layer width Xdm.

Abstract: The present invention relates to a semiconductor device with one or more current confinement regions and to a method of manufacturing such a device, particularly buried heterostructure light emitting devices such as semiconductor lasers and light emitting diodes. The device comprises an active layer, a current conduction region, one or more current confinement regions adjacent the current conduction region. The current conduction region and current confinement region are arranged to channel an applied electric current to the active layer. The or each current confinement region includes both a metal-doped current blocking structure and a p-n junction current blocking structure. The p-n current blocking structure is between the current conduction region and the metal-doped current blocking structure.

Abstract: An electronic device on a semiconductor substrate can include first and second field effect transistors on a substrate. In particular, the first field effect transistor includes a first gate dielectric layer having a first nitrogen concentration, and the second field effect transistor includes a second gate dielectric layer having a second nitrogen concentration lower than the first nitrogen concentration. More particularly, the first field effect transistor can be a PMOS transistor, and the second field effect transistor can be an NMOS transistor. Related methods are also discussed.

Abstract: A semiconductor device of the present invention comprises Al0.3Ga0.7N layer 4 and Al0.1Ga0.9N layer 5 having different Al contents as an electron supply layer on GaN layer 6 serving as an active layer. An area where Al0.3Ga0.7N layer 4 is formed is used as a low resistance area, while an area where Al0.1Ga0.9N layer 5 is formed is used as a high resistance area. As a result, a distribution of two-dimensional electrons serving as carriers is produced within a horizontal plane perpendicular to the thickness direction of the layers to form a desired device configuration. For example, when the configuration is applied to a transistor configuration, a channel concentration under a gate is reduced to improve withstand voltage between the gate and a drain, and at the same time, a channel concentration in source and drain areas is increased to realize low contact resistance.

Abstract: A method of selectively forming contact regions on a substrate having a plurality of exposed regions includes selectively forming a contact region on each of the exposed regions of the substrate. During formation, each contact region has a first growth rate in a first direction and a second growth rate in a second direction. While each contact region is being selectively formed on the respective exposed region, the contact region is heated to increase the first growth rate of the contact region in the first direction relative to the second growth rate of the contact region in the second direction. The first growth rate may be a vertical growth rate and the second growth rate may be a lateral growth rate. The contact may be heated by applying electromagnetic radiation to an upper surface of the substrate and not applying the radiation to the vertical portions of the contact region to thereby increase the vertical growth rate relative to the lateral growth rate.

Abstract: The present invention relates to a semiconductor device (1) with one or more current confinement regions (20,45) and to a method of manufacturing such a device, particularly buried heterostructure light emitting devices such as semiconductor lasers and light emitting diodes. The device (1) comprises an active layer (10), a current conduction region (4), one or more current confinement regions (20,45) adjacent the current conduction region. The current conduction region (4) and current confinement region (20,45) are arranged to channel an applied electric current to the active layer (10). The or each current confinement region includes both a metal-doped current blocking structure (45) and a p-n junction current blocking structure (20). The p-n current blocking structure (20) is between the current conduction region (4) and the metal-doped current blocking structure (45).

Abstract: A high voltage microwave field effect transistor (FET) and method for its manufacture. The FET (10) includes a channel layer (18) formed of compressively strained GaInP. Carrier confinement layers (16), (20) formed of tensile strained (AlGa)InP are formed both above (20) and below (16) the channel layer (20) to confine the carriers to the channel layer (20) and to provide a high breakdown voltage.

Abstract: The present invention relates to a heterojunction structure based upon the oxide/high-k dielectric barrier. In exemplary embodiment, a silicon layer has a silicon dioxide layer thereon, and a high-k dielectric material disposed on the oxide layer. Thereafter, a metal layer, serving as the gate metal for the device is disposed on the high-k dielectric. The silicon dioxide layer has a relatively high barrier height, but has a relatively small thickness, and relative to the high-k dielectric, the barrier height differential fosters real space transfer. In this structure, the high barrier height of the silicon dioxide layer results in higher mobility and thereby greater substrate current. By virtue of the relative thick layer of high-k dielectric, leakage current is significantly reduced.

Abstract: A semiconductor device includes: a substrate; a buffer layer including GaN formed on the substrate, wherein surfaces of the buffer layer are c facets of Ga atoms; a separating layer including (InXAl1-X)YGa1-YN (where 0≦X≦1, 0≦Y≦1) formed on the buffer layer, wherein surfaces of the separating layer are c facets of In, Al, or Ga atoms; a channel layer including GaN, InGaN, or a combination of GaN and InGaN formed on the separating layer, wherein surfaces of the channel layer are c facets of Ga or In atoms; and an electron supply layer including AlGaN formed on the channel layer, wherein surfaces of the electron supply layer are c facets of Al or Ga atoms, wherein the AlN composition ratio in the separating layer is smaller than the AlN composition ratio in the electron supply layer.

Abstract: Heterostructure field-effect transistors (HFETs) and other electronic devs are fabricated from a series of semiconductor layers to have reduced impact ionization. On to a first barrier layer there is added a unique second subchannel layer having high quality transport properties for reducing impact ionization. A third barrier layer having a controlled thickness to permit electrons to tunnel through the layer to the subchannel layer is added as a spacer for the fourth main channel layer. A fifth multilayer composite barrier layer is added which has at least a barrier layer in contact with the fourth channel layer and on top a sixth cap layer is applied. The device is completed by adding two ohmic contacts in a spaced apart relationship on the sixth cap layer with a Schottky gate between them which is formed in contact with the fifth barrier layer.

Abstract: A new quantum well MOS transistor is described along with a processes for manufacturing it. In this transistor, the source and drain areas are separated from the channel by sufficiently thin insulating layers to enable the passage of charge carriers by the tunnel effect. Each of the source and drain areas is separated from the substrate by an electrically insulating layer that is sufficiently thick to prevent charge carriers from passing through this insulating layer.

Abstract: A quantum wire switch and a switching method for switching charge carriers between a first output and a second output utilizing quantum interference of the charge carriers. A quantum switch includes a quantum wire extending from an input to a first output, a second quantum wire extending from the input to a second output, and a third quantum wire extending between the first and second outputs, the three quantum wires together defining a ring. A controllable-length quantum wire electron stub tuner is connected to the ring. As charge carriers propagate from the input around the ring the stub tuner is used to control the quantum interference of the charge carriers resulting in local maxima and minima at various points around the ring. Setting the stub to a first length results in a local maximum at the first output and a local minimum at the second output, and the charge carriers can propagate to the first output and not the second output.

Abstract: A semiconductor integrated circuit comprising a first functional block consisting essentially of a first circuit which includes a small junction device, and a second functional block consisting essentially of a second circuit which includes a field effect transistor, the second functional block being mutually connected to the first functional block.

Abstract: A quantum wire switch and a switching method for switching charge carriers between a first output and a second output utilizing quantum interference of the charge carriers. A quantum switch includes a quantum wire extending from an input to a first output, a second quantum wire extending from the input to a second output, and a third quantum wire extending between the first and second outputs, the three quantum wires together defining a ring. A controllable-length quantum wire electron stub tuner is connected to the ring. As charge carriers propagate from the input around the ring the stub tuner is used to control the quantum interference of the charge carriers resulting in local maxima and minima at various points around the ring. Setting the stub to a first length results in a local maximum at the first output and a local minimum at the second output, and the charge carriers can propagate to the first output and not the second output.

Abstract: A semiconductor device exploiting a quantum interference effect is disclosed. The device comprises: a semiconductor body; n-1 (n.gtoreq.3) rods of forbidden regions extending along one direction, the forbidden regions being rotationally asymmetric around the one direction and being changeable in cross sectional area; a channel region consisting of a plurality of elemental channel regions, the forbidden regions dividing the channel region into the plurality of elemental channel regions, each of the elemental channel regions forming a closed circuit and being defined around each of the forbidden regions, the channel region being multiply connected with connectivity of n; and source and drain electrodes electrically connected to one and another ends of the channel region along the one direction.

Abstract: A semiconductor substrate has a surface layer disposed underneath a gate electrode of a field-effect transistor and having a resistance higher than the resistance of an inner layer which is formed in the semiconductor substrate below the surface layer. The surface layer is formed when a donor doped in the surface layer and an acceptor generated based on a compressive stress which is developed in the surface layer when the gate electrode is formed substantially cancel out each other. The field-effect transistor operates alternatively as a junction field-effect transistor when the surface layer is turned into a p-type structure when a compressive stress is generated in the surface layer and a metal semiconductor field-effect transistor when the surface layer is turned into an n-type structure when a tensile stress is generated in the surface layer.

Abstract: A semiconductor device according to the invention is characterized by comprising a heterostructure which comprises an active layer in which carriers can flow within a conduction channel, the heterostructure including a recessed region in which part of the conduction channel is disposed and substantially in the same plane as a pair of side gate, thereby defining a restricted conduction region of the conduction channel.

Abstract: A tunnel transistor including source and drain and a silicon oxide tunneling layer overlying the source. A polysilicon quantum well layer positioned on the tunneling layer and in contact with the drain. The quantum well layer having a thickness which places the ground state above the Fermi level. A silicon oxide insulating layer positioned on the quantum well layer and a gate electrode positioned on the insulating layer overlying the quantum well layer and the source terminal. The tunneling layer being thin enough to allow tunneling between the source and the quantum well layer, and the insulating layer being thick enough to prevent tunneling therethrough.

Abstract: An Si-doped AlInAs layer and an intrinsic AlInAs layer are successively grown on a semi-insulating InP substrate in a molecular beam epitaxy chamber. The sample is then heat-treated in a nitrogen ambient at 400.degree. C. for 18 minutes so that electrical characteristics of the sample are deteriorated because of the infiltration of fluorine into the Si-doped AlInAs layer. The sample is then placed in the molecular beam epitaxy chamber and reheat-treated in an ultra-high vacuum at 400.degree. C. for seven minutes and the fluorine is removed.

Abstract: A thin film transistor includes, a) a thin film source region; b) a thin film drain region; c) a polycrystalline thin film channel region intermediate the thin film source region and the thin film drain region; d) a transistor gate and gate dielectric operatively positioned adjacent the thin film channel region; and e) the thin film channel region comprising at least an inner layer, an outer layer and a middle layer sandwiched between the inner layer and the outer layer, the inner layer and the outer layer comprising polycrystalline silicon and having respective energy bandgaps, the middle sandwich layer comprising a polycrystalline material and having a lower energy bandgap than either of the inner and outer layers. Alternately, the channel region is homogeneous, comprising germanium or an alloy of polycrystalline silicon and germanium.

Abstract: A field effect transistor has a quantum dot array in its channel region. The quantum dot array is composed of a plurality of quantum dots arranged adjacent to each other on a common plane. Each quantum dot may be made of heterojunction of compound semiconductors or junction of a semiconductor and an insulator. The field effect transistor has a differential negative resistance.

Abstract: A complementary III-V heterostructure field effect device includes the same refractory ohmic material for providing the contacts (117, 119), to both the N-type and P-type devices. Furthermore, the refractory ohmic contacts (117, 119) directly contact the InGaAs channel layer (16) to provide improved ohmic contact, despite the fact that the structure incorporates an advantageous high aluminum composition barrier layer (18) and an advantageous GaAs cap layer (20).

Abstract: A heterojunction FET includes an electron supply layer formed on a non-doped semiconductor layer serving as a channel forming layer and a current path forming layer formed on the electron supply layer. The electron supply layer has an energy band gap greater than the non-doped semiconductor layer and its portion under a gate electrode is always depleted at any gate bias voltage in a bias voltage range for operating of the field effect transistor. The current path forming layer has a larger electron mobility than the electron supply layer. The gate electrode is formed on the current supply layer. Under a high gate bias voltage condition, parallel conduction does not occur in the electron supply layer but does occur in the current path forming layer. Since the current path forming layer has a larger carrier mobility than the electron supply layer, the mutual conductance value is kept high.

Abstract: Quantum well structures are fabricated by use of a process employing a Focused Ion Beam (FIB) scanning in the surface of a semiconductor substrate. The quantum well structures thus fabricated include Resonant Tunneling Transistors (RRTs) and one dimensional quantum wire devices, fabricated in conventional Metal Semiconductor Field Effect Transistors (MESFETs) or in High Electron Mobility Transistors (HEMTs). The RRT comprises a pair of implant barriers in the semiconductor substrate, whereby charge carriers are capable of tunneling through the implant barriers into the quantum well during the state of resonance. The one dimensional quantum wire device comprises a multiplicity of implant barriers disposed in the semiconductor substrate substantially parallel to the travelling direction of the charge carriers. The intersection of the implant barriers and the two dimensional gas (2DEG) inside the HEMT enclose truly one dimensional quantum wells which enable electrons to travel therethrough with high mobility.

Abstract: A semiconductor device according to the invention has a channel layer, which is sandwiched by a first and a second barrier layers, and an electron supply layer for supplying the channel layer with electrons through at least one of the barrier layers. The channel layer has a superlattice structure formed by periodically repeating, in the direction of electron movement, a first and a second semiconductor material regions, each of which has a different band gap from the other. With this superlattice structure, a plurality of mini-bands are formed within a potential well, which is formed by the first and second barrier layers. Impurity concentration of the electron supply layer is so controlled that electrons may move mainly within a mini-band in which effective mass of electrons is minimum among those mini-bands. Thus, a semiconductor device having a high electron mobility in the room temperature can be obtained without requiring high purification of crystal.

Abstract: Novel electron wave combining and/or branching devices and Aharonov-Bohm type quantum interference devices are proposed, which have no curved electron waveguide structures to form an electron branching or decoupling part or ring geometry. But instead the electron branching part or ring geometry is effectively constructed in a straight double quantum well structures, by the control of the shapes of the wave functions or of the subband energy levels relative to the Fermi level by electric fields.

Abstract: The invention provides a FET by forming a channel layer in a layer including "n" type impurity at high concentration, which is sandwiched by a first semiconductor layer and a second semiconductor layer lightly doped with impurity. Therefore even when electrons in the channel layer obtain high energy, the electrons in this arrangement rush out essentially to the second semiconductor layer excelling in its electron carrying characteristic, thus a travelling speed of the electrons in the channel layer is not lowered. Furthermore, because the channel layer is allowed to include impurity at high concentration, the current drive capability can be improved.

Abstract: A high speed transistor featured by a wide operation range and a high gain has a channel layer of a three-layer structure wherein undoped GaInAs layers are arranged above and beneath a GaAs layer. The GaAs layer includes at least one n-type delta doped layer. A cap layer, which is an undoped GaAs layer, and a buffer layer are formed above and beneath the channel layer on the substrate. A gate electrode and a source region, a drain region, a source electrode and a drain electrode which are self-aligned with respect to the gate electrode, also are formed.

Abstract: A method and apparatus is provided for propagating photoelectrons in a semiconductor material and for controlling the direction of photoelectrons produced in a semiconductor material. A selected region of the semiconductor material is irradiated with two beams of light that overlap in space and time. The two interfering light beams have a predetermined phase relationship and are harmonically related such that the frequency of one is approximately a multiple of two of the other. Each of the beams of light produce substantially a same number of photoelectrons in the semiconductor material. As the phase relationship between the two beams is varied, the direction of propagation of the photoelectrons produced, varies.

Abstract: A heterostructure includes a stained epitaxial layer of either silicon or germanium that is located overlying a silicon substrate, with a spatially graded Ge.sub.x Si.sub.1-x epitaxial layer overlain by a ungraded Ge.sub.x.sbsb.0 Si.sub.1-x.sbsb.0 intervening between the silicon substrate and the strained layer. Such a heterostructure can serve as a foundation for such devices as surface emitting LEDs, either n-channel or p-channel silicon-based MODFETs, and either n-channel or p-channel silicon-based MOSFETs.

Abstract: The invention provides a FET by forming a channel layer in layer including "n" type impurity at high concentration, which is sandwiched by a first semiconductor layer and a second semiconductor layer lightly doped with impurity. Therefore even when electrons in the channel layer obtain high energy, the electrons in this arrangement rush out essentially to the second semiconductor layer excelling in electron carrying characteristic, thus a travelling speed of the electrons in the channel layer is not lowered. Furthermore the channel layer being formed in layer and allowed to include impurity at high concentration, the current drive capability can be improved.

Abstract: An interband single-electron tunnel/transistor utilizes an interband single-electron tunneling phenomenon between a valence band and a conduction band through a p-n junction. The transistor includes the combination of microcapacities as fundamental constituent elements each formed by joining a p-type semiconductor material doped with an impurity in the degree of concentration with which a Fermi level overlaps a valence band and an n-type semiconductor material doped with an impurity in the degree of concentration with which the Fermi level overlaps a conduction band. The microcapacity includes a p-n junction having a junction area with which interband electron tunneling is inhibited due to Coulomb blockade.

Abstract: A quantum multifunction transistor including a plurality of conduction layers of semiconductor material with a tunnel barrier layer sandwiched therebetween. The conduction layers each being very thin to form discrete energy levels, and the material being chosen so that discrete energy levels therein are not aligned across the tunnel barrier layer in an equilibrium state. A gate coupled to a portion of one of the conduction layers for aligning, in response to a voltage applied thereto, discrete energy levels in the conduction layers across the tunnel barrier layer, whereby majority carrier current flows through the transistor. Application of a higher voltage to the gate results in minority carrier current flow through the transistor.

Abstract: A buffer layer, a first undoped layer, a first active layer and second undoped layer, a second active layer, a third undoped layer, a cap layer and contact layers are epitaxially grown on a semiconductor substrate in the stated order. A gate electrode is formed in a recess etched groove which formed in the center and reaches the cap layer through the contact layers. A drain electrode and a source electrode are formed on the contact layers and on both sides of the gate electrode.

Abstract: A quantum interference effect transistor comprising a semiconductor substrate, an n-type first semiconductor layer, a channel second semiconductor layer, an n-type third semiconductor layer, a gate electrode, a source electrode, a drain electrode, a source region and a drain region, said second semiconductor layer having an electron affinity larger than that of the first and third layers to generate a two dimensional electron gas channel, characterized in that the channel second layer between the source and drain regions consists of lead portions and a middle portion sandwiched with them, and in the middle portion the channel is divided into two channel passages without forming a separation layer in the second layer. The first, second and third layers form a quantum well structure.

Abstract: In a semiconductor device, a channel layer of an undoped semiconductor material passes carriers therethrough ballistically, a carrier injection part injects the carriers into the channel layer with directivity to form a quantum mechanical wave of carriers, a carrier collection part provided on the channel layer recovers the carriers; a carrier drainage part provided on the channel layer absorbs the carriers that have been scattered; a carrier control part controls the flow of the carriers from the carrier injection part to the carrier collection part; and a potential control layer, provided adjacent to the channel layer, controls the potential level of the channel layer such that the potential level is uniform throughout the channel layer.

Abstract: A quantum interference device in the form of a variable lateral confinement resonant tunneling transistor having a quantum waveguide structure including a primary current transmission path defined by a region between source and drain electrodes and where there is a resonance region therebetween in which quantum interference of tunneling wave functions establish a resonance tunneling condition that extends beyond the primary current path. Upon the application of a voltage across the drain and source electrodes, a tunneling current can be made to flow. A gate electrode formed on the quantum well structure remote from the primary current transmission path includes a variable depletion region thereunder or an electrostatic pinch off region, the size of which is a function of the magnitude of the bias voltage applied thereto.