With Multiple Channels Or Channel Segments Connected In Parallel, Or With Channel Much Wider Than Length Between Source And Drain (e.g., Power Jfet) Patents (Class 257/287)
  • Patent number: 10535741
    Abstract: A vertical JFET is provided. The JFET is mixed with lateral channel structure and p-GaN gate structure. The JFET has a N+ implant source region. In one embodiment, a JFET is provided with a drain metal deposited over a backside of an N substrate, an n-type drift layer epitaxial grown over a topside of the N substrate, a buried P-type block layer deposited over the n-type drift layer, an implanted N+ source region on side walls of the lateral channel layer, and an source metal attached to the top of the p-layer and attached to the implanted N+ source region at the side. In one embodiment, the JFET further comprises a gate layer, and wherein the gate layer is a dielectric gate structure that enables a fully enhanced channel. In another embodiment, the gate layer is a p-type GaN gate structure that enables a partially enhanced channel.
    Type: Grant
    Filed: January 29, 2018
    Date of Patent: January 14, 2020
    Inventor: Gangfeng Ye
  • Patent number: 10475935
    Abstract: There are provided a nanometer semiconductor device with a high-quality epitaxial layer and a method of manufacturing the same. According to an embodiment, the semiconductor device may include: a substrate; at least one nanowire spaced apart from the substrate; at least one semiconductor layer, each formed around a periphery of respective one of the at least one nanowire to at least partially surround the corresponding nanowire, wherein the semiconductor layer(s) formed around the respective nanowire(s) are separated from each other; an isolation layer formed on the substrate, exposing the at least one semiconductor layer; and a gate stack formed on the isolation layer and intersecting the at least one semiconductor layer, wherein the gate stack includes a gate dielectric layer at least partially surrounding a periphery of respective one of the at least one semiconductor layer and a gate conductor layer.
    Type: Grant
    Filed: December 7, 2016
    Date of Patent: November 12, 2019
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventor: Huilong Zhu
  • Patent number: 10439042
    Abstract: A semiconductor device and a fabrication method are provided. The method includes providing a substrate; forming a gate structure film on the substrate; forming a patterned mask structure on the gate structure film, where the patterned mask structure includes a first mask layer at least including a first material layer and a second mask layer on the first mask layer; forming a gate structure on the substrate by etching the gate structure film using the patterned mask structure as an etch mask, where the first material layer has an etching rate smaller than the second mask layer; and forming a spacer at least on a sidewall of the gate structure.
    Type: Grant
    Filed: December 1, 2017
    Date of Patent: October 8, 2019
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Jing Lin
  • Patent number: 10431628
    Abstract: According to one embodiment, a method includes forming a drain contact above a channel, each having a hollow circular cross-section thereof along a plane perpendicular to a film thickness direction, forming gate dielectric layers on sides of the drain contact and the channel, forming a source line positioned below the channel that is electrically coupled to a plurality of channels in a direction along the plane, forming gate layers on sides of the gate dielectric layers, where an inner gate layer fills a hole through a center of a center concentric circular cross-section of the gate dielectric layers along the plane, and where an outer gate layer surrounds an outside concentric circular cross-section of the gate dielectric layers along the plane, forming an electrode above the upper surface of the drain contact, and forming a fourth insulative layer on sides of the electrode along the plane.
    Type: Grant
    Filed: January 9, 2018
    Date of Patent: October 1, 2019
    Assignee: SPIN MEMORY, INC.
    Inventors: Kuk-Hwan Kim, Marcin Gajek, Dafna Beery, Amitay Levi
  • Patent number: 10411693
    Abstract: Thermo-migration induced stress in power devices can be mitigated by deactivating a subset of power device components (e.g., transistors, etc.) when the power device experiences a high stress condition. Deactivating the subset of power device components serves to bifurcate the active area of the power switching device into smaller active regions, which advantageously changes the temperature gradients in the active area/regions. In some embodiments, a control circuit dynamically deactivates different subsets of power device components to shift the thermo-migration induced stress points to different portions of the active region over the lifetime of the power switching device.
    Type: Grant
    Filed: October 28, 2014
    Date of Patent: September 10, 2019
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Cristian Mihai Boianceanu, Dan-Ionut Simon
  • Patent number: 10366981
    Abstract: A power semiconductor device includes a diode part disposed in a first region of a substrate, a junction field effect transistor (JFET) part disposed in a second region adjacent to the first region of the substrate, an anode terminal disposed on the first region of the substrate, and a cathode terminal disposed on the second region of the substrate. The diode part includes a p-type body region disposed inside the substrate and electrically connected with the anode terminal, an n-type well disposed on one side of the p-type body region and having a first impurity concentration, and a first n-type semiconductor region disposed below the p-type body region and having a second impurity concentration which is lower than the first impurity concentration.
    Type: Grant
    Filed: September 4, 2015
    Date of Patent: July 30, 2019
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Sun-hak Lee, Yong Zhong Hu, Hye-mi Kim
  • Patent number: 10361276
    Abstract: A trench N-channel field effect transistor has an active area and an edge area. A first pair of parallel-extending deep trenches extends parallel to a side edge of the die. A second pair of parallel-extending deep trenches extends perpendicularly to the side edge, toward the side edge, so that each trench of the second pair terminates into the inside deep trench of the first pair. An embedded field plate structure is embedded in these trenches. A plurality of floating P type well regions is disposed entirely between the second pair of deep trenches, between the active area and the inside deep trench of the first pair. Using this edge area structure, the breakdown voltage BVDSS of the overall device is increased because the breakdown voltage of the edge area is increased as compared to the same structure without the floating P type well regions.
    Type: Grant
    Filed: March 17, 2018
    Date of Patent: July 23, 2019
    Assignee: Littelfuse, Inc.
    Inventor: Kyoung Wook Seok
  • Patent number: 10229995
    Abstract: A method of fabricating a fin structure with tensile stress includes providing a structure divided into an N-type transistor region and a P-type transistor region. Next, two first trenches and two second trenches are formed in the substrate. The first trenches define a fin structure. The second trenches segment the first trenches and the fin. Later, a flowable chemical vapor deposition is performed to form a silicon oxide layer filling the first trenches and the second trenches. Then, a patterned mask is formed only within the N-type transistor region. The patterned mask only covers the silicon oxide layer in the second trenches. Subsequently, part of the silicon oxide layer is removed to make the exposed silicon oxide layer lower than the top surface of the fin structure by taking the patterned mask as a mask. Finally, the patterned mask is removed.
    Type: Grant
    Filed: August 4, 2017
    Date of Patent: March 12, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Kai-Lin Lee, Zhi-Cheng Lee, Wei-Jen Chen, Ting-Hsuan Kang, Ren-Yu He, Hung-Wen Huang, Chi-Hsiao Chen, Hao-Hsiang Yang, An-Shih Shih, Chuang-Han Hsieh
  • Patent number: 10224399
    Abstract: Transistor structures having channel regions comprising alternating layers of compressively and tensilely strained epitaxial materials are provided. The alternating epitaxial layers can form channel regions in single and mitigate transistor structures. In alternate embodiments, one of the two alternating layers is selectively etched away to form nanoribbons or nanowires of the remaining material. The resulting strained nanoribbons or nanowires form the channel regions of transistor structures. Also provided are computing devices comprising transistors comprising channel regions comprised of alternating compressively and tensilely strained epitaxial layers and computing devices comprising transistors comprising channel regions comprised of strained nanoribbons or nanowires.
    Type: Grant
    Filed: February 8, 2018
    Date of Patent: March 5, 2019
    Assignee: Intel Corporation
    Inventors: Van H. Le, Benjamin Chu-Kung, Harold Hal W. Kennel, Willy Rachmady, Ravi Pillarisetty, Jack T. Kavalieros
  • Patent number: 10186573
    Abstract: In one embodiment, a RESURF structure between a source and a drain in a lateral MOSFET is formed in a trench having a flat bottom surface and angled sidewalls toward the source. Alternating P and N-type layers are epitaxially grown in the trench, and their charges balanced to achieve a high breakdown voltage. In the area of the source, the ends of the P and N-layers angle upward to the surface under the lateral gate and contact the body region. Thus, for an N-channel MOSFET, a positive gate voltage above the threshold forms a channel between the source and the N-layers in the RESURF structure as well as creates an inversion of the ends of the P-layers near the surface for low on-resistance. In another embodiment, the RESURF structure is vertically corrugated by being formed around trenches, thus extending the length of the RESURF structure for a higher breakdown voltage.
    Type: Grant
    Filed: July 5, 2016
    Date of Patent: January 22, 2019
    Assignee: MaxPower Semiconductor, Inc.
    Inventors: Hamza Yilmaz, Mohamed N. Darwish, Richard A. Blanchard
  • Patent number: 10181508
    Abstract: Provided is a guard ring section to which a fine processing is easily applied. Provided is a semiconductor device comprising: a semiconductor substrate; an active region formed in the semiconductor substrate; and a guard ring section formed more outside than the active region in the semiconductor substrate, wherein the guard ring section includes: a guard ring formed in a circular pattern on an upper surface of the semiconductor substrate; an interlayer insulating film formed above the guard ring; a field plate formed in a circular pattern along the guard ring and above the interlayer insulating film; and a tungsten plug formed in a circular pattern along the guard ring and penetrating the interlayer insulating film to connect the guard ring and the field plate.
    Type: Grant
    Filed: March 1, 2017
    Date of Patent: January 15, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Hiroyuki Tanaka, Kota Ohi, Yuichi Onozawa, Yoshihiro Ikura, Kazutoshi Sugimura
  • Patent number: 10164083
    Abstract: A silicon carbide semiconductor device includes an ohmic electrode and a Schottky electrode that are in contact with the drain electrode respectively on the drain electrode and are next to each other; a first conductivity type first withstand voltage holding region in contact with the ohmic electrode on the ohmic electrode; a second conductivity type second withstand voltage holding region in contact with the Schottky electrode on the Schottky electrode and is next to the first withstand voltage holding region; a second conductivity type well region in contact onto the first and second withstand voltage holding regions; a first conductivity type source region selectively provided on a surface layer of the well region; and a gate electrode opposite to a channel region defined by the well region sandwiched between the source region and the first withstand voltage holding region, with a gate oxide film interposed therebetween.
    Type: Grant
    Filed: January 7, 2015
    Date of Patent: December 25, 2018
    Assignee: Mitsubishi Electric Corporation
    Inventor: Yuji Ebiike
  • Patent number: 10147785
    Abstract: In at least some embodiments, a semiconductor device structure comprises a first surface comprising a source and a gate; a second surface comprising a drain; a substrate of a first type, wherein the substrate is in contact with the drain; a first column in contact with the substrate and the first surface of the device, the first column comprising a dielectric material; and a mirroring axis, wherein a centerline of the first column is disposed along the mirroring axis, forming a first device side and a second device side, wherein the first device side mirrors the second device side.
    Type: Grant
    Filed: January 26, 2017
    Date of Patent: December 4, 2018
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Jaume Roig-Guitart, Filip Bauwens
  • Patent number: 10134792
    Abstract: Semiconductor devices are provided. The semiconductor devices may include a substrate, a device isolation pattern in the substrate to electrically isolate a first pixel and a second pixel from each other, a conductive pattern in the device isolation pattern, and a doping layer on a side surface of the device isolation pattern. The doping layer may have a conductivity type different from a conductivity type of the substrate.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: November 20, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Taeyon Lee, Gwideokryan Lee, Myungwon Lee
  • Patent number: 10096706
    Abstract: In some embodiments, the present disclosure relates to a vertical transistor device, and an associated method of formation. The transistor device has a source region over a substrate and a vertical channel bar over the source region. The vertical channel bar has a bottom surface with an elongated shape. A conductive gate region is separated from sidewalls of the vertical channel bar by a gate dielectric layer. The conductive gate region has a vertical leg and a horizontal leg protruding outward from a sidewall of the vertical leg. A dielectric layer vertically extends from a plane extending along an uppermost surface of the conductive gate region to a position surrounded by the conductive gate region. A drain contact is over the vertical channel bar.
    Type: Grant
    Filed: June 6, 2017
    Date of Patent: October 9, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Hao Wang, Jhon Jhy Liaw, Wai-Yi Lien, Jia-Chuan You, Yi-Hsun Chiu, Ching-Wei Tsai, Wei-Hao Wu
  • Patent number: 10050108
    Abstract: A semiconductor device may include a semiconductor layer, an insulation gate section, and a first conductivity-type semiconductor region; wherein the semiconductor layer may include a vertical drift region being of a second conductivity type and disposed at the one of main surfaces; a body region being of the first conductivity type, adjoining the vertical drift region, and disposed at the one of main surfaces; and a source region being of the second conductivity type, separated from the vertical drift region by the body region, and disposed at the one of main surfaces, wherein the insulation gate section is opposed to a portion of the body region which separates the vertical drift region and the source region; and the first conductivity-type semiconductor region is opposed to at least a part of a portion of the vertical drift region which is disposed at the one of main surfaces.
    Type: Grant
    Filed: August 8, 2017
    Date of Patent: August 14, 2018
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventor: Takashi Okawa
  • Patent number: 9917212
    Abstract: The present disclosure provides a transistor structure, including a self-aligned source-drain structure surrounded by an insulating structure and a gate of a second conductive type separated from the source and the drain by the insulating structure. The self-aligned source-drain structure includes a source and a drain of a first conductive type, a channel between the source and the drain, and a polysilicon contact over and aligned with the channel. A method for manufacturing the transistor structure is also provided in the present disclosure.
    Type: Grant
    Filed: September 6, 2016
    Date of Patent: March 13, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Fu-Yu Chu, Chih-Chang Cheng, Ruey-Hsin Liu
  • Patent number: 9853124
    Abstract: Method of making a transistor with semiconducting nanowires, including: making a semiconducting nanowire on a support, one portion of the nanowire being covered by a dummy gate, in which the dummy gate and the nanowire are surrounded by a dielectric layer, removing the dummy gate, forming a first space surrounded by first parts of the dielectric layer, making an ion implantation in a second part of the dielectric layer under said first portion, said first parts protecting third parts of the dielectric layer, etching said second part, forming a second space, making a gate in the spaces, and a dielectric portion on the gate and said first parts, making an ion implantation in fourth parts of the dielectric layer surrounding second portions of the nanowire, the dielectric portion protecting said first and third parts, etch said fourth parts.
    Type: Grant
    Filed: November 15, 2016
    Date of Patent: December 26, 2017
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Sylvain Barraud, Emmanuel Augendre, Sylvain Maitrejean, Nicolas Posseme
  • Patent number: 9735150
    Abstract: A semiconductor device includes an interlayer insulating film in which first contact holes and second contact holes are provided. Each of the second contact holes has a width narrower than a width of the corresponding first contact hole. A contact plug is located in the corresponding second contact hole. An upper electrode layer is arranged on an upper surface of the interlayer insulating film, upper surfaces of the contact plugs, and inner surfaces of the first contact holes. The protective insulating film covers an upper surface of the external field. An end portion extending along a direction intersecting with the plurality of trenches of the protective insulating film extends through a range located above the plurality of the second contact holes. A pillar region is in contact with the upper electrode layer in the first contact hole.
    Type: Grant
    Filed: June 6, 2016
    Date of Patent: August 15, 2017
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Shinya Iwasaki, Satoru Kameyama, Yuki Yakushigawa
  • Patent number: 9647120
    Abstract: A method for forming features of a vertical FET device, starting with a semiconductor substrate that includes fins and a horizontal surface. The fins also have a base, a top, and sidewalls. An etch process is performed to create bottom lateral recesses at the base of the fins. The method continues with growing a bottom source/drain region in the bottom recesses which forms PN junctions, and etching the fins to form top lateral recesses at the top of the fins. The method continues with growing a top source/drain region in the top recesses of the fins, therefore forming PN junctions.
    Type: Grant
    Filed: October 19, 2016
    Date of Patent: May 9, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Zhenxing Bi, Kangguo Cheng, Juntao Li, Peng Xu
  • Patent number: 9627539
    Abstract: A replacement channel and a method for forming the same in a semiconductor device are provided. A channel area is defined in a substrate which is a surface of a semiconductor wafer or a structure such as a fin formed over the wafer. Portions of the channel region are removed and are replaced with a replacement channel material formed by an epitaxial growth/deposition process to include a first dopant concentration level less than a first dopant concentration level. A subsequent doping operation or operations is then used to boost the average dopant concentration to a level greater than the first dopant concentration level. The replacement channel material is formed to include a gradient in which the upper portion of the replacement channel material has a greater dopant concentration than the lower portion of replacement channel material.
    Type: Grant
    Filed: January 15, 2015
    Date of Patent: April 18, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Lien Huang, Ming-Huan Tsai, Clement Hsingjen Wann
  • Patent number: 9620440
    Abstract: A multichip package includes a first semiconductor device mounted on a first leadframe, in which a primary heat producing surface of the first semiconductor device is oriented towards and in contact with a heat dispersing region of the first leadframe. A second semiconductor device is mounted on a second leadframe, in which a primary heat producing surface of the second semiconductor device is oriented towards and in contact with a heat dispersing region of the second leadframe. A surface of the heat dispersing region of the first leadframe is exposed on a first side of the multichip package, and a surface of the heat dispersing region of the second leadframe is exposed on a second side of the multichip package that is opposite from the first side.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: April 11, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Makoto Shibuya
  • Patent number: 9543395
    Abstract: In general, in a semiconductor active element such as a normally-off JFET based on SiC in which an impurity diffusion speed is significantly lower than in silicon, gate regions are formed through ion implantation into the side walls of trenches formed in source regions. However, to ensure the performance of the JFET, it is necessary to control the area between the gate regions thereof with high precision. Besides, there is such a problem that, since a heavily doped PN junction is formed by forming the gate regions in the source regions, an increase in junction current cannot be avoided. The present invention provides a normally-off power JFET and a manufacturing method thereof and forms the gate regions according to a multi-epitaxial method which repeats a process including epitaxial growth, ion implantation, and activation annealing a plurality of times.
    Type: Grant
    Filed: November 9, 2014
    Date of Patent: January 10, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Koichi Arai, Yasuaki Kagotoshi, Nobuo Machida, Natsuki Yokoyama, Haruka Shimizu
  • Patent number: 9530881
    Abstract: A semiconductor device includes a first-conductive-type first semiconductor layer having a first surface and an opposing second surface. A first-conductive-type second semiconductor layer is on the first surface, and a second-conductive-type third semiconductor layer is on the second semiconductor layer. A first-conductive-type fourth semiconductor layer is on the third semiconductor layer. A first electrode is provided on the second semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer via an insulating film. A second electrode is on the fourth semiconductor layer. A third electrode is separated from the second electrode in a second direction. The third electrode has a width in the second direction, and the width of the third electrode narrows from a first depth to a second depth. An angle of the side surface of the second semiconductor layer is greater than or equal to 90 degrees.
    Type: Grant
    Filed: March 1, 2015
    Date of Patent: December 27, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kouta Tomita, Kenji Maeyama
  • Patent number: 9385181
    Abstract: A semiconductor diode includes a semiconductor body having opposite first and second sides. A first and a second semiconductor region are consecutively arranged along a lateral direction at the second side. The first and second semiconductor regions are of opposite first and second conductivity types and are electrically coupled to an electrode at the second side. The semiconductor diode further includes a third semiconductor region of the second conductivity type buried in the semiconductor body at a distance from the second side. The second and third semiconductor regions are separated from each other.
    Type: Grant
    Filed: January 23, 2014
    Date of Patent: July 5, 2016
    Assignee: Infineon Technologies AG
    Inventors: Hans Peter Felsl, Elmar Falck, Manfred Pfaffenlehner, Frank Hille, Andreas Haertl, Holger Schulze, Daniel Schloegl
  • Patent number: 9318322
    Abstract: System and method for controlling the channel thickness and preventing variations due to formation of small features. An embodiment comprises a fin raised above the substrate and a capping layer is formed over the fin. The channel carriers are repelled from the heavily doped fin and confined within the capping layer. This forms a thin-channel that allows greater electrostatic control of the gate.
    Type: Grant
    Filed: November 13, 2014
    Date of Patent: April 19, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Zhiqiang Wu, Ken-Ichi Goto, Wen-Hsing Hsieh, Jon-Hsu Ho, Chih-Ching Wang, Ching-Fang Huang
  • Patent number: 9312295
    Abstract: A semiconductor device has a chip region including a back-side illumination type photoelectric conversion element, a mark-like appearance part, a pad electrode, and a coupling part. The mark-like appearance part includes an insulation film covering the entire side surface of a trench part formed in a semiconductor substrate. The pad electrode is arranged at a position overlapping the mark-like appearance part. The coupling part couples the pad electrode and mark-like appearance part. At least a part of the pad electrode on the other main surface side of the substrate is exposed through an opening reaching the pad electrode from the other main surface side of the substrate. The mark-like appearance part and coupling part are arranged to at least partially surround the outer circumference of the opening in plan view.
    Type: Grant
    Filed: February 27, 2015
    Date of Patent: April 12, 2016
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Takashi Terada, Shinya Hori
  • Patent number: 9281396
    Abstract: A trench structure which is capable of promoting extension of a depletion layer and hardly causes thermal stress is provided. A semiconductor device includes a semiconductor substrate. A plurality of loop trenches is formed on the surface of the semiconductor substrate. Each loop trench is configured to extend so as to surround a region smaller than the region where a plurality of gate trenches is formed. Each loop trench is separated from other loop trenches. A second insulating layer is located in each loop trench. P-type fourth regions are formed in the semiconductor substrate. Each fourth region is in contact with a bottom surface of corresponding one of the loop trenches and is configured to extend along the corresponding one of the loop trenches.
    Type: Grant
    Filed: October 2, 2014
    Date of Patent: March 8, 2016
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Hidefumi Takaya, Katsuhiro Kutsuki
  • Patent number: 9252208
    Abstract: Methods and structures for forming uniaxially-strained, nanoscale, semiconductor bars from a biaxially-strained semiconductor layer are described. A spatially-doubled mandrel process may be used to form a mask for patterning dense, narrow trenches through the biaxially-strained semiconductor layer. The resulting slicing of the biaxially-strained layer enhances carrier mobility and can increase device performance.
    Type: Grant
    Filed: July 31, 2014
    Date of Patent: February 2, 2016
    Assignees: STMicroelectronics, Inc., Commissariat A L'Energie Atomique Et Aux Energies Alternives, GlobalFoundries Inc.
    Inventors: Pierre Morin, Maud Vinet, Laurent Grenouillet, Ajey Poovannummoottil Jacob
  • Patent number: 9246347
    Abstract: A semiconductor die with integrated MOSFET and diode-connected enhancement mode JFET is disclosed. The MOSFET-JFET die includes common semiconductor substrate region (CSSR) of type-1 conductivity. A MOSFET device and a diode-connected enhancement mode JFET (DCE-JFET) device are located upon CSSR. The DCE-JFET device has the CSSR as its DCE-JFET drain. At least two DCE-JFET gate regions of type-2 conductivity located upon the DCE-JFET drain and laterally separated from each other with a DCE-JFET gate spacing. At least a DCE-JFET source of type-1 conductivity located upon the CSSR and between the DCE-JFET gates. A top DCE-JFET electrode, located atop and in contact with the DCE-JFET gate regions and DCE-JFET source regions. When properly configured, the DCE-JFET simultaneously exhibits a forward voltage Vf substantially lower than that of a PN junction diode while the reverse leakage current can be made comparable to that of a PN junction diode.
    Type: Grant
    Filed: December 10, 2013
    Date of Patent: January 26, 2016
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Sik Lui, Wei Wang
  • Patent number: 9165919
    Abstract: A semiconductor device that is equipped with an ESD protection element, which has a size increase thereof suppressed, does not require extra process, and can be formed without inducing deterioration of characteristics of the semiconductor device. This semiconductor device includes a semiconductor substrate, a circuit element, that includes a PN junction formed of a region, which is formed on the semiconductor substrate, and which has a conductivity type different from that of the substrate and a protection element for the circuit element. The protection element is a transistor formed of the region, another region having the conductivity type same as that of the region, and the semiconductor substrate. The emitter for the transistor and the semiconductor substrate are connected to each other.
    Type: Grant
    Filed: February 28, 2012
    Date of Patent: October 20, 2015
    Assignee: NEW JAPAN RADIO CO., LTD.
    Inventors: Hideaki Matsumoto, Jun Yamashita, Kenji Esashika, Takao Sugino
  • Patent number: 9129984
    Abstract: A 3D semiconductor device and a method of manufacturing the same are provided. The 3D semiconductor device includes a semiconductor substrate, an insulating layer formed on the semiconductor substrate, an active line including a source region and a drain region formed on the insulating layer, a gate electrode located on a portion of the active line, corresponding to a region between the source region and the drain region, and extending to a direction substantially perpendicular to the active line, and a line-shaped common source node formed to be electrically coupled to the source region and extending substantially in parallel to the gate electrode in a space between gate electrodes.
    Type: Grant
    Filed: November 7, 2013
    Date of Patent: September 8, 2015
    Assignee: SK Hynix Inc.
    Inventor: Suk Ki Kim
  • Patent number: 9093508
    Abstract: A method is provided for fabricating a nano field-effect vacuum tube. The method includes providing a substrate having an insulating layer and a sacrificial layer; and forming a sacrificial line, a source sacrificial layer and a drain sacrificial layer. The method also includes forming a trench in the insulating layer; and forming a dielectric layer on the surface of the sacrificial line. Further, the method includes forming a metal layer on the dielectric layer to fill up the trench, cover the sacrificial line and expose the source sacrificial layer and the drain sacrificial layer; and removing the source sacrificial layer and the drain sacrificial layer. Further, the method also includes removing the sacrificial line to form a through channel; forming an isolation layer on the metal layer; and forming a source region and a drain region on the insulating layer at both ends of the metal layer.
    Type: Grant
    Filed: April 10, 2015
    Date of Patent: July 28, 2015
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventor: Deyuan Xiao
  • Patent number: 9024365
    Abstract: A high voltage junction field effect transistor and a manufacturing method thereof are provided. The high voltage junction field effect transistor includes a base, a drain, a source and a P type top layer. The drain and the source are disposed above the base. A channel is formed between the source and the drain. The P type top layer is disposed above the channel.
    Type: Grant
    Filed: September 10, 2012
    Date of Patent: May 5, 2015
    Assignee: Macronix International Co., Ltd.
    Inventors: Li-Fan Chen, Wing-Chor Chan, Jeng Gong
  • Publication number: 20150109048
    Abstract: A transistor includes a channel forming layer on a substrate, a gate on the channel forming layer and including an electrochemically indifferent metal, a solid electrolyte layer between the channel forming layer and the gate, the solid electrolyte layer is formed as a stack structure with the gate on the channel forming layer, an active metal layer including an electrochemically active metal capable of enabling channel switching by using an oxidation-reduction reaction of the electrochemically active metal so that the active metal layer forms a metal channel in a channel region between the channel forming layer and the solid electrolyte layer, and a source and a drain electrically connected to the active metal layer.
    Type: Application
    Filed: October 23, 2014
    Publication date: April 23, 2015
    Inventors: Woo-young YANG, Ki-hong KIM, Sang-jun CHOI, Young-eal KIM, Seong-yong PARK
  • Patent number: 8994125
    Abstract: A semiconductor device includes, on a semiconductor substrate, a gate insulating film, a pMIS metal material or an nMIS metal material, a gate electrode material, and a gate sidewall metal layer.
    Type: Grant
    Filed: August 20, 2012
    Date of Patent: March 31, 2015
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventor: Kenshi Kanegae
  • Patent number: 8987817
    Abstract: A semiconductor device of the present invention includes: a semiconductor substrate of a first conductive type; an epitaxial layer of the first conductive type formed on the semiconductor substrate and having a protrusion formed on a surface thereof; a well region of a second conductive type formed on the surface of the epitaxial layer at each side of the protrusion; a source region of the first conductive type selectively formed in a surface of the well region; a gate insulating film formed so as to cover at least the protrusion and the surface of the well region; and a gate electrode formed on a part of the gate insulating film corresponding to the protrusion. The gate insulating film is thicker in a region thereof corresponding to an upper surface of the protrusion than the other regions thereof.
    Type: Grant
    Filed: August 3, 2011
    Date of Patent: March 24, 2015
    Assignee: Mitsubishi Electric Corporation
    Inventor: Yoichiro Tarui
  • Patent number: 8981490
    Abstract: A method of fabricating a CMOS integrated circuit (IC) includes implanting a first n-type dopant at a first masking level that exposes a p-region of a substrate surface having a first gate stack thereon to form NLDD regions for forming n-source/drain extension regions for at least a portion of a plurality of n-channel MOS (NMOS) transistors on the IC. A p-type dopant is implanted at a second masking level that exposes an n-region in the substrate surface having a second gate stack thereon to form PLDD regions for at least a portion of a plurality of p-channel MOS (PMOS) transistors on the IC. A second n-type dopant is retrograde implanted including through the first gate stack to form a deep nwell (DNwell) for the portion of NMOS transistors. A depth of the DNwell is shallower below the first gate stack as compared to under the NLDD regions.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: March 17, 2015
    Assignee: Texas Instruments Incorporated
    Inventor: Mahalingam Nandakumar
  • Patent number: 8975712
    Abstract: One method disclosed herein includes forming first and second transistor devices in and above adjacent active regions that are separated by an isolation region, wherein the transistors comprise a source/drain region and a shared gate structure, forming a continuous conductive line that spans across the isolation region and contacts the source/drain regions of the transistors and etching the continuous conductive line to form separated first and second unitary conductive source/drain contact structures that contact the source/drain regions of the first and second transistors, respectively. A device disclosed herein includes a gate structure, source/drain regions, first and second unitary conductive source/drain contact structures, each of which contacts one of the source/drain regions, and first and second conductive vias that contact the first and second unitary conductive source/drain contact structures, respectively.
    Type: Grant
    Filed: May 14, 2013
    Date of Patent: March 10, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Mahbub Rashed, Juhan Kim, Yunfei Deng, Suresh Venkatesan
  • Patent number: 8969929
    Abstract: A general insulated gate power semiconductor active element with many gate electrodes arranged in parallel has a laminated structure including a barrier metal film and a thick aluminum electrode film formed over the gate electrodes via an interlayer insulating film. When the aluminum electrode film is embedded in between the gate electrodes in parallel, voids may be generated with the electrodes. Such voids allow the etchant to penetrate in wet etching, which may promote the etching up to a part of the electrode film in an active cell region which is to be left. Thus, an insulated gate power semiconductor device is provided to include gate electrodes protruding outward from the inside of the active cell region, and a gate electrode coupling portion for coupling the gate electrodes outside the active cell region. The gate electrode coupling portion is covered with a metal electrode covering the active cell region.
    Type: Grant
    Filed: September 21, 2011
    Date of Patent: March 3, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Koichiro Sakanishi, Tsuyoshi Kachi, Koji Fujishima
  • Patent number: 8928044
    Abstract: A this film transistor is provided. The thin film transistor includes a semiconductor layer including a source region, a drain region, and a channel region, wherein the channel region is provided between the source region and the drain region; and a gate electrode overlapping with the channel region, wherein the channel region includes at least a portion of a channel width that is configured to at least one of continuously decrease and continuously increase in a lengthwise direction.
    Type: Grant
    Filed: January 5, 2011
    Date of Patent: January 6, 2015
    Assignee: Japan Display West Inc.
    Inventors: Yoshitaka Ozeki, Yasuhito Kuwahara, Shigetaka Toriyama, Hiroyuki Ikeda
  • Patent number: 8928045
    Abstract: A channel region having a first conductivity type is disposed in a surface portion of a semiconductor substrate. A gate region having a second conductivity type is disposed in a surface portion of the channel region. A first semiconductor region having the second conductivity type is disposed under the channel region. Source/drain regions having the first conductivity type are disposed in parts of the surface portion of the channel region on both sides of the gate region in a channel length direction. Second semiconductor regions each having a high impurity concentration and the second conductivity type are disposed in parts of the semiconductor substrate on both sides of the channel region in a channel width direction.
    Type: Grant
    Filed: November 30, 2012
    Date of Patent: January 6, 2015
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Masato Oooka, Osamu Matsui, Shuji Tsujino
  • Patent number: 8928074
    Abstract: Semiconductor devices and methods of making the devices are described. The devices can be junction field-effect transistors (JFETs) or diodes such as junction barrier Schottky (JBS) diodes or PiN diodes. The devices have graded p-type semiconductor layers and/or regions formed by epitaxial growth. The methods do not require ion implantation. The devices can be made from a wide-bandgap semiconductor material such as silicon carbide (SiC) and can be used in high temperature and high power applications.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: January 6, 2015
    Assignee: Power Integrations, Inc.
    Inventors: Lin Cheng, Michael Mazzola
  • Patent number: 8916913
    Abstract: The present disclosure discloses a high voltage semiconductor device and the associated methods of manufacturing. In one embodiment, the high voltage semiconductor device comprises: an epitaxial layer, a first low voltage well formed in the epitaxial layer; a second low voltage well formed in the epitaxial layer; a high voltage well formed in the epitaxial layer, wherein the second low voltage well is surrounded by the high voltage well; a first highly doping region formed in the first low voltage well; a second highly doping region and a third highly doping region formed in the second low voltage well, wherein the third highly doping region is adjacent to the second highly doping region; a field oxide formed in the epitaxial layer as a shallow-trench isolation structure; and a gate region formed on the epitaxial layer.
    Type: Grant
    Filed: July 13, 2012
    Date of Patent: December 23, 2014
    Assignee: Monolithic Power Systems, Inc.
    Inventors: Ji-Hyoung Yoo, Lei Zhang
  • Patent number: 8896021
    Abstract: An integrated circuit device includes a semiconductor substrate and a first transistor and a second transistor constructed in the semiconductor substrate. The first transistor has a first operating voltage higher than a second operating voltage of a second transistor. The first transistor includes a first drain structure, a first source structure, an isolation structure and a first gate structure. The first source structure includes a high voltage first-polarity well region, a first-polarity body region, a heavily doped first-polarity region, a second-polarity grade region and a heavily doped second-polarity region. The heavily doped second-polarity region is surrounded by the second-polarity grade region. The second-polarity grade region is surrounded by the first-polarity body region. The second transistor includes a second drain structure, a second source structure, a second gate structure and a first-polarity drift region.
    Type: Grant
    Filed: September 14, 2011
    Date of Patent: November 25, 2014
    Assignee: United Microelectronics Corporation
    Inventors: Chung-I Huang, Pao-An Chang, Ming-Tsung Lee
  • Patent number: 8890207
    Abstract: System and method for controlling the channel thickness and preventing variations due to formation of small features. An embodiment comprises a fin raised above the substrate and a capping layer is formed over the fin. The channel carriers are repelled from the heavily doped fin and confined within the capping layer. This forms a thin-channel that allows greater electrostatic control of the gate.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: November 18, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Zhiqiang Wu, Ken-Ichi Goto, Wen-Hsing Hsieh, Jon-Hsu Ho, Chih-Ching Wang, Ching-Fang Huang
  • Patent number: 8853691
    Abstract: A transistor and a manufacturing method thereof are provided. The transistor includes a first gate, a second gate disposed on one side of the first gate, a first semiconductor layer, a second semiconductor layer, an oxide layer, a first insulation layer, a second insulation layer, a source, and a drain. The first semiconductor layer is disposed between the first and second gates; the second semiconductor layer is disposed between the first semiconductor layer and the second gate. The oxide layer is disposed between the first semiconductor layer and the second semiconductor layer. The first insulation layer is disposed between the first gate and the first semiconductor layer; the second insulation layer is disposed between the second gate and the second semiconductor layer. The source and the drain are disposed between the first insulation layer and the second insulation layer and respectively disposed on opposite sides of the oxide layer.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: October 7, 2014
    Assignee: E Ink Holdings Inc.
    Inventors: Chih-Hsiang Yang, Ted-Hong Shinn, Wei-Tsung Chen, Hsing-Yi Wu
  • Patent number: 8847295
    Abstract: A structure and method of forming a semiconductor device with a fin is provided. In an embodiment a hard mask is utilized to pattern a gate electrode layer and is then removed. After the hard mask has been removed, the gate electrode layer may be separated into individual gate electrodes.
    Type: Grant
    Filed: August 1, 2013
    Date of Patent: September 30, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Feng Shieh, Chih-Hao Yu, Chang-Yun Chang
  • Patent number: 8841667
    Abstract: A transistor structure disposed on a substrate includes a gate electrode, a gate insulating layer overlapping the gate electrode, a channel layer overlapping the gate electrode, and a plurality of first electrodes and a plurality of second electrodes overlapping the gate electrode. The gate insulating layer is disposed between the channel layer and the gate electrode. Besides, the gate insulating layer is located among the first electrodes, the second electrodes, and the gate electrode. The first electrodes and the second electrodes are alternately arranged along a first direction. Each of the first electrodes has a first width along the first direction. Each of the second electrodes has a second width along the first direction. A ratio of the first width to the second width ranges from 2 to 20. A driving circuit structure having the transistor structure is also provided.
    Type: Grant
    Filed: August 3, 2012
    Date of Patent: September 23, 2014
    Assignee: Au Optronics Corporation
    Inventors: Jyu-Yu Chang, Chun-Wei Lai, Po-Yuan Shen, Wen-Jung Lee, Chih-Wei Tai
  • Patent number: 8823095
    Abstract: It is the purpose of the invention to provide a MOS transistor (20) which guarantees a voltage as high as possible, has a required area as small as possible and which enables the integration into integrated smart power circuits. It results there from as an object of the invention to form the edge structure of the transistors such that it certainly fulfils the requirements on high breakthrough voltages, a good isolation to the surrounding region and requires a minimum of surface on the silicon disc anyway. This is achieved with an elongated MOS power transistor having drain (30) and source (28) for high rated voltages above 100V, wherein the transistor comprises an isolating trench (22) in the edge area for preventing an early electrical breakthrough below the rated voltage. The trench is lined with an isolating material (70, 72), wherein the isolating trench terminates the circuit component.
    Type: Grant
    Filed: June 14, 2007
    Date of Patent: September 2, 2014
    Assignee: X-Fab Semiconductor Foundries AG
    Inventor: Ralf Lerner