With Multiple Channels Or Channel Segments Connected In Parallel, Or With Channel Much Wider Than Length Between Source And Drain (e.g., Power Jfet) Patents (Class 257/287)
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Patent number: 7498617Abstract: A III-nitride power device that includes a Schottky electrode integrated with a power switch. The combination is used in power supply circuits such as a boost converter circuit.Type: GrantFiled: February 2, 2006Date of Patent: March 3, 2009Assignee: International Rectifier CorporationInventor: Daniel M. Kinzer
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Patent number: 7449762Abstract: A Lateral Epitaxial Gallium Nitride metal insulator semiconductor field effect transistor (LEGaN-MISFET) is described that includes a body region including at least one layer formed of Gallium Nitride having a first conductivity type formed on the substrate; a resurf layer of Gallium Nitride having a second conductivity type formed the body region; a source region in contact with the resurf layer; a drain region, in contact with the resurf layer and spaced apart from the source region; a gate metal insulator semiconductor (MIS) structure in contact with the body region including a gate contact; and a MIS conductive inversion channel along the surface of the body region in contact with the gate MIS structure. A lateral current conduction path may be formed in the resurf layer between the source region and the drain region connected by the MIS channel, where the lateral current conduction path is controlled by an applied gate source bias.Type: GrantFiled: April 7, 2006Date of Patent: November 11, 2008Assignee: Wide Bandgap LLCInventor: Ranbir Singh
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Publication number: 20080272409Abstract: A junction field effect transistor comprises a semiconductor substrate, a source region formed in the substrate, a drain region formed in the substrate and spaced apart from the source region, and a gate region formed in the substrate. The transistor further comprises a first channel region formed in the substrate and spaced apart from the gate region, and a second channel region formed in the substrate and between the first channel region and the gate region. The second channel region has a higher concentration of doped impurities than the first channel region.Type: ApplicationFiled: May 3, 2007Publication date: November 6, 2008Inventors: Sachin R. Sonkusale, Weimin Zhang, Ashok K. Kapoor
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Patent number: 7442971Abstract: By providing a self-biasing semiconductor switch, an SRAM cell having a reduced number of individual active components may be realized. In particular embodiments, the self-biasing semiconductor device may be provided in the form of a double channel field effect transistor that allows the formation of an SRAM cell with less than six transistor elements and, in preferred embodiments, with as few as two individual transistor elements.Type: GrantFiled: January 28, 2005Date of Patent: October 28, 2008Assignee: Advanced Micro Devices, Inc.Inventors: Frank Wirbeleit, Manfred Horstmann, Christian Hobert
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Patent number: 7427788Abstract: A field effect transistor (FET) includes spaced apart source and drain regions disposed on a substrate and at least one pair of elongate channel regions disposed on the substrate and extending in parallel between the source and drain regions. A gate insulating region surrounds the at least one pair of elongate channel regions, and a gate electrode surrounds the gate insulating region and the at least one pair of elongate channel regions. Support patterns may be interposed between the semiconductor substrate and the source and drain regions. The elongate channel regions may have sufficiently small cross-section to enable complete depletion thereof. For example, a width and a thickness of the elongate channel regions may be in a range from about 10 nanometers to about 20 nanometers. The elongate channel regions may have rounded cross-sections, e.g., each of the elongate channel regions may have an elliptical cross-section.Type: GrantFiled: October 26, 2005Date of Patent: September 23, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Ming Li, Sung-min Kim
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Publication number: 20080217664Abstract: The disclosure herein pertains to fashioning a low noise junction field effect transistor (JFET) where transistor gate materials are utilized in forming and electrically isolating active areas of a the JFET. More particularly, active regions are self aligned with patterned gate electrode material and sidewall spacers which facilitate desirably locating the active regions in a semiconductor substrate. This mitigates the need for additional materials in the substrate to isolate the active regions from one another, where such additional materials can introduce noise into the JFET. This also allows a layer of gate dielectric material to remain over the surface of the substrate, where the layer of gate dielectric material provides a substantially uniform interface at the surface of the substrate that facilitates uninhibited current flow between the active regions, and thus promotes desired device operation.Type: ApplicationFiled: March 8, 2007Publication date: September 11, 2008Inventors: Xiaoju Wu, Fan-Chi Frank Hou, Pinghai Hao
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Patent number: 7391087Abstract: An MOS device comprising a gate dielectric formed on a first conductivity type region. A gate electrode formed on the gate dielectric. A pair of sidewall spacers are formed along laterally opposite sidewalls of the gate electrode. A pair of deposited silicon or silicon alloy source/drain regions are formed in the first conductivity region and on opposite sides of a gate electrode wherein the silicon or silicon alloy source/drain regions extend beneath the gate electrode and to define a channel region beneath the gate electrode in the first conductivity type region wherein the channel region directly beneath the gate electrode is larger than the channel region deeper into said first conductivity type region.Type: GrantFiled: December 30, 1999Date of Patent: June 24, 2008Assignee: Intel CorporationInventors: Anand Murthy, Robert S. Chau, Patrick Morrow
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Publication number: 20080142853Abstract: A method of forming an electronic device includes, forming a first channel coupled to a first current electrode and a second current electrode and forming a second channel coupled to the first current electrode and the second current electrode. The method also includes the second channel being substantially parallel to the first channel within a first plane, wherein the first plane is parallel to a major surface of a substrate over which the first channel lies. A gate electrode is formed surrounding the first channel and the second channel in a second plane, wherein the second plane is perpendicular to the major surface of the substrate. The resulting semiconductor device has a plurality of locations with a plurality of channels at each location. At small dimensions the channels form quantum wires connecting the source and drain.Type: ApplicationFiled: February 26, 2008Publication date: June 19, 2008Applicant: FREESCALE SEMICONDUCTOR, INC.Inventor: Marius Orlowski
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Patent number: 7385273Abstract: A power semiconductor device that includes a plurality of gate structure each having a gate insulation of a first thickness, and a termination region, the termination including a field insulation body surrounding the active region and having a recess that includes a bottom insulation thicker than the first thickness.Type: GrantFiled: June 9, 2006Date of Patent: June 10, 2008Assignee: International Rectifier CorporationInventors: Hugo R Burke, Simon Green
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Publication number: 20080128673Abstract: A transistor for a phase change memory device includes a semiconductor substrate in which active regions are delimited by an isolation structure. A groove is defined on a surface of a gate forming area of each active region. Portions of the isolation structure, which are adjacent to the gate forming area of the active region, are recessed to expose side faces of the gate forming area of the active region. A gate is formed on the gate forming area of the active region over the gate forming area grooves and exposed side faces thereof as well as the recessed portions of the isolation structure. Junction areas are then formed in the active region on both sides of the gate to complete the transistor of a phase change memory device.Type: ApplicationFiled: September 14, 2007Publication date: June 5, 2008Inventors: Heon Yong CHANG, Suk Kyoung HONG, Hae Chan PARK, Nam Kyun PARK
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Publication number: 20080067561Abstract: A quantum interference transistor comprising an source region for emitting electron waves into a vacuum, a drain region for collecting the electron waves, a repeating nanostructure in a region between the source and drain regions for introducing a constant phase shift between a plurality of electron waves, and a gate for controlling the phase shift introduced by the nanostructure; wherein the repeating nanostructure is characterized by having sharply defined geometric patterns or indents of a dimension that creates de Broglie wave interference.Type: ApplicationFiled: September 18, 2007Publication date: March 20, 2008Inventors: Amiran Bibilashvili, Avto Tavkhelidze
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Patent number: 7329913Abstract: A semiconductor device comprising a semiconductor body having a top surface and a first and second laterally opposite sidewalls as formed on an insulating substrate. A gate dielectric is formed on the top surface of the semiconductor body and on the first and second laterally opposite sidewalls of the semiconductor body. A gate electrode is then formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the first and second laterally opposite sidewalls of the semiconductor body. The gate electrode comprises a metal film formed directly adjacent to the gate dielectric layer. A pair of source and drain regions are uniformed in the semiconductor body on opposite sides of the gate electrode.Type: GrantFiled: December 27, 2004Date of Patent: February 12, 2008Assignee: Intel CorporationInventors: Justin K. Brask, Brian S. Doyle, Mark L. Doczy, Robert S. Chau
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Patent number: 7297580Abstract: The present invention provides a unit cell of a metal-semiconductor field-effect transistor (MESFET). The unit cell of the MESFET includes a source, a drain and a gate. The gate is disposed between the source and the drain and on an n-type conductivity channel layer. A p-type conductivity region is provided beneath the source and has an end that extends towards the drain. The p-type conductivity region is spaced apart from the n-type conductivity channel region and is electrically coupled to the source.Type: GrantFiled: June 1, 2005Date of Patent: November 20, 2007Assignee: Cree, Inc.Inventor: Saptharishi Sriram
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Patent number: 7288803Abstract: A III-nitride power semiconductor device that includes a current sense electrode.Type: GrantFiled: September 30, 2005Date of Patent: October 30, 2007Assignee: International Rectifier CorporationInventors: Robert Beach, Paul Bridger, Daniel M. Kinzer
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Patent number: 7276723Abstract: Alternate layers of wide band gap and narrow band gaps of different kinds of semiconductors are used to form multiple channels of a FET. The channels are doped or formed as 2-DEG/2-DHG in narrow band semiconductor by charge supply layer in the wide band gap semiconductor. The different kinds of semiconductors form heterojunctions to confine the electrons/holes in separate thin spikes layers. A number of spikes (3-10 nm thick) of different doped or 2-DEG/2-DHG concentrations in various channels can result in overall electron concentration gradient such as a 1/x3 electron/hole concentrations profile. Such an electron/hole concentration gradient can result in a linear variation of drain current with voltage to obtain a wide dynamic range.Type: GrantFiled: August 18, 2005Date of Patent: October 2, 2007Assignee: Epitaxial TechnologiesInventors: Ayub Mohammed Fathimulla, Harry Stephen Hier, Olaleye Adetord Aina
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Patent number: 7274051Abstract: In a field effect transistor (FET), and a method of fabricating the same, the FET includes a semiconductor substrate, source and drain regions formed on the semiconductor substrate, a plurality of wire channels electrically connecting the source and drain regions, the plurality of wire channels being arranged in two columns and at least two rows, and a gate dielectric layer surrounding each of the plurality of wire channels and a gate electrode surrounding the gate dielectric layer and each of the plurality of wire channels.Type: GrantFiled: March 9, 2005Date of Patent: September 25, 2007Assignee: Samsung Electronics Co., Ltd.Inventors: Sungmin Kim, Ming Li, Eungjung Yoon
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Patent number: 7268394Abstract: Junction field effect transistors (JFETs) can be fabricated with an epitaxial layer that forms a sufficiently thick channel region to enable the JFET for use in high voltage applications (e.g., having a breakdown voltage greater than about 20V). Additionally or alternatively, threshold voltage (VT) implants can be introduced at one or more of the gate, source and drain regions to improve noise performance of the JFET. Additionally, fabrication of such a JFET can be facilitated forming the entire JFET structure concurrently with a CMOS fabrication process and/or with a BiCMOS fabrication process.Type: GrantFiled: January 18, 2005Date of Patent: September 11, 2007Assignee: Texas Instruments IncorporatedInventors: Pinghai Hao, Fan-Chi Hou, Imran Khan
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Patent number: 7265399Abstract: High power transistors are provided. The transistors include a source region, a drain region and a gate contact. The gate contact is positioned between the source region and the drain region. First and second ohmic contacts are provided on the source and drain regions, respectively. The first and second ohmic contacts respectively define a source contact and a drain contact. The source contact and the drain contact have respective first and second widths. The first and second widths are different. Related methods of fabricating transistors are also provided.Type: GrantFiled: October 29, 2004Date of Patent: September 4, 2007Assignee: Cree, Inc.Inventors: Saptharishi Sriram, Jason Henning
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Patent number: 7221010Abstract: Silicon carbide metal-oxide semiconductor field effect transistors (MOSFETs) may include an n-type silicon carbide drift layer, a first p-type silicon carbide region adjacent the drift layer and having a first n-type silicon carbide region therein, an oxide layer on the drift layer, and an n-type silicon carbide limiting region disposed between the drift layer and a portion of the first p-type region. The limiting region may have a carrier concentration that is greater than the carrier concentration of the drift layer. Methods of fabricating silicon carbide MOSFET devices are also provided.Type: GrantFiled: October 30, 2003Date of Patent: May 22, 2007Assignee: Cree, Inc.Inventor: Sei-Hyung Ryu
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Patent number: 7211864Abstract: A fully depleted castellated-gate MOSFET device is disclosed along with a method of making the same. The device has robust I/O applications, and includes a semiconductor substrate body having an upper portion with an upper end surface and a lower portion with a lower end surface. A source region, a drain region, and a channel-forming region between the source and drain regions are all formed in the semiconductor substrate body. trench isolation insulator islands surround the source and drain regions as well as the channel-forming region. The channel-forming region is made up of a plurality of thin, spaced, vertically-orientated conductive channel elements that span longitudinally along the device between the source and drain regions. A gate structure is also provided in the form of a plurality of spaced, castellated gate elements interposed between the channel elements.Type: GrantFiled: September 13, 2004Date of Patent: May 1, 2007Inventor: John J. Seliskar
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Patent number: 7202517Abstract: A multiple gate semiconductor device. The device includes at least two gates. The dopant distribution in the semiconductor body of the device varies from a low value near the surface of the body towards a higher value inside the body of the device.Type: GrantFiled: July 16, 2004Date of Patent: April 10, 2007Assignee: Interuniversitair Microelektronica Centrum (IMEC vzw)Inventors: Abhisek Dixit, Kristin De Meyer
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Patent number: 7187022Abstract: In a semiconductor device having a multi-bridge-channel, and a method for fabricating the same, the device includes first and second semiconductor posts protruding from a surface of a semiconductor substrate and having a source and a drain region, respectively, in upper side portions thereof, channel semiconductor layers connecting upper side portions of the first and second semiconductor posts, a gate insulation layer on the channel semiconductor layers and the semiconductor substrate, the gate insulation layer surrounding at least a portion of the channel semiconductor layers, a gate electrode layer on the gate insulation layer to enclose at least a portion of a region between the channel semiconductor layers, and junction auxiliary layers formed between the channel semiconductor layers, the junction auxiliary layers contacting the gate electrode layer and upper side portions of the first and second semiconductor posts, and having a same width as the channel semiconductor layers.Type: GrantFiled: November 23, 2005Date of Patent: March 6, 2007Assignee: Samsung Electronics Co., Ltd.Inventors: Eun-jung Yun, Sung-min Kim, Sung-young Lee
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Patent number: 7166894Abstract: The present invention relates to a power junction device including a substrate of the SiCOI type with a layer of silicon carbide (16) insulated from a solid carrier (12) by a buried layer of insulant (14), and including at least one Schottky contact between a first metal layer (40) and the surface layer of silicon carbide (16), the first metal layer (30) constituting an anode.Type: GrantFiled: March 12, 2003Date of Patent: January 23, 2007Assignee: Commissariat a l'Energie AtomiqueInventors: François Templier, Thierry Billon, Nicolas Daval
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Patent number: 7141838Abstract: An integrated circuit system includes providing a semiconductor substrate and forming buried word lines in the semiconductor substrate with the buried word lines including vertical charge-trapping dielectric layers. The system further includes forming bit lines further comprising forming in-substrate portions in the semiconductor substrate, and forming above-substrate portions over the semiconductor substrate.Type: GrantFiled: January 27, 2005Date of Patent: November 28, 2006Assignee: Spansion LLCInventor: Michael Brennan
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Patent number: 7141837Abstract: A MOS transistor formed in a silicon substrate comprising an active area surrounded with an insulating wall, a first conductive strip covering a central strip of the active area, one or several second conductive strips placed in the active area right above the first strip, and conductive regions placed in two recesses of the insulating wall and placed against the ends of the first and second strips, the silicon surfaces opposite to the conductive strips and regions being covered with an insulator forming a gate oxide.Type: GrantFiled: April 2, 2004Date of Patent: November 28, 2006Assignee: STMicroelectronics S.A.Inventors: Philippe Coronel, Yves Morand, Thomas Skotnicki, Robin Cerutti
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Patent number: 7135747Abstract: A high power, high frequency semiconductor device has a plurality of unit cells connected in parallel. The unit cells each having a controlling electrode and first and second controlled electrodes. A thermal spacer divides at least one of the unit cells into a first active portion and a second active portion, spaced apart from the first potion by the thermal spacer. The controlling electrode and the first and second controlled electrodes of the unit cell cross over the first thermal spacer.Type: GrantFiled: February 25, 2004Date of Patent: November 14, 2006Assignee: Cree, Inc.Inventors: Scott Thomas Allen, James William Milligan
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Patent number: 7126173Abstract: An electronic power device of improved structure is fabricated with MOS technology to have a gate finger region and corresponding source regions on either sides of the gate region. This device has a first-level metal layer arranged to independently contact the gate region and source regions, and has a protective passivation layer arranged to cover the gate region. Advantageously, a wettable metal layer, deposited onto the passivation layer and the first-level metal layer, overlies said source regions. In this way, the additional wettable metal layer is made to act as a second-level metal.Type: GrantFiled: October 30, 2002Date of Patent: October 24, 2006Assignee: STMicroelectronics, S.r.l.Inventors: Ferruccio Frisina, Antonio Pinto, Angelo Magri
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Patent number: 7112832Abstract: A transistor (10) overlies a substrate (12) and has a plurality of overlying channels (72, 74, 76) that are formed in a stacked arrangement. A continuous gate (60) material surrounds each of the channels. Each of the channels is coupled to source and drain electrodes (S/D) to provide increased channel surface area in a same area that a single channel structure is conventionally implemented. A vertical channel dimension between two regions of the gate (60) are controlled by a growth process as opposed to lithographical or spacer formation techniques. The gate is adjacent all sides of the multiple overlying channels. Each channel is formed by growth from a common seed layer and the source and drain electrodes and the channels are formed of a substantially homogenous crystal lattice.Type: GrantFiled: March 29, 2005Date of Patent: September 26, 2006Assignee: Freescale Semiconductor, Inc.Inventors: Marius K. Orlowski, Leo Mathew
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Patent number: 7109516Abstract: The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication.Type: GrantFiled: August 25, 2005Date of Patent: September 19, 2006Assignee: AmberWave Systems CorporationInventors: Thomas A. Langdo, Matthew T. Currie, Glyn Braithwaite, Richard Hammond, Anthony J. Lochtefeld, Eugene A. Fitzgerald
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Patent number: 7091535Abstract: A high voltage PMOS device having an improved breakdown voltage is achieved. An asymmetrical high voltage integrated circuit structure comprises a gate electrode on a substrate and source and drain regions within the substrate on either side and adjacent to the gate electrode wherein the source region is encompassed by an n-well. A symmetrical high voltage integrated circuit structure comprises a gate electrode on a substrate, source and drain regions within the substrate on either side and adjacent to the gate electrode, and an n-well in the substrate underlying the gate electrode. The n-well in both structures shifts the breakdown point from the silicon surface to the bottom of the source or drain regions.Type: GrantFiled: March 5, 2004Date of Patent: August 15, 2006Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Hung-Chih Tsai, Chien-Chih Chou, Ying-Ting Chang, Che-Jung Chu, Kuo-Chio Liu
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Patent number: 7071503Abstract: A semi-conductor structure for controlling and switching a current has a switch element and an edge element. The switch element contains a first semi-conductor area of a first conductivity type contacted by way of an anode electrode and a cathode electrode, a depletion area that is arranged inside the first semi-conductor area and that can be influenced by a control voltage applied to the control electrode for the purpose of current control, and an island area of a second conductivity type that is buried inside the first semi-conductor area. The edge element contains an edge area of the second conductivity type that is buried inside the first semi-conductive area and that is formed on a common level with the buried island area, in addition to an edge terminating area of a second conductivity type adjacent the edge area.Type: GrantFiled: September 24, 2004Date of Patent: July 4, 2006Assignee: SiCED Electronics Development GmbH & Co. KGInventors: Karl Dohnke, Rudolf Elpelt, Peter Friedrichs, Heinz Mitlehner, Reinhold Schörner
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Patent number: 7064407Abstract: A JFET controlled Schottky barrier diode includes a p-type diffusion region integrated into the cathode of the Schottky diode to form an integrated JFET where the integrated JFET provides on-off control of the Schottky barrier diode. The p-type diffusion region encloses a portion of the forward current path of the Schottky barrier diode where the p-type diffusion region forms the gate of the JFET and the enclosed portion of the forward current path forms the channel region of the JFET. By applying a reverse biased potential to the gate of the JEFT with respect to the anode of the Schottky diode, the forward current of the Schottky diode can be pinched off, thereby providing on-off control over the Schottky diode forward current.Type: GrantFiled: February 4, 2005Date of Patent: June 20, 2006Assignee: Micrel, Inc.Inventor: Shekar Mallikarjunaswamy
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Patent number: 7038260Abstract: A method for fabricating a dual gate structure for JFETs and MESFETs and the associated devices. Trenches are etched in a semiconductor substrate for fabrication of a gate structure for a JFET or MESFET. A sidewall spacer may be formed on the walls of the trenches to adjust the lateral dimension for a first gate. Following the formation of the first gate by implantation or deposition, a buffer region is implanted below the first gate using a complementary dopant and a second sidewall spacer with a thickness that may be the same or greater than the thickness of the first sidewall spacer. Subsequent to the buffer implant, a second gate is implanted beneath the buffer layer using a third sidewall spacer with a greater thickness than the first sidewall spacer.Type: GrantFiled: March 4, 2003Date of Patent: May 2, 2006Assignee: Lovoltech, IncorporatedInventor: Ho-Yuan Yu
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Patent number: 7026669Abstract: A lateral channel transistor with an optimal conducting channel formed in widebandgap semiconductors like Silicon Carbide and Diamond is provided. Contrary to conventional vertical design of power transistors, a higher, optimum doping for a given thickness supports higher source/drain blocking voltage. A backside gate is insulated from the channel region using a low doped layer of the opposite conductivity type than the channel region to support the rated blocking voltage of the device.Type: GrantFiled: June 3, 2004Date of Patent: April 11, 2006Inventor: Ranbir Singh
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Patent number: 7023033Abstract: A lateral JFET has a basic structure including an n-type semiconductor layer (3) formed of an n-type impurity region and a p-type semiconductor layer formed of a p-type impurity region on the n-type semiconductor layer (3). Moreover, in the p-type semiconductor layer, there are provided a p+-type gate region layer (7) extending into the n-type semiconductor layer (3) and containing p-type impurities of an impurity concentration higher than that of the n-type semiconductor layer (3) and an n+-type drain region layer (9) spaced from the p+-type gate region layer (7) by a predetermined distance and containing n-type impurities of an impurity concentration higher than that of the n-type semiconductor layer (3). With this structure, the lateral JFET can be provided that has an ON resistance further decreased while maintaining a high breakdown voltage performance.Type: GrantFiled: June 11, 2002Date of Patent: April 4, 2006Assignee: Sumitomo Electric Industries, Ltd.Inventors: Shin Harada, Kenichi Hirotsu, Hiroyuki Matsunami, Tsunenobu Kimoto
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Patent number: 7009229Abstract: A protection device for integrated circuits. A complementary well is fabricated in a semiconductor substrate. An enhancement mode junction field effect transistor (JFET) is fabricated in the complementary well. An interface bonding pad is fabricated above the JFET. A source contact is also fabricated in the well. The gate and drain of the JFET are coupled to the interface bonding pad and the source of the JFET is coupled to the substrate.Type: GrantFiled: March 3, 2004Date of Patent: March 7, 2006Assignee: Lovoltech, IncorporatedInventors: Chong Ming Lin, Ho Yuan Yu
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Patent number: 6967371Abstract: A method and apparatus for providing a meshed power and signal bus system on an array type integrated circuit that minimizes the size of the circuit. In a departure from the art, through-holes for the mesh system are placed in the cell array, as well as the peripheral circuits. The power and signal buses of the mesh system run in both vertical and horizontal directions across the array such that all the vertical buses lie in one metal layer, and all the horizontal buses lie in another metal layer. The buses of one layer are connected to the appropriate bus(es) of the other layer using through-holes located in the array. Once connected, the buses extend to the appropriate sense amplifier drivers. The method and apparatus are facilitated by an improved subdecoder circuit implementing a hierarchical word line structure.Type: GrantFiled: September 20, 2004Date of Patent: November 22, 2005Assignees: Hitachi, Ltd., Texas Instruments IncorporatedInventors: Goro Kitsukawa, Takesada Akiba, Hiroshi Otori, William R. McKee, Jeffrey E. Koelling, Troy H. Herndon
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Patent number: 6960798Abstract: A semiconductor component has a semiconductor body comprising a blocking pn junction, a source zone of a first conductivity type connected to a first electrode and bordering on a zone forming the blocking pn junction of a second conductivity type complementary to the first conductivity type, and a drain zone of the first conductivity type connected to a second electrode. The side of the zone of the second conductivity type facing the drain zone forms a first surface, and in the region between the first surface and a second surface located between the first surface and the drain zone, comprises areas of the first and second conductivity type nested in one another. The second surface is positioned at a distance from the drain zone such that the areas of the first and second conductivity type nested in each other do not reach the drain zone.Type: GrantFiled: June 6, 2003Date of Patent: November 1, 2005Assignee: Infineon Technologies AGInventors: Gerald Deboy, Dirk Ahlers, Helmut Strack, Michael Rueb, Hans Martin Weber
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Patent number: 6919598Abstract: A structure for making a LDMOS transistor (100) includes an interdigitated source finger (26) and a drain finger (21) on a substrate (15). Termination regions (35, 37) are formed at the tips of the source finger and drain finger. A drain (45) of a second conductivity type is formed in the substrate of a first conductivity type. A field reduction region (7) of a second conductivity type is formed in the drain and is wrapped around the termination regions for controlling the depletion at the tip and providing higher voltage breakdown of the transistor.Type: GrantFiled: March 10, 2003Date of Patent: July 19, 2005Inventors: Zia Hossain, Mohamed Imam, Joe Fulton
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Patent number: 6903426Abstract: A semiconductor switching device includes two FETs with different device characteristics, a common input terminal, and two output terminals. A signal transmitting FET has a gate width of 500 ?m and a signal receiving FET has a gate width of 400 ?m. A resistor connecting a gate electrode and a control terminal of the signal transmitting FET is tightly configured to provide expanding space for the FET. Despite the reduced size, the switching device can allow a maximum power of 22.5 dBm to pass through because of the asymmetrical device design. The switching device operates at frequencies of 2.4 GHz or higher without use of shunt FET.Type: GrantFiled: May 24, 2002Date of Patent: June 7, 2005Assignee: Sanyo Electric Co., Ltd.Inventors: Tetsuro Asano, Toshikazu Hirai, Mikito Sakakibara
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Patent number: 6894329Abstract: A semiconductor component has a semiconductor body comprising blocking pn junction, a source zone of a first conductivity type connected to a first electrode and bordering on a zone forming the blocking pn junction of a second conductivity type complementary to the first conductivity type, and a drain zone of the first conductivity type connected to a second electrode. The side of the zone of the second conductivity type facing the drain zone forms a first surface, and in the region between the first surface and a second surface located between the first surface and the drain zone, comprises areas of the first and second conductivity type nested in one another. The second surface coincides with the surface of the drain zone facing the source zone, such that the regions of the first and second conductivity type nested inside each other reach the drain zone.Type: GrantFiled: June 6, 2003Date of Patent: May 17, 2005Assignee: Infineon Technologies AGInventors: Gerald Deboy, Dirk Ahlers, Helmut Strack, Michael Rueb, Hans Martin Weber
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Patent number: 6888182Abstract: A thin film transistor of the present invention is provided with (i) a plurality of divided channel regions formed under a gate electrode, and (ii) divided source regions and divided drain regions between which each of the divided channel regions is sandwiched, the divided source regions being connected with one another, and the divided drain regions being connected with one another. Here, the divided channel regions are so arranged that a spacing between the divided channel regions is smaller than a channel divided width which is a width of one divided channel region, the channel divided width is not more than 50 ?m, and the spacing is not less than 3 ?m. With this arrangement, it is possible to provide a thin film transistor capable of obtaining reliability with reducing the variation in threshold voltage by reducing the self-heating at the channel regions, as well as capable of reducing the increase of a layout area.Type: GrantFiled: March 18, 2003Date of Patent: May 3, 2005Assignee: Sharp Kabushiki KaishaInventors: Masahiro Mitani, Yasumori Fukushima
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Patent number: 6870189Abstract: A junction field effect transistor (JFET) is provided that is capable of a high voltage resistance, high current switching operation, that operates with a low loss, and that has little variation. This JFET is provided with a gate region (2) of a second conductivity type provided on a surface of a semiconductor substrate, a source region (1) of a first conductivity type, a channel region (10) of the first conductivity type that adjoins the source region, a confining region (5) of the second conductivity type that adjoins the gate region and confines the channel region, a drain region (3) of the first conductivity type provided on a reverse face, and a drift region (4) of the first conductivity type that continuously lies in a direction of thickness of the substrate from a channel to a drain.Type: GrantFiled: September 11, 2000Date of Patent: March 22, 2005Assignee: Sumitomo Electric Industries, Ltd.Inventors: Shin Harada, Kenichi Hirotsu, Hiroyuki Matsunami, Tsunenobu Kimoto
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Patent number: 6855981Abstract: A silicon carbide power device includes a junction field effect transistor and a protective diode, which is a Zener or PN junction diode. The PN junction of the protective diode has a breakdown voltage lower than the PN junction of the transistor. Another silicon carbide power device includes a protective diode, which is a Schottky diode. The Schottky diode has a breakdown voltage lower than the PN junction of the transistor by adjusting Schottky barrier height or the depletion layer formed in the semiconductor included in the Schottky diode. Another silicon carbide power device includes three protective diodes, which are Zener diodes. Two of the protective diodes are used to clamp the voltages applied to the gate and the drain of the transistor due to surge energy and used to release the surge energy. The last diode is a thermo-sensitive diode, with which the temperature of the JFET is measured.Type: GrantFiled: August 29, 2002Date of Patent: February 15, 2005Assignee: Denso CorporationInventors: Rajesh Kumar, Hiroki Nakamura, Tsuyoshi Yamamoto, Toshiyuki Morishita
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Patent number: 6831317Abstract: A method and apparatus for providing a meshed power and signal bus system on an array type integrated circuit that minimizes the size of the circuit. In a departure from the art, through-holes for the mesh system are placed in the cell array, as well as the peripheral circuits. The power and signal buses of the mesh system run in both vertical and horizontal directions across the array such that all the vertical buses lie in one metal layer, and all the horizontal buses lie in another metal layer. The buses of one layer are connected to the appropriate bus(es) of the other layer using through-holes located in the array. Once connected, the buses extend to the appropriate sense amplifier drivers. The method and apparatus are facilitated by an improved subdecoder circuit implementing a hierarchical word line structure.Type: GrantFiled: December 10, 2002Date of Patent: December 14, 2004Assignee: Hitachi, Ltd.Inventors: Goro Kitsukawa, Takesada Akiba, Hiroshi Otori, William R. McKee, Jeffrey E. Koelling, Troy H. Herndon
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Patent number: 6828609Abstract: A semiconductor component having a semiconductor body comprises a blocking pn junction, a source zone of a first conductivity type and bordering on a zone forming the blocking pn junction of a second conductivity type complementary to the first conductivity type, and a drain zone of the first conductivity type. The side of the zone of the second conductivity type faces the drain zone forming a first surface, and in the region between the first surface and a second surface areas of the first and second conductivity type are nested in one another. The areas of the first and second conductivity type are variably so doped that near the first surface doping atoms of the second conductivity type predominate, and near the second surface doping atoms of the first conductivity type predominate. Furthermore a plurality of floating zones of the first and second conductivity type is provided.Type: GrantFiled: June 6, 2003Date of Patent: December 7, 2004Assignee: Infineon Technologies AGInventors: Gerald Deboy, Dirk Ahlers, Helmut Strack, Michael Rueb, Hans Martin Weber
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Patent number: 6825514Abstract: A process for manufacturing of a semiconductor device comprising a blocking pn junction, a source zone of a first conductivity type connected to a first electrode and bordering on a zone forming the blocking pn junction of a second conductivity type complementary to the first conductivity type, and a drain zone of the first conductivity type connected to a second electrode, the side of the zone of the second conductivity type facing the drain zone forming a first surface, and in the region between the first surface and a second surface located between the first surface and the drain zone, areas of the first and second conductivity type nested in one another, comprises the step of: varying in individual semiconductor layers, by doping, the degree of compensation in the regions of the second conductivity type.Type: GrantFiled: June 6, 2003Date of Patent: November 30, 2004Assignee: Infineon Technologies AGInventors: Gerald Deboy, Dirk Ahlers, Helmut Strack, Michael Rueb, Hans Martin Weber
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Patent number: 6815794Abstract: Semiconductor devices with a multiple isolation structure and methods for fabricating the same are provided. In one aspect, a semiconductor device comprises a heavily doped buried layer having a first conductivity type, which is formed in a predetermined region of a semiconductor substrate, and an epitaxial layer having the first conductivity type, which covers an entire surface of the semiconductor substrate. A device isolation structure is disposed such that the device isolation structure penetrates the epitaxial layer and a portion of the semiconductor substrate to define a device region. The device isolation structure includes an upper isolation structure penetrating an epitaxial layer as well as a lower isolation structure formed in the semiconductor substrate under the upper isolation structure.Type: GrantFiled: February 25, 2003Date of Patent: November 9, 2004Assignee: Samsung Electronics Co., Ltd.Inventors: Hwa-Sook Shin, Kwang-Dong Yoo
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Patent number: 6815742Abstract: A method and apparatus for providing a meshed power and signal bus system on an array type integrated circuit that minimizes the size of the circuit. In a departure from the art, through-holes for the mesh system are placed in the cell array, as well as the peripheral circuits. The power and signal buses of the mesh system run in both vertical and horizontal directions across the array such that all the vertical buses lie in one metal layer, and all the horizontal buses lie in another metal layer. The buses of one layer are connected to the appropriate bus(es) of the other layer using through-holes located in the array. Once connected, the buses extend to the appropriate sense amplifier drivers. The method and apparatus are facilitated by an improved subdecoder circuit implementing a hierarchical word line structure.Type: GrantFiled: December 5, 2003Date of Patent: November 9, 2004Assignees: Hitachi, Ltd., Texas Instruments IncorporatedInventors: Goro Kitsukawa, Takesada Akiba, Hiroshi Otori, William R. McKee, Jeffrey E. Koelling, Troy H. Herndon
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Patent number: 6800887Abstract: Known techniques to improve metal-oxide-semiconductor field effect transistor (MOSFET) performance is to add a high stress dielectric layer to the MOSFET. The high stress dielectric layer introduces stress in the MOSFET that causes electron mobility drive current to increase. This technique increases process complexity, however, and can degrade PMOS performance. Embodiments of the present invention create dislocation loops in the MOSFET substrate to introduce stress and implants nitrogen in the substrate to control the growth of the dislocation loops so that the stress remains beneath the channel of the MOSFET.Type: GrantFiled: March 31, 2003Date of Patent: October 5, 2004Assignee: Intel CorporationInventors: Cory E. Weber, Mark Armstrong, Harold Kennel, Tahir Ghani, Paul A. Packan, Scott Thompson