With Multiple Channels Or Channel Segments Connected In Parallel, Or With Channel Much Wider Than Length Between Source And Drain (e.g., Power Jfet) Patents (Class 257/287)
  • Publication number: 20080067561
    Abstract: A quantum interference transistor comprising an source region for emitting electron waves into a vacuum, a drain region for collecting the electron waves, a repeating nanostructure in a region between the source and drain regions for introducing a constant phase shift between a plurality of electron waves, and a gate for controlling the phase shift introduced by the nanostructure; wherein the repeating nanostructure is characterized by having sharply defined geometric patterns or indents of a dimension that creates de Broglie wave interference.
    Type: Application
    Filed: September 18, 2007
    Publication date: March 20, 2008
    Inventors: Amiran Bibilashvili, Avto Tavkhelidze
  • Patent number: 7329913
    Abstract: A semiconductor device comprising a semiconductor body having a top surface and a first and second laterally opposite sidewalls as formed on an insulating substrate. A gate dielectric is formed on the top surface of the semiconductor body and on the first and second laterally opposite sidewalls of the semiconductor body. A gate electrode is then formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the first and second laterally opposite sidewalls of the semiconductor body. The gate electrode comprises a metal film formed directly adjacent to the gate dielectric layer. A pair of source and drain regions are uniformed in the semiconductor body on opposite sides of the gate electrode.
    Type: Grant
    Filed: December 27, 2004
    Date of Patent: February 12, 2008
    Assignee: Intel Corporation
    Inventors: Justin K. Brask, Brian S. Doyle, Mark L. Doczy, Robert S. Chau
  • Patent number: 7297580
    Abstract: The present invention provides a unit cell of a metal-semiconductor field-effect transistor (MESFET). The unit cell of the MESFET includes a source, a drain and a gate. The gate is disposed between the source and the drain and on an n-type conductivity channel layer. A p-type conductivity region is provided beneath the source and has an end that extends towards the drain. The p-type conductivity region is spaced apart from the n-type conductivity channel region and is electrically coupled to the source.
    Type: Grant
    Filed: June 1, 2005
    Date of Patent: November 20, 2007
    Assignee: Cree, Inc.
    Inventor: Saptharishi Sriram
  • Patent number: 7288803
    Abstract: A III-nitride power semiconductor device that includes a current sense electrode.
    Type: Grant
    Filed: September 30, 2005
    Date of Patent: October 30, 2007
    Assignee: International Rectifier Corporation
    Inventors: Robert Beach, Paul Bridger, Daniel M. Kinzer
  • Patent number: 7276723
    Abstract: Alternate layers of wide band gap and narrow band gaps of different kinds of semiconductors are used to form multiple channels of a FET. The channels are doped or formed as 2-DEG/2-DHG in narrow band semiconductor by charge supply layer in the wide band gap semiconductor. The different kinds of semiconductors form heterojunctions to confine the electrons/holes in separate thin spikes layers. A number of spikes (3-10 nm thick) of different doped or 2-DEG/2-DHG concentrations in various channels can result in overall electron concentration gradient such as a 1/x3 electron/hole concentrations profile. Such an electron/hole concentration gradient can result in a linear variation of drain current with voltage to obtain a wide dynamic range.
    Type: Grant
    Filed: August 18, 2005
    Date of Patent: October 2, 2007
    Assignee: Epitaxial Technologies
    Inventors: Ayub Mohammed Fathimulla, Harry Stephen Hier, Olaleye Adetord Aina
  • Patent number: 7274051
    Abstract: In a field effect transistor (FET), and a method of fabricating the same, the FET includes a semiconductor substrate, source and drain regions formed on the semiconductor substrate, a plurality of wire channels electrically connecting the source and drain regions, the plurality of wire channels being arranged in two columns and at least two rows, and a gate dielectric layer surrounding each of the plurality of wire channels and a gate electrode surrounding the gate dielectric layer and each of the plurality of wire channels.
    Type: Grant
    Filed: March 9, 2005
    Date of Patent: September 25, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sungmin Kim, Ming Li, Eungjung Yoon
  • Patent number: 7268394
    Abstract: Junction field effect transistors (JFETs) can be fabricated with an epitaxial layer that forms a sufficiently thick channel region to enable the JFET for use in high voltage applications (e.g., having a breakdown voltage greater than about 20V). Additionally or alternatively, threshold voltage (VT) implants can be introduced at one or more of the gate, source and drain regions to improve noise performance of the JFET. Additionally, fabrication of such a JFET can be facilitated forming the entire JFET structure concurrently with a CMOS fabrication process and/or with a BiCMOS fabrication process.
    Type: Grant
    Filed: January 18, 2005
    Date of Patent: September 11, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Pinghai Hao, Fan-Chi Hou, Imran Khan
  • Patent number: 7265399
    Abstract: High power transistors are provided. The transistors include a source region, a drain region and a gate contact. The gate contact is positioned between the source region and the drain region. First and second ohmic contacts are provided on the source and drain regions, respectively. The first and second ohmic contacts respectively define a source contact and a drain contact. The source contact and the drain contact have respective first and second widths. The first and second widths are different. Related methods of fabricating transistors are also provided.
    Type: Grant
    Filed: October 29, 2004
    Date of Patent: September 4, 2007
    Assignee: Cree, Inc.
    Inventors: Saptharishi Sriram, Jason Henning
  • Patent number: 7221010
    Abstract: Silicon carbide metal-oxide semiconductor field effect transistors (MOSFETs) may include an n-type silicon carbide drift layer, a first p-type silicon carbide region adjacent the drift layer and having a first n-type silicon carbide region therein, an oxide layer on the drift layer, and an n-type silicon carbide limiting region disposed between the drift layer and a portion of the first p-type region. The limiting region may have a carrier concentration that is greater than the carrier concentration of the drift layer. Methods of fabricating silicon carbide MOSFET devices are also provided.
    Type: Grant
    Filed: October 30, 2003
    Date of Patent: May 22, 2007
    Assignee: Cree, Inc.
    Inventor: Sei-Hyung Ryu
  • Patent number: 7211864
    Abstract: A fully depleted castellated-gate MOSFET device is disclosed along with a method of making the same. The device has robust I/O applications, and includes a semiconductor substrate body having an upper portion with an upper end surface and a lower portion with a lower end surface. A source region, a drain region, and a channel-forming region between the source and drain regions are all formed in the semiconductor substrate body. trench isolation insulator islands surround the source and drain regions as well as the channel-forming region. The channel-forming region is made up of a plurality of thin, spaced, vertically-orientated conductive channel elements that span longitudinally along the device between the source and drain regions. A gate structure is also provided in the form of a plurality of spaced, castellated gate elements interposed between the channel elements.
    Type: Grant
    Filed: September 13, 2004
    Date of Patent: May 1, 2007
    Inventor: John J. Seliskar
  • Patent number: 7202517
    Abstract: A multiple gate semiconductor device. The device includes at least two gates. The dopant distribution in the semiconductor body of the device varies from a low value near the surface of the body towards a higher value inside the body of the device.
    Type: Grant
    Filed: July 16, 2004
    Date of Patent: April 10, 2007
    Assignee: Interuniversitair Microelektronica Centrum (IMEC vzw)
    Inventors: Abhisek Dixit, Kristin De Meyer
  • Patent number: 7187022
    Abstract: In a semiconductor device having a multi-bridge-channel, and a method for fabricating the same, the device includes first and second semiconductor posts protruding from a surface of a semiconductor substrate and having a source and a drain region, respectively, in upper side portions thereof, channel semiconductor layers connecting upper side portions of the first and second semiconductor posts, a gate insulation layer on the channel semiconductor layers and the semiconductor substrate, the gate insulation layer surrounding at least a portion of the channel semiconductor layers, a gate electrode layer on the gate insulation layer to enclose at least a portion of a region between the channel semiconductor layers, and junction auxiliary layers formed between the channel semiconductor layers, the junction auxiliary layers contacting the gate electrode layer and upper side portions of the first and second semiconductor posts, and having a same width as the channel semiconductor layers.
    Type: Grant
    Filed: November 23, 2005
    Date of Patent: March 6, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Eun-jung Yun, Sung-min Kim, Sung-young Lee
  • Patent number: 7166894
    Abstract: The present invention relates to a power junction device including a substrate of the SiCOI type with a layer of silicon carbide (16) insulated from a solid carrier (12) by a buried layer of insulant (14), and including at least one Schottky contact between a first metal layer (40) and the surface layer of silicon carbide (16), the first metal layer (30) constituting an anode.
    Type: Grant
    Filed: March 12, 2003
    Date of Patent: January 23, 2007
    Assignee: Commissariat a l'Energie Atomique
    Inventors: François Templier, Thierry Billon, Nicolas Daval
  • Patent number: 7141837
    Abstract: A MOS transistor formed in a silicon substrate comprising an active area surrounded with an insulating wall, a first conductive strip covering a central strip of the active area, one or several second conductive strips placed in the active area right above the first strip, and conductive regions placed in two recesses of the insulating wall and placed against the ends of the first and second strips, the silicon surfaces opposite to the conductive strips and regions being covered with an insulator forming a gate oxide.
    Type: Grant
    Filed: April 2, 2004
    Date of Patent: November 28, 2006
    Assignee: STMicroelectronics S.A.
    Inventors: Philippe Coronel, Yves Morand, Thomas Skotnicki, Robin Cerutti
  • Patent number: 7141838
    Abstract: An integrated circuit system includes providing a semiconductor substrate and forming buried word lines in the semiconductor substrate with the buried word lines including vertical charge-trapping dielectric layers. The system further includes forming bit lines further comprising forming in-substrate portions in the semiconductor substrate, and forming above-substrate portions over the semiconductor substrate.
    Type: Grant
    Filed: January 27, 2005
    Date of Patent: November 28, 2006
    Assignee: Spansion LLC
    Inventor: Michael Brennan
  • Patent number: 7135747
    Abstract: A high power, high frequency semiconductor device has a plurality of unit cells connected in parallel. The unit cells each having a controlling electrode and first and second controlled electrodes. A thermal spacer divides at least one of the unit cells into a first active portion and a second active portion, spaced apart from the first potion by the thermal spacer. The controlling electrode and the first and second controlled electrodes of the unit cell cross over the first thermal spacer.
    Type: Grant
    Filed: February 25, 2004
    Date of Patent: November 14, 2006
    Assignee: Cree, Inc.
    Inventors: Scott Thomas Allen, James William Milligan
  • Patent number: 7126173
    Abstract: An electronic power device of improved structure is fabricated with MOS technology to have a gate finger region and corresponding source regions on either sides of the gate region. This device has a first-level metal layer arranged to independently contact the gate region and source regions, and has a protective passivation layer arranged to cover the gate region. Advantageously, a wettable metal layer, deposited onto the passivation layer and the first-level metal layer, overlies said source regions. In this way, the additional wettable metal layer is made to act as a second-level metal.
    Type: Grant
    Filed: October 30, 2002
    Date of Patent: October 24, 2006
    Assignee: STMicroelectronics, S.r.l.
    Inventors: Ferruccio Frisina, Antonio Pinto, Angelo Magri
  • Patent number: 7112832
    Abstract: A transistor (10) overlies a substrate (12) and has a plurality of overlying channels (72, 74, 76) that are formed in a stacked arrangement. A continuous gate (60) material surrounds each of the channels. Each of the channels is coupled to source and drain electrodes (S/D) to provide increased channel surface area in a same area that a single channel structure is conventionally implemented. A vertical channel dimension between two regions of the gate (60) are controlled by a growth process as opposed to lithographical or spacer formation techniques. The gate is adjacent all sides of the multiple overlying channels. Each channel is formed by growth from a common seed layer and the source and drain electrodes and the channels are formed of a substantially homogenous crystal lattice.
    Type: Grant
    Filed: March 29, 2005
    Date of Patent: September 26, 2006
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Marius K. Orlowski, Leo Mathew
  • Patent number: 7109516
    Abstract: The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication.
    Type: Grant
    Filed: August 25, 2005
    Date of Patent: September 19, 2006
    Assignee: AmberWave Systems Corporation
    Inventors: Thomas A. Langdo, Matthew T. Currie, Glyn Braithwaite, Richard Hammond, Anthony J. Lochtefeld, Eugene A. Fitzgerald
  • Patent number: 7091535
    Abstract: A high voltage PMOS device having an improved breakdown voltage is achieved. An asymmetrical high voltage integrated circuit structure comprises a gate electrode on a substrate and source and drain regions within the substrate on either side and adjacent to the gate electrode wherein the source region is encompassed by an n-well. A symmetrical high voltage integrated circuit structure comprises a gate electrode on a substrate, source and drain regions within the substrate on either side and adjacent to the gate electrode, and an n-well in the substrate underlying the gate electrode. The n-well in both structures shifts the breakdown point from the silicon surface to the bottom of the source or drain regions.
    Type: Grant
    Filed: March 5, 2004
    Date of Patent: August 15, 2006
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Hung-Chih Tsai, Chien-Chih Chou, Ying-Ting Chang, Che-Jung Chu, Kuo-Chio Liu
  • Patent number: 7071503
    Abstract: A semi-conductor structure for controlling and switching a current has a switch element and an edge element. The switch element contains a first semi-conductor area of a first conductivity type contacted by way of an anode electrode and a cathode electrode, a depletion area that is arranged inside the first semi-conductor area and that can be influenced by a control voltage applied to the control electrode for the purpose of current control, and an island area of a second conductivity type that is buried inside the first semi-conductor area. The edge element contains an edge area of the second conductivity type that is buried inside the first semi-conductive area and that is formed on a common level with the buried island area, in addition to an edge terminating area of a second conductivity type adjacent the edge area.
    Type: Grant
    Filed: September 24, 2004
    Date of Patent: July 4, 2006
    Assignee: SiCED Electronics Development GmbH & Co. KG
    Inventors: Karl Dohnke, Rudolf Elpelt, Peter Friedrichs, Heinz Mitlehner, Reinhold Schörner
  • Patent number: 7064407
    Abstract: A JFET controlled Schottky barrier diode includes a p-type diffusion region integrated into the cathode of the Schottky diode to form an integrated JFET where the integrated JFET provides on-off control of the Schottky barrier diode. The p-type diffusion region encloses a portion of the forward current path of the Schottky barrier diode where the p-type diffusion region forms the gate of the JFET and the enclosed portion of the forward current path forms the channel region of the JFET. By applying a reverse biased potential to the gate of the JEFT with respect to the anode of the Schottky diode, the forward current of the Schottky diode can be pinched off, thereby providing on-off control over the Schottky diode forward current.
    Type: Grant
    Filed: February 4, 2005
    Date of Patent: June 20, 2006
    Assignee: Micrel, Inc.
    Inventor: Shekar Mallikarjunaswamy
  • Patent number: 7038260
    Abstract: A method for fabricating a dual gate structure for JFETs and MESFETs and the associated devices. Trenches are etched in a semiconductor substrate for fabrication of a gate structure for a JFET or MESFET. A sidewall spacer may be formed on the walls of the trenches to adjust the lateral dimension for a first gate. Following the formation of the first gate by implantation or deposition, a buffer region is implanted below the first gate using a complementary dopant and a second sidewall spacer with a thickness that may be the same or greater than the thickness of the first sidewall spacer. Subsequent to the buffer implant, a second gate is implanted beneath the buffer layer using a third sidewall spacer with a greater thickness than the first sidewall spacer.
    Type: Grant
    Filed: March 4, 2003
    Date of Patent: May 2, 2006
    Assignee: Lovoltech, Incorporated
    Inventor: Ho-Yuan Yu
  • Patent number: 7026669
    Abstract: A lateral channel transistor with an optimal conducting channel formed in widebandgap semiconductors like Silicon Carbide and Diamond is provided. Contrary to conventional vertical design of power transistors, a higher, optimum doping for a given thickness supports higher source/drain blocking voltage. A backside gate is insulated from the channel region using a low doped layer of the opposite conductivity type than the channel region to support the rated blocking voltage of the device.
    Type: Grant
    Filed: June 3, 2004
    Date of Patent: April 11, 2006
    Inventor: Ranbir Singh
  • Patent number: 7023033
    Abstract: A lateral JFET has a basic structure including an n-type semiconductor layer (3) formed of an n-type impurity region and a p-type semiconductor layer formed of a p-type impurity region on the n-type semiconductor layer (3). Moreover, in the p-type semiconductor layer, there are provided a p+-type gate region layer (7) extending into the n-type semiconductor layer (3) and containing p-type impurities of an impurity concentration higher than that of the n-type semiconductor layer (3) and an n+-type drain region layer (9) spaced from the p+-type gate region layer (7) by a predetermined distance and containing n-type impurities of an impurity concentration higher than that of the n-type semiconductor layer (3). With this structure, the lateral JFET can be provided that has an ON resistance further decreased while maintaining a high breakdown voltage performance.
    Type: Grant
    Filed: June 11, 2002
    Date of Patent: April 4, 2006
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Shin Harada, Kenichi Hirotsu, Hiroyuki Matsunami, Tsunenobu Kimoto
  • Patent number: 7009229
    Abstract: A protection device for integrated circuits. A complementary well is fabricated in a semiconductor substrate. An enhancement mode junction field effect transistor (JFET) is fabricated in the complementary well. An interface bonding pad is fabricated above the JFET. A source contact is also fabricated in the well. The gate and drain of the JFET are coupled to the interface bonding pad and the source of the JFET is coupled to the substrate.
    Type: Grant
    Filed: March 3, 2004
    Date of Patent: March 7, 2006
    Assignee: Lovoltech, Incorporated
    Inventors: Chong Ming Lin, Ho Yuan Yu
  • Patent number: 6967371
    Abstract: A method and apparatus for providing a meshed power and signal bus system on an array type integrated circuit that minimizes the size of the circuit. In a departure from the art, through-holes for the mesh system are placed in the cell array, as well as the peripheral circuits. The power and signal buses of the mesh system run in both vertical and horizontal directions across the array such that all the vertical buses lie in one metal layer, and all the horizontal buses lie in another metal layer. The buses of one layer are connected to the appropriate bus(es) of the other layer using through-holes located in the array. Once connected, the buses extend to the appropriate sense amplifier drivers. The method and apparatus are facilitated by an improved subdecoder circuit implementing a hierarchical word line structure.
    Type: Grant
    Filed: September 20, 2004
    Date of Patent: November 22, 2005
    Assignees: Hitachi, Ltd., Texas Instruments Incorporated
    Inventors: Goro Kitsukawa, Takesada Akiba, Hiroshi Otori, William R. McKee, Jeffrey E. Koelling, Troy H. Herndon
  • Patent number: 6960798
    Abstract: A semiconductor component has a semiconductor body comprising a blocking pn junction, a source zone of a first conductivity type connected to a first electrode and bordering on a zone forming the blocking pn junction of a second conductivity type complementary to the first conductivity type, and a drain zone of the first conductivity type connected to a second electrode. The side of the zone of the second conductivity type facing the drain zone forms a first surface, and in the region between the first surface and a second surface located between the first surface and the drain zone, comprises areas of the first and second conductivity type nested in one another. The second surface is positioned at a distance from the drain zone such that the areas of the first and second conductivity type nested in each other do not reach the drain zone.
    Type: Grant
    Filed: June 6, 2003
    Date of Patent: November 1, 2005
    Assignee: Infineon Technologies AG
    Inventors: Gerald Deboy, Dirk Ahlers, Helmut Strack, Michael Rueb, Hans Martin Weber
  • Patent number: 6919598
    Abstract: A structure for making a LDMOS transistor (100) includes an interdigitated source finger (26) and a drain finger (21) on a substrate (15). Termination regions (35, 37) are formed at the tips of the source finger and drain finger. A drain (45) of a second conductivity type is formed in the substrate of a first conductivity type. A field reduction region (7) of a second conductivity type is formed in the drain and is wrapped around the termination regions for controlling the depletion at the tip and providing higher voltage breakdown of the transistor.
    Type: Grant
    Filed: March 10, 2003
    Date of Patent: July 19, 2005
    Inventors: Zia Hossain, Mohamed Imam, Joe Fulton
  • Patent number: 6903426
    Abstract: A semiconductor switching device includes two FETs with different device characteristics, a common input terminal, and two output terminals. A signal transmitting FET has a gate width of 500 ?m and a signal receiving FET has a gate width of 400 ?m. A resistor connecting a gate electrode and a control terminal of the signal transmitting FET is tightly configured to provide expanding space for the FET. Despite the reduced size, the switching device can allow a maximum power of 22.5 dBm to pass through because of the asymmetrical device design. The switching device operates at frequencies of 2.4 GHz or higher without use of shunt FET.
    Type: Grant
    Filed: May 24, 2002
    Date of Patent: June 7, 2005
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Tetsuro Asano, Toshikazu Hirai, Mikito Sakakibara
  • Patent number: 6894329
    Abstract: A semiconductor component has a semiconductor body comprising blocking pn junction, a source zone of a first conductivity type connected to a first electrode and bordering on a zone forming the blocking pn junction of a second conductivity type complementary to the first conductivity type, and a drain zone of the first conductivity type connected to a second electrode. The side of the zone of the second conductivity type facing the drain zone forms a first surface, and in the region between the first surface and a second surface located between the first surface and the drain zone, comprises areas of the first and second conductivity type nested in one another. The second surface coincides with the surface of the drain zone facing the source zone, such that the regions of the first and second conductivity type nested inside each other reach the drain zone.
    Type: Grant
    Filed: June 6, 2003
    Date of Patent: May 17, 2005
    Assignee: Infineon Technologies AG
    Inventors: Gerald Deboy, Dirk Ahlers, Helmut Strack, Michael Rueb, Hans Martin Weber
  • Patent number: 6888182
    Abstract: A thin film transistor of the present invention is provided with (i) a plurality of divided channel regions formed under a gate electrode, and (ii) divided source regions and divided drain regions between which each of the divided channel regions is sandwiched, the divided source regions being connected with one another, and the divided drain regions being connected with one another. Here, the divided channel regions are so arranged that a spacing between the divided channel regions is smaller than a channel divided width which is a width of one divided channel region, the channel divided width is not more than 50 ?m, and the spacing is not less than 3 ?m. With this arrangement, it is possible to provide a thin film transistor capable of obtaining reliability with reducing the variation in threshold voltage by reducing the self-heating at the channel regions, as well as capable of reducing the increase of a layout area.
    Type: Grant
    Filed: March 18, 2003
    Date of Patent: May 3, 2005
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Masahiro Mitani, Yasumori Fukushima
  • Patent number: 6870189
    Abstract: A junction field effect transistor (JFET) is provided that is capable of a high voltage resistance, high current switching operation, that operates with a low loss, and that has little variation. This JFET is provided with a gate region (2) of a second conductivity type provided on a surface of a semiconductor substrate, a source region (1) of a first conductivity type, a channel region (10) of the first conductivity type that adjoins the source region, a confining region (5) of the second conductivity type that adjoins the gate region and confines the channel region, a drain region (3) of the first conductivity type provided on a reverse face, and a drift region (4) of the first conductivity type that continuously lies in a direction of thickness of the substrate from a channel to a drain.
    Type: Grant
    Filed: September 11, 2000
    Date of Patent: March 22, 2005
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Shin Harada, Kenichi Hirotsu, Hiroyuki Matsunami, Tsunenobu Kimoto
  • Patent number: 6855981
    Abstract: A silicon carbide power device includes a junction field effect transistor and a protective diode, which is a Zener or PN junction diode. The PN junction of the protective diode has a breakdown voltage lower than the PN junction of the transistor. Another silicon carbide power device includes a protective diode, which is a Schottky diode. The Schottky diode has a breakdown voltage lower than the PN junction of the transistor by adjusting Schottky barrier height or the depletion layer formed in the semiconductor included in the Schottky diode. Another silicon carbide power device includes three protective diodes, which are Zener diodes. Two of the protective diodes are used to clamp the voltages applied to the gate and the drain of the transistor due to surge energy and used to release the surge energy. The last diode is a thermo-sensitive diode, with which the temperature of the JFET is measured.
    Type: Grant
    Filed: August 29, 2002
    Date of Patent: February 15, 2005
    Assignee: Denso Corporation
    Inventors: Rajesh Kumar, Hiroki Nakamura, Tsuyoshi Yamamoto, Toshiyuki Morishita
  • Patent number: 6831317
    Abstract: A method and apparatus for providing a meshed power and signal bus system on an array type integrated circuit that minimizes the size of the circuit. In a departure from the art, through-holes for the mesh system are placed in the cell array, as well as the peripheral circuits. The power and signal buses of the mesh system run in both vertical and horizontal directions across the array such that all the vertical buses lie in one metal layer, and all the horizontal buses lie in another metal layer. The buses of one layer are connected to the appropriate bus(es) of the other layer using through-holes located in the array. Once connected, the buses extend to the appropriate sense amplifier drivers. The method and apparatus are facilitated by an improved subdecoder circuit implementing a hierarchical word line structure.
    Type: Grant
    Filed: December 10, 2002
    Date of Patent: December 14, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Goro Kitsukawa, Takesada Akiba, Hiroshi Otori, William R. McKee, Jeffrey E. Koelling, Troy H. Herndon
  • Patent number: 6828609
    Abstract: A semiconductor component having a semiconductor body comprises a blocking pn junction, a source zone of a first conductivity type and bordering on a zone forming the blocking pn junction of a second conductivity type complementary to the first conductivity type, and a drain zone of the first conductivity type. The side of the zone of the second conductivity type faces the drain zone forming a first surface, and in the region between the first surface and a second surface areas of the first and second conductivity type are nested in one another. The areas of the first and second conductivity type are variably so doped that near the first surface doping atoms of the second conductivity type predominate, and near the second surface doping atoms of the first conductivity type predominate. Furthermore a plurality of floating zones of the first and second conductivity type is provided.
    Type: Grant
    Filed: June 6, 2003
    Date of Patent: December 7, 2004
    Assignee: Infineon Technologies AG
    Inventors: Gerald Deboy, Dirk Ahlers, Helmut Strack, Michael Rueb, Hans Martin Weber
  • Patent number: 6825514
    Abstract: A process for manufacturing of a semiconductor device comprising a blocking pn junction, a source zone of a first conductivity type connected to a first electrode and bordering on a zone forming the blocking pn junction of a second conductivity type complementary to the first conductivity type, and a drain zone of the first conductivity type connected to a second electrode, the side of the zone of the second conductivity type facing the drain zone forming a first surface, and in the region between the first surface and a second surface located between the first surface and the drain zone, areas of the first and second conductivity type nested in one another, comprises the step of: varying in individual semiconductor layers, by doping, the degree of compensation in the regions of the second conductivity type.
    Type: Grant
    Filed: June 6, 2003
    Date of Patent: November 30, 2004
    Assignee: Infineon Technologies AG
    Inventors: Gerald Deboy, Dirk Ahlers, Helmut Strack, Michael Rueb, Hans Martin Weber
  • Patent number: 6815742
    Abstract: A method and apparatus for providing a meshed power and signal bus system on an array type integrated circuit that minimizes the size of the circuit. In a departure from the art, through-holes for the mesh system are placed in the cell array, as well as the peripheral circuits. The power and signal buses of the mesh system run in both vertical and horizontal directions across the array such that all the vertical buses lie in one metal layer, and all the horizontal buses lie in another metal layer. The buses of one layer are connected to the appropriate bus(es) of the other layer using through-holes located in the array. Once connected, the buses extend to the appropriate sense amplifier drivers. The method and apparatus are facilitated by an improved subdecoder circuit implementing a hierarchical word line structure.
    Type: Grant
    Filed: December 5, 2003
    Date of Patent: November 9, 2004
    Assignees: Hitachi, Ltd., Texas Instruments Incorporated
    Inventors: Goro Kitsukawa, Takesada Akiba, Hiroshi Otori, William R. McKee, Jeffrey E. Koelling, Troy H. Herndon
  • Patent number: 6815794
    Abstract: Semiconductor devices with a multiple isolation structure and methods for fabricating the same are provided. In one aspect, a semiconductor device comprises a heavily doped buried layer having a first conductivity type, which is formed in a predetermined region of a semiconductor substrate, and an epitaxial layer having the first conductivity type, which covers an entire surface of the semiconductor substrate. A device isolation structure is disposed such that the device isolation structure penetrates the epitaxial layer and a portion of the semiconductor substrate to define a device region. The device isolation structure includes an upper isolation structure penetrating an epitaxial layer as well as a lower isolation structure formed in the semiconductor substrate under the upper isolation structure.
    Type: Grant
    Filed: February 25, 2003
    Date of Patent: November 9, 2004
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hwa-Sook Shin, Kwang-Dong Yoo
  • Patent number: 6800887
    Abstract: Known techniques to improve metal-oxide-semiconductor field effect transistor (MOSFET) performance is to add a high stress dielectric layer to the MOSFET. The high stress dielectric layer introduces stress in the MOSFET that causes electron mobility drive current to increase. This technique increases process complexity, however, and can degrade PMOS performance. Embodiments of the present invention create dislocation loops in the MOSFET substrate to introduce stress and implants nitrogen in the substrate to control the growth of the dislocation loops so that the stress remains beneath the channel of the MOSFET.
    Type: Grant
    Filed: March 31, 2003
    Date of Patent: October 5, 2004
    Assignee: Intel Corporation
    Inventors: Cory E. Weber, Mark Armstrong, Harold Kennel, Tahir Ghani, Paul A. Packan, Scott Thompson
  • Publication number: 20040178443
    Abstract: A structure for making a LDMOS transistor (100) includes an interdigitated source finger (26) and a drain finger (21) on a substrate (15). Termination regions (35, 37) are formed at the tips of the source finger and drain finger. A drain (45) of a second conductivity type is formed in the substrate of a first conductivity type. A field reduction region (7) of a second conductivity type is formed in the drain and is wrapped around the termination regions for controlling the depletion at the tip and providing higher voltage breakdown of the transistor.
    Type: Application
    Filed: March 10, 2003
    Publication date: September 16, 2004
    Applicant: Semiconductor Components Industries, LLC.
    Inventors: Zia Hossain, Mohamed Imam, Joe Fulton
  • Patent number: 6784505
    Abstract: Merging together the drift regions in a low-power trench MOSFET device via a dopant implant through the bottom of the trench permits use of a very small cell pitch, resulting in a very high channel density and a uniformly doped channel and a consequent significant reduction in the channel resistance. By properly choosing the implant dose and the annealing parameters of the drift region, the channel length of the device can be closely controlled, and the channel doping may be made highly uniform. In comparison with a conventional device, the threshold voltage is reduced, the channel resistance is lowered, and the drift region on-resistance is also lowered. Implementing the merged drift regions requires incorporation of a new edge termination design, so that the PN junction formed by the P epi-layer and the N+ substrate can be terminated at the edge of the die.
    Type: Grant
    Filed: May 3, 2002
    Date of Patent: August 31, 2004
    Assignee: Fairchild Semiconductor Corporation
    Inventor: Jun Zeng
  • Patent number: 6777728
    Abstract: A semiconductor device includes a channel layer, a gate electrode formed on the channel layer, a p-type source region formed on a first side of the channel layer, and a p-type drain region formed on a second side of the channel layer. A heavy-hole band and a light-hole band are separated by compressive strain applied isotropically in an in-plane direction in the channel layer. A channel direction connecting the p-type source and drain regions is set substantially to a direction to maximize hole mobility in the channel layer.
    Type: Grant
    Filed: December 27, 2002
    Date of Patent: August 17, 2004
    Assignee: Fujitsu Limited
    Inventors: Masashi Shima, Tetsuji Ueno, Yoshiki Sakuma, Shunji Nakamura
  • Patent number: 6774417
    Abstract: A protection device for integrated circuits. A complementary well is fabricated in a semiconductor substrate. An enhancement mode junction field effect transistor (JFET) is fabricated in the complementary well. An interface bonding pad is fabricated above the JFET. A source contact is also fabricated in the well. The gate and drain of the JFET are coupled to the interface bonding pad and the source of the JFET is coupled to the substrate.
    Type: Grant
    Filed: October 23, 2002
    Date of Patent: August 10, 2004
    Assignee: Lovoltech, Inc.
    Inventors: Chong Ming Lin, Ho Yuan Yu
  • Patent number: 6720615
    Abstract: A semiconductor device has a drift region in which a drift current flows if it is in the ON mode and which is depleted if it is in the OFF mode. The drift region is formed as a structure having a plurality of first conductive type divided drift regions and a plurality of second conductive type compartment regions in which each of the compartment regions is positioned among the adjacent drift regions in parallel to make p-n junctions, respectively.
    Type: Grant
    Filed: April 5, 2002
    Date of Patent: April 13, 2004
    Assignee: Fuji Electric Co., Ltd.
    Inventor: Tatsuhiko Fujihira
  • Publication number: 20040056306
    Abstract: A power semiconductor device is disclosed, which comprises a semiconductor layer including a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type, which are periodically formed in the lateral direction, and a power semiconductor element including the semiconductor layers that are formed periodically, wherein a distribution of an amount of an impurity in a vertical direction of the first semiconductor layer differs from a distribution of an amount of an impurity in the vertical direction of the second semiconductor layer.
    Type: Application
    Filed: January 15, 2003
    Publication date: March 25, 2004
    Inventors: Wataru Saito, Ichiro Omura, Kozo Kinoshita
  • Publication number: 20040036140
    Abstract: A semiconductor device including an N-type semiconductor substrate which includes arsenic as an impurity, a first electrode formed on a main surface of the N-type semiconductor substrate, a ground surface formed on another surface of the N-type semiconductor substrate, a second electrode formed on the ground surface and ohmically-contacted with the N-type semiconductor substrate, a semiconductor element formed in the N-type semiconductor substrate and flowing current between the first electrode and the second electrode during ON-state thereof. The device has a reduced ON-resistance thereof.
    Type: Application
    Filed: August 28, 2003
    Publication date: February 26, 2004
    Inventors: Yoshifumi Okabe, Masami Yamaoka, Akira Kuroyanagi
  • Patent number: 6693314
    Abstract: A junction field-effect transistor containing a semiconductor region with an inner region is described. In addition, a first and a second connecting region, respectively, are disposed within the semiconductor region. The first connecting region has the same conductivity type as the inner region, but in a higher doping concentration. The second connecting region has the opposite conductivity type to that of the inner region. This reduces the forward resistance while at the same time maintaining a high reverse voltage strength.
    Type: Grant
    Filed: June 22, 2001
    Date of Patent: February 17, 2004
    Assignee: SiCed Electronics Development GmbH & Co. KG
    Inventors: Heinz Mitlehner, Dietrich Stephani, Jenoe Tihanyi
  • Patent number: 6686616
    Abstract: SiC MESFETs are disclosed which utilize a semi-insulating SiC substrate which substantially free of deep-level dopants. Utilization of the semi-insulating substrate may reduce back-gating effects in the MESFETs. Also provided are SiC MESFETs with a two recess gate structure. MESFETS with a selectively doped p-type buffer layer are also provided. Utilization of such a buffer layer may reduce output conductance by a factor of 3 and produce a 3 db increase in power gain over SiC MESFETs with conventional p-type buffer layers. A ground contact may also be provided to the p-type buffer layer and the p-type buffer layer may be made of two p-type layers with the layer formed on the substrate having a higher dopant concentration. SiC MESFETs according to embodiments of the present invention may also utilize chromium as a Schottky gate material. Furthermore, an oxide-nitride-oxide (ONO) passivation layer may be utilized to reduce surface effects in SiC MESFETs.
    Type: Grant
    Filed: May 10, 2000
    Date of Patent: February 3, 2004
    Assignee: Cree, Inc.
    Inventors: Scott T. Allen, John W. Palmour, Terrence S. Alcorn
  • Patent number: 6677626
    Abstract: This invention achieves a high inverse voltage of a super-junction semiconductor device, which has a drift layer composed of a parallel pn layer that conducts electricity in the ON state and is depleted in the OFF state. An n− high resistance region is formed at the periphery of a drift layer composed of a parallel pn layer of n drift regions and p partition regions. The impurity density ND of the n− high resistance region is 5.62×1017×VDSS−1.36(cm−3) or less. VDSS denotes the withstand voltage (V). An n low resistance region is arranged adjacent to the n− high resistance region.
    Type: Grant
    Filed: November 10, 1999
    Date of Patent: January 13, 2004
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Youichi Shindou, Yasushi Miyasaka, Tatsuhiko Fujihira, Manabu Takei