With Multiple Channels Or Channel Segments Connected In Parallel, Or With Channel Much Wider Than Length Between Source And Drain (e.g., Power Jfet) Patents (Class 257/287)
  • Patent number: 5869856
    Abstract: Disclosed is a field effect transistor which has: an operating layer which is of a compound semiconductor; a first conductive layer which is formed as a channel layer; a second conductive layer which is formed below the first conductive layer and through which a current less than that flowing through the first conductive layer is flown; an ohmic electrode which is ohmic-junctioned with the second conductive layer; and a source electrode and a drain electrode which are junctioned with the first conductive layer; wherein the source electrode and the drain electrode are ohmic-junctioned with the ohmic electrode with a resistivity lower than the resistivity between the first conductive layer and the second conductive layer.
    Type: Grant
    Filed: December 24, 1996
    Date of Patent: February 9, 1999
    Assignee: NEC Corporation
    Inventor: Kensuke Kasahara
  • Patent number: 5861644
    Abstract: A method of improving the performance of a traveling wave field-effect transistor operated at frequencies in the microwave range or above the microwave range comprising the steps of forming a depletion region beneath a gate electrode wherein, in a plane transverse to the direction of signal propagation, a depletion region edge has a first end portion located between the gate electrode and a drain electrode and a second end portion located between the gate electrode and a source electrode; and separating the depletion region edge from the drain electrode. Further improvements in the operation of the TWFET include adjusting the first end portion of the depletion region edge to be closer to the gate electrode relative to the distance between the second end portion of the depletion region edge and the gate electrode, controlling an effective conductivity of a semiconductor of the traveling-wave field effect transistor, and setting the length of the gate electode at about one micron.
    Type: Grant
    Filed: May 5, 1997
    Date of Patent: January 19, 1999
    Inventor: Alison Schary
  • Patent number: 5850099
    Abstract: Generally, and in one form of the invention, a method for fabricating a transistor having a plurality of active regions comprising spacing or shaping the emitters 20 and 22, or gates, in a non-uniform manner to provide a substantially constant temperature over an active region of the transistor is disclosed. An advantage of the invention is that the occurrence of a thermal runaway condition between transistor current and temperature is generally avoided.
    Type: Grant
    Filed: November 12, 1993
    Date of Patent: December 15, 1998
    Assignee: Texas Instruments Incorporated
    Inventor: William Uei-Chung Liu
  • Patent number: 5793072
    Abstract: A thin film transistor having two vertically stacked channels and dual gate non-photosensitive structure, where the source drain to bottom gate structure is self-aligned. This structure occupies the same area on a substrate as a conventional single gate thin film transistor. This invention also discloses a process for manufacturing a dual gate structure with a simple three mask procedure.
    Type: Grant
    Filed: August 9, 1996
    Date of Patent: August 11, 1998
    Assignee: International Business Machines Corporation
    Inventor: Yue Kuo
  • Patent number: 5789771
    Abstract: The invention relates to the structure of the camel-gate field-effect transistor with multiple modulation-doped channels. The device structure, from the bottom to the top in succession, includes the substrate, the buffer layer, the multiple modulation-doped channels, the thin and complete depletion layer, and the ohmic contact layer. The transistor is characterized by a camel-gate diode, which is composed of the multiple modulation-doped channels, the thin and complete depletion layer and the ohmic contact layer. The gate structure may achieve the high potential height between the gate electrode and the source electrode as well as the high breakdown voltage performance. Furthermore, the use of multiple modulation-doped channels, made of n-type GaAs materials with different thickness and doped concentration, can exhibit excellent properties of high output current, large and linear transconductances.
    Type: Grant
    Filed: December 11, 1996
    Date of Patent: August 4, 1998
    Assignee: National Science Council of Republic of China
    Inventors: Wen-Chau Liu, Wen-Shiung Lour, Jung-Hui Tsai
  • Patent number: 5789791
    Abstract: The gate resistance of a high-frequency multi-finger MOS transistor is reduced by shorting together the ends of each of the gates by utilizing gate contacts, metal regions, vias, and a metal layer. Alternately, the gate resistance is reduced by utilizing a metal line that shorts all of the gate contacts together, and overlies each of the gates. By reducing the gate resistance, the maximum frequency f.sub.MAX of the multi-finger transistor can be increased.
    Type: Grant
    Filed: November 15, 1996
    Date of Patent: August 4, 1998
    Assignee: National Semiconductor Corporation
    Inventor: Albert M. Bergemont
  • Patent number: 5773891
    Abstract: In a sub-micron line width process, a first layer of polysilicon 13 is patterned into lines 1,2 spaced a predetermined distance. An oxide layer 11 is deposited. A second layer of polysilicon 14 is deposited on the insulating layer. A gate contact 19 or emitter contact 35 is formed from the second polysilicon layer 14. The gate 19 or emitter 35 is spaced from the lines 1,2 a distance approximately equal to the thickness of the second polysilicon layer 14.
    Type: Grant
    Filed: June 5, 1995
    Date of Patent: June 30, 1998
    Assignee: Harris Corporation
    Inventors: Jose Avelino Delgado, Stephen Joseph Gaul
  • Patent number: 5751033
    Abstract: A frequency converter has low noise figure and high conversion gain characteristics, and can drive directly a 50 Ohm load. In one embodiment, a dual-gate FET is employed that is composed of a first and second FET as the frequency mixing elements, and a third FET is connected in parallel to the first. The gate voltage of the first FET is set to be substantially equal to the pinch-off voltage in order to thereby ensure low noise figure. The second FET is set to a high g.sub.m, from which a frequency-converted signal is outputted. The gate bias of the third FET is set to provide a path for the current flowing through the second FET. As a result, the second FET can be set to a high g.sub.m regardless of the gate voltage of the first FET, in order to ensure high conversion gain.
    Type: Grant
    Filed: July 8, 1996
    Date of Patent: May 12, 1998
    Assignee: NEC Corporation
    Inventor: Tatsuya Miya
  • Patent number: 5734189
    Abstract: An FET device is disclosed of the type typically fabricated on a substrate and including an active FET region, an input port, an output port, a common connection and via ground connections for coupling the common connection to a ground. The improvement includes the via connections being disposed on an outer periphery that bounds the active FET region which reduces the distance between the common connection and ground, and thereby reduces the associated common lead inductance.
    Type: Grant
    Filed: December 9, 1996
    Date of Patent: March 31, 1998
    Assignee: ITT Industries, Inc.
    Inventor: William Leland Pribble
  • Patent number: 5726469
    Abstract: A surface voltage sustaining structure around an n.sup.+ (or p.sup.+)-type region on a p.sup.- (or n.sup.-)-type substrate for high-voltage devices is made by a combination of n-type regions and/or p-type regions and produces an effective surface density of donor (or acceptor) decreasing with the distance to the n.sup.+ (or p.sup.+)-type region on the surface, when all of the regions are depleted under reverse breakdown voltage. The surface voltage sustaining structure can make the breakdown voltage of the n.sup.+ -p.sup.- (or p.sup.+ -n.sup.-)-junction reach more than 90% of that one-sided parallel plane junction with the same substrate doping concentration. High-voltage vertical devices as well as high-voltage lateral devices with fast response, low on-voltage and high current density can be made by using this invention.
    Type: Grant
    Filed: July 19, 1995
    Date of Patent: March 10, 1998
    Assignee: University of Elec. Sci. & Tech. of China
    Inventor: Xingbi Chen
  • Patent number: 5672890
    Abstract: It is an object of the present invention to provide a structure of a field effect transistor, which effectively suppresses a leakage current from a source/drain region to a substrate side without increasing a parasitic capacitance, and a method of manufacturing the same.
    Type: Grant
    Filed: September 12, 1995
    Date of Patent: September 30, 1997
    Assignee: Sumitomo Electric Industries
    Inventor: Shigeru Nakajima
  • Patent number: 5644146
    Abstract: A thin film transistor comprises a dielectric substrate (1), a semiconductor layer (3) of poly-crystalline silicon layer having a drain region (8), an active gate region (4, 8-0), and a source region (7) placed on said substrate (1), a drain terminal (10) and a source terminal (10A) connected to said respective regions for external connection, a gate electrode (6) coupled with a part of said gate region (4) through a dielectric layer (4A), wherein length (d) of said gate electrode (6) is shorter than the length of gate region (4 plus 8-0), so that an offset region (8-0), where no gate electrode faces with said gate region, is produced.
    Type: Grant
    Filed: March 21, 1995
    Date of Patent: July 1, 1997
    Assignees: TDK Corporation, Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Michio Arai, Mitsufumi Codama, Ichiro Takayama
  • Patent number: 5616950
    Abstract: Generally, and in one form of the invention, a method for fabricating a transistor having a plurality of active regions comprising spacing or shaping the emitters 20 and 22, or gates, in a non-uniform manner to provide a substantially constant temperature over an active region of the transistor is disclosed. An advantage of the invention is that the occurrence of a thermal runaway condition between transistor current and temperature is generally avoided.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: April 1, 1997
    Assignee: Texas Instruments Incorporated
    Inventor: William U. Liu
  • Patent number: 5602405
    Abstract: A semiconductor device, by which a base in which gates are buried can be formed by the junction of semiconductor substrates to each other at a lower temperature, and a fabrication process thereof are provided. Recesses are defined in the top of an N.sup.- substrate. A P.sup.+ layer is formed on the underside of the N.sup.- substrate. P.sup.+ -Gate regions are each formed in an area ranging from the bottom to lower side portions of the recesses. A metal layer composed of an Au-Sb alloy is formed on the underside of the N.sup.+ substrate. The N.sup.- substrate and the N.sup.+ substrate are subjected to a treatment for removing impurities thereon with an aqueous solution of sulfuric acid and hydrogen peroxide, washed with purified water and dried by a spin dryer. The N.sup.- substrate and the N.sup.+ substrate are heated at about 350.degree. C.
    Type: Grant
    Filed: June 6, 1995
    Date of Patent: February 11, 1997
    Assignee: NGK Insulators, Ltd.
    Inventor: Yoshio Terasawa
  • Patent number: 5561305
    Abstract: A method and apparatus for finding internal charge flow distribution in a dual-channel field effect semiconductor device having at least two source terminals, two drain terminals, a control gate and two isolation gates. Electrical energy of different frequencies is applied to different ones of the source terminals for causing currents to flow in each of the channels between the source and drain terminals. Using the isolation gates to achieve channel pinch off, one of the drain terminals and one of the source terminals are selectively coupled to only one of the channels. A control signal is applied to the control gate for controlling the amount of the electrical energy conducting in each of the channels. Data is collected by measuring currents at the different frequencies at each of the drain terminals while a magnetic field perpendicular to the plane of the channels is varied.
    Type: Grant
    Filed: February 16, 1994
    Date of Patent: October 1, 1996
    Assignee: The United States of America as represented by the Secretary of the Army
    Inventor: Doran D. Smith
  • Patent number: 5541424
    Abstract: An electronic component especially a p-channel or n-channel permeable base transistor (PBT) is provided as a plurality of layers, fabricated in a laminated composite, and with at least one laterally structured layer provided for controlling a space charge zone, especially a base of the electronic component.
    Type: Grant
    Filed: July 23, 1994
    Date of Patent: July 30, 1996
    Assignee: Forschungszentrum Julich GmbH
    Inventor: Jurgen Graber
  • Patent number: 5532505
    Abstract: This invention aims at providing an high output FET having a planar type-gate structure suitable for integration, and a structure that suppresses long gate effect. A heavily doped thin channel layer 13 is formed on a semiconductor substrate 11, and a cap layer including a doped layer 15 is formed on the channel layer 13. A thickness and a dopant concentration of the doped layer 15 are so set that the doped layer 15 per se is depleted by a surface depletion region resulting from an interface level of the semiconductor substrate surface, and the surface depletion region does not widen to the channel layer 13. Consequently no long gate effect takes place on the side where a gate bias is lower.
    Type: Grant
    Filed: November 10, 1993
    Date of Patent: July 2, 1996
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Nobuhiro Kuwata
  • Patent number: 5497015
    Abstract: A semiconductor device using interference effects of electron waves passing through a multichannel, wherein the multichannel is formed by a Dirac-delta-doped layer. A method of manufacturing a semiconductor device comprising the steps of: selectively forming a region of a predetermined crystallographic orientation onto a semiconductor substrate; and alternately growing the first semiconductor layer and the second semiconductor layer whose electron affinity is smaller than that of the first semiconductor layer onto the region of the predetermined crystallographic orientation by a vapor-phase growth method so as to have a convex shape in a manner such that an area of an upper layer is smaller. A semiconductor device in which a channel portion comprising a zigzag fine line is provided between a source and a drain.
    Type: Grant
    Filed: November 13, 1989
    Date of Patent: March 5, 1996
    Assignee: Sony Corporation
    Inventors: Akira Ishibashi, Kenji Funato, Yoshifumi Mori
  • Patent number: 5493136
    Abstract: This invention provides a high-speed FET with a sufficiently high output current, and an FET having a high mobility of channel electrons and a high electron saturation rate. For this purpose, in this invention, a buffer layer, a first channel layer, a first spacer layer, a second channel layer, a second spacer layer, a third channel layer, and a capping layer are sequentially epitaxially grown on a semi-insulating GaAs semiconductor substrate. Drain and source regions are formed, and a gate electrode is formed to Schottky-contact the capping layer. Drain and source electrodes are formed to ohmic-contact the drain and source regions. Extension of a surface depletion layer from the substrate surface to a deep portion is prevented by the third channel layer closest to the substrate surface. For this reason, a sufficient quantity of electrons for forming a current channel are assured by the second and first channel layers.
    Type: Grant
    Filed: February 17, 1994
    Date of Patent: February 20, 1996
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Ken-ichiro Matsuzaki, Shigeru Nakajima, Nobuhiro Kuwata, Kenji Otobe, Nobuo Shiga, Ken-ichi Yoshida
  • Patent number: 5473181
    Abstract: In an integrated circuit arrangement having at least one power component and low-voltage components, the at least one power component is realized in a semiconductor substrate. At least one contact of the power component is arranged on a principal surface of the substrate. The contact is covered with an insulation layer at a surface of which at least one thin-film component, particularly a thin-film transistor, is provided above the contact.
    Type: Grant
    Filed: September 29, 1994
    Date of Patent: December 5, 1995
    Assignee: Siemens Aktiengesellschaft
    Inventors: Udo Schwalke, Michael Stoisiek
  • Patent number: 5459343
    Abstract: A semiconductor device which includes a channel region of predetermined conductivity type having a pair of opposing surfaces (11 or 33) , a control element of opposite conductivity type disposed on one of the opposing surfaces (13 or 31) and a pair of spaced apart electrodes (17, 19 or 35, 37) disposed over the other of the opposing surfaces. The control element and channel region form a pn junction therebetween. An electrically insulating layer (15) can be disposed between the spaced apart electrodes (17, 19) and the channel region (11) in a high frequency embodiment.
    Type: Grant
    Filed: March 4, 1994
    Date of Patent: October 17, 1995
    Assignee: Texas Instruments Incorporated
    Inventors: David J. Seymour, Frank J. Morris
  • Patent number: 5446296
    Abstract: In this MESFET, an undoped AlInAs layer 120, an undoped InP layer 130, an n-InGaAs layer 140, an undoped InP layer 150, and an AlInAs layer 160 are formed on a semi-insulating InP substrate 110. A source electrode 410, a drain electrode 430, and a gate electrode 420 are formed on the AlInAs layer 160. The source electrode 410 and the drain electrode 430 are in ohmic contact with the AlInAs layer 160, and the gate electrode 420 forms a Schottky junction with the AlInAs layer 160.
    Type: Grant
    Filed: February 3, 1995
    Date of Patent: August 29, 1995
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Shigeru Nakajima
  • Patent number: 5428234
    Abstract: A semiconductor device which comprises a semiconductor substrate having thereon a channel region, said channel region comprising (A) a channel, and (B) a metallic layer or a compound layer of a metal with a constituent material of the semiconductor substrate, provided that at least a part of said metallic layer or said compound layer is included in said channel. The semiconductor device has stable characteristics with high operation speed, and yet, is capable of being fabricated by a simple process.
    Type: Grant
    Filed: September 16, 1994
    Date of Patent: June 27, 1995
    Assignee: Sony Corporation
    Inventor: Hirofumi Sumi
  • Patent number: 5391895
    Abstract: A double diamond mesa vertical field effect transistor includes a diamond layer, a first diamond mesa on a diamond layer, and a second diamond mesa on the first diamond mesa, opposite the diamond layer. A source contact is formed on the second diamond mesa, opposite the first diamond mesa, and a gate is formed on the first diamond mesa opposite the diamond layer. The drain contact may be formed on the diamond layer adjacent the first diamond mesa, or the diamond layer itself may be formed on a nondiamond substrate and a drain contact may be provided on the nondiamond substrate. An integrated array of field effect transistors may be formed, including a plurality of second mesas on the first mesa, with a plurality of gates formed on the first mesa between the second mesas and a source formed on each second mesa, opposite the first mesa. The second mesas may also extend over the multiple gate contacts on the first mesa to form a common source region with a common source contact.
    Type: Grant
    Filed: September 21, 1992
    Date of Patent: February 21, 1995
    Assignee: Kobe Steel USA, Inc.
    Inventor: David L. Dreifus
  • Patent number: 5376812
    Abstract: A method for producing a Schottky barrier gate type field effect transistor includes producing a low concentration active region at a desired position of a semi-insulating compound semiconductor substrate and producing a gate electrode comprising refractory metal on the active region, producing a first insulating film and etching the same thereby to produce first side wall assist films comprising the first insulating film at both side walls of the gate electrode, removing one of the first side wall assist films at the side where a source electrode is to be produced, depositing a second insulating film to the thickness less than that of the first insulating film, etching the second insulating film thereby to produce a second side wall assist film having narrower width than that of the first side wall assist film at the side wall of the gate electrode where the source electrode is to be produced, and conducting ion implantation using the first and second side wall assist films and the gate electrode as a mask t
    Type: Grant
    Filed: December 20, 1989
    Date of Patent: December 27, 1994
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Tomoki Oku
  • Patent number: 5359214
    Abstract: A field effect transistor device constructed in accordance with the present invention includes a channel of semiconductive material such as silicon having at least one row of pores extending therethrough. Internal pn junctions are fabricated within the porous region, such that the inside of each pore is coated with a layer of opposite conductivity type semiconductive material. When voltage is applied to the internal pn-junctions, the space charge around the pores widens or contracts, depending upon the direction of the bias, thereby permitting the modulation of current flow through the channel.
    Type: Grant
    Filed: June 2, 1993
    Date of Patent: October 25, 1994
    Assignee: Kulite Semiconductor Products
    Inventors: Anthony D. Kurtz, Joseph S. Shor, Alexander A. Ned
  • Patent number: 5323036
    Abstract: In a power FET composed of a substrate having upper and lower surfaces, the FET providing a current flow path between the upper and lower surfaces, and the FET having a plurality of drain regions extending to the substrate upper surface and an insulated gate electrode disposed on the upper surface, the improvement wherein said drain regions are disposed in a hexagonal lattice pattern, and said gate electrode comprises: a plurality of gate segments each covering a respective drain region; and a plurality of connecting segments each connecting together three of said gate segments.
    Type: Grant
    Filed: January 21, 1992
    Date of Patent: June 21, 1994
    Assignee: Harris Corporation
    Inventors: John M. S. Neilson, Frederick P. Jones, Joseph A. Yedinak, Christopher L. Rexer
  • Patent number: 5317176
    Abstract: A power transistor has a plurality of contacted, individual transistors. The contacts of these individual transistors are arranged at such intervals from one another that a temperature distribution results during operation that is substantially uniform for an intended power range of the transistor.
    Type: Grant
    Filed: March 3, 1993
    Date of Patent: May 31, 1994
    Assignee: Siemens Aktiengesellschaft
    Inventors: Ulrich Schaper, Birgit Holzapfl
  • Patent number: 5317175
    Abstract: P channel MOSFET and N channel MOSFET are formed in a (011) orientated semiconductor surface in such a manner that the channel of the P channel MOSFET is perpendicular to the channel of the N channel MOSFET. This arrangement can reduce a total channel resistance. The P channel MOSFET is formed so that the channel is parallel to the <011> direction, for example, and the N channel MOSFET is formed so that the channel is perpendicular to the <011> direction.
    Type: Grant
    Filed: January 29, 1992
    Date of Patent: May 31, 1994
    Assignee: Nissan Motor Co., Ltd.
    Inventor: Kraisorn Throngnumchai
  • Patent number: 5309006
    Abstract: An FET crossbar switch device is implemented by using a split gate electrode and a shared source and drain pad to implement source and drain electrodes on an integrated circuit substrate. First and second inputs to the device are associated with first and second transmission lines, each of which is directly connected to a first and second source electrode areas. Disposed between the source electrode areas are respective drain electrode sections, each of which is coupled to an associated output transmission line. The input and output transmission lines are fabricated directly on the integrated circuit substrate. Gate fingers or electrodes are directed between respective drain electrodes and adjacent source electrodes. By properly biasing the gate electrodes, one can direct the first input to the first output with the second input directed to the second output. In a second state the first input can be connected to the second output with the second input disconnected or connected to the first output.
    Type: Grant
    Filed: November 5, 1991
    Date of Patent: May 3, 1994
    Assignee: ITT Corporation
    Inventors: David A. Willems, Victor E. Steel
  • Patent number: 5285090
    Abstract: Electrical ohmic contacts are made to a matrix of silicon having conductive rods embedded therein without making contact to any of the rods. Those rods which extend to the surface in the selected area of the matrix to be contacted are etched to form holes. The holes are filled with insulating polycrystalline silicon. The region of the selected area is heavily doped, and an ohmic contact member is made thereto. The underlying rods are spaced from the ohmic contact member and the heavily-doped region by intervening polycrystalline silicon.
    Type: Grant
    Filed: February 6, 1992
    Date of Patent: February 8, 1994
    Assignee: GTE Laboratories Incorporated
    Inventors: Brian M. Ditchek, Marvin Tabasky
  • Patent number: 5270554
    Abstract: A high power, high frequency, metal-semiconductor field-effect transistor comprises a bulk single crystal silicon carbide substrate, an optional first epitaxial layer of p-type conductivity silicon carbide formed upon the substrate, and a second epitaxial layer of n-type conductivity silicon carbide formed upon the first epitaxial layer. The second epitaxial layer has two separate well regions therein that are respectively defined by higher carrier concentrations of n-type dopant ions than are present in the remainder of the second epitaxial layer. Ohmic contacts are positioned upon the wells for respectively defining one of the well regions as the source and the other as the drain. A Schottky metal contact is positioned upon a portion of the second epitaxial layer that is between the ohmic contacts and thereby between the source and drain for forming an active channel in the second epitaxial layer when a bias is applied to the Schottky contact.
    Type: Grant
    Filed: June 14, 1991
    Date of Patent: December 14, 1993
    Assignee: Cree Research, Inc.
    Inventor: John W. Palmour
  • Patent number: 5258638
    Abstract: A layout of a MOSFET current driver is disclosed which improves the fabrication yield and the current drive capability over that of the prior art while keeping the layout area the same as the prior art. In this design, the gate is laid out to have a lateral serpentine pattern rather than a vertical serpentine pattern to create a larger gate in order to improve the current drive capability. In addition, the contacts for the drain and the contacts for the source are removed from the gate layout area which facilitates condensing the gate layout and increasing the size of the gate. Also, this design has only two metal strips: one for the drain and one for the source of the MOSFET current driver. The two metal strips substantially overlap the serpentine patterned gate. Having only two metal strips reduces the spaces between the metal strips to one space thereby reducing the probability of having a short or a defect and improving the fabrication yield.
    Type: Grant
    Filed: August 13, 1992
    Date of Patent: November 2, 1993
    Assignee: Xerox Corporation
    Inventors: Abdul M. Elhatem, Steven A. Buhler
  • Patent number: 5254863
    Abstract: A semiconductor device is formed by a semiconductor body (1) having a substrate (2) on which is provided a channel-defining region (10) extending between input and output regions (20) and (21). The channel-defining region (10) has a channel layer (11) forming a heterojunction (12) with at least one barrier layer (13) to form within the channel layer (11) a two-dimensional free charge carrier gas (14) of one conductivity type for providing a conduction channel (14) controllable by a gate electrode (25). A potential well region (30) is provided between the substrate (2) and the channel-defining region (10).
    Type: Grant
    Filed: October 15, 1991
    Date of Patent: October 19, 1993
    Assignee: U.S. Philips Corp.
    Inventor: Stephen J. Battersby
  • Patent number: 5227653
    Abstract: A lateral trench-gate bipolar transistor device includes spaced-apart, surface-adjoining, laterally-oriented anode and cathode regions. A channel region at least partially surrounds the cathode region, and a gate region is provided adjacent to, but insulated from, the cathode region and the channel region. The gate region extends in a substantially vertical direction adjacent the cathode region and the channel region in order to induce a substantially vertical conduction channel in the channel region of the lateral device during operation. The gate region can advantageously be provided in a trench surrounding the transistor device, with a trench-shaped gate dielectric layer being provided on the trench sidewalls and floor to insulate the gate from the remainder of the device. Devices may be fabricated in an epitaxial surface layer, which may be provided either directly on a semiconductor substrate, or else on an intervening insulating layer.
    Type: Grant
    Filed: August 7, 1991
    Date of Patent: July 13, 1993
    Assignee: North American Philips Corp.
    Inventor: Johnny K. O. Sin
  • Patent number: 5216275
    Abstract: A semiconductor power device wherein the reverse voltage across the p.sup.+ -regions(s) and the n.sup.+ -regions(s) is sustained by a composite buffer layer, shortly as CB-layer. The CB-layer contains two kinds of semiconductor regions with opposite types of conduction. These two kinds of regions are alternatively arranged, viewed from any cross-section parallel to the interface between the layer itself and the n.sup.+ (or p.sup.+)-region. Whereas the hitherto-used voltage sustaining layer contains only one kind of semiconductor with single type of conduction in the same sectional view. Design guidelines are also provided in this invention. The relation between the on-resistance in unit area Ron and the breakdown voltage V.sub.B of the CB-layer invented is Ron ocV.sub.B.sup.113 which represents a breakthrough to the conventional voltage sustaining layer, whereas the other performances of the power devices remain almost unchanged.
    Type: Grant
    Filed: September 17, 1991
    Date of Patent: June 1, 1993
    Assignee: University of Electronic Science and Technology of China
    Inventor: Xingbi Chen
  • Patent number: 5206531
    Abstract: A semiconductor device is provided of the type having a doped semiconductor region coupled to source and drain electrodes and an elongated control gate contacting the doped region along the length of the gate for forming a nonconducting depletion region across the doped region for preventing current flow therethrough with the gate having a minimized width to reduce contact area with the doped region, wherein the width of the gate is repeatedly reduced along the length thereof for further reducing contact area with the doped semiconductor region.
    Type: Grant
    Filed: March 19, 1991
    Date of Patent: April 27, 1993
    Assignee: Lockheed Sanders, Inc.
    Inventor: Niru V. Dandekar
  • Patent number: 5185534
    Abstract: At least two unit transistor groups, each including unit transistors arranged along a straight line, are disposed on a substrate parallel to and facing each other. Each transistor in one group and a facing transistor in the other group have integral first, second, and control electrodes. The first, second, and control electrodes of the unit transistors are connected to associated respective electrode pads.
    Type: Grant
    Filed: June 3, 1991
    Date of Patent: February 9, 1993
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Shinichi Sakamoto, Takuji Sonoda, Nobuyuki Kasai
  • Patent number: 5160984
    Abstract: In an amplifying feedback-type FET semiconductor element for use as a wide-band microwave amplifier in telecommunications system such as a radar, a monolithic IC feedback circuit is located between at least two parallel FET cells of an FET semiconductor element and also between gate and drain lead electrodes of the FET semiconductor element. The feedback circuit includes at least two connecting lines and at least one passive element and is connected to the two lead electrodes. With this arrangement, it is possible to reduce the total length of said connecting lines to a minimum, thus guaranteeing a frequency characteristic showing a flat gain over a wide band.
    Type: Grant
    Filed: July 19, 1991
    Date of Patent: November 3, 1992
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Mitsuru Mochizuki, Tadashi Takagi, Shuji Urasaki