Abstract: A transistor array for semiconductor memory devices is provided. A plurality of semiconductor pillars extending outwardly from a bulk section of a semiconductor substrate is arranged in rows and columns. Each pillar forms an active area of a vertical channel access transistor. Insulating trenches are formed between the rows of pillars. Buried word lines extend within the insulating trenches along the rows of pillars. Bit line trenches are formed between columns of pillars. Bit lines extend perpendicular to the word lines in lower portions of the bit line trenches. A first and a second column of pillars face adjacent each bit line. Each bit line is coupled to the active areas in the pillars of the first column of pillars via a single sided bit line contact formed from polycrystalline silicon and is insulated from the active areas of the pillars of the second column of pillars.

Abstract: A semiconductor device having a vertical channel capable of reducing the interface contact resistance between a gate electrode surrounding an active pillar and a word line connecting the gate electrode and a method of manufacturing the same is provided. The semiconductor device includes a plurality of active pillars extending in a direction perpendicular to a surface of a semiconductor substrate. A word line structure is formed on an outer periphery for connecting the active pillars disposed in the same row or column. Top and bottom source/drain regions are formed over and under the active pillars, respectively, in relation to the word line structure.

Abstract: The invention includes a semiconductor structure having U-shaped transistors formed by etching a semiconductor substrate. In an embodiment, the source/drain regions of the transistors are provided at the tops of pairs of pillars defined by crossing trenches in the substrate. One pillar is connected to the other pillar in the pair by a ridge that extends above the surrounding trenches. The ridge and lower portions of the pillars define U-shaped channels on opposite sides of the U-shaped structure, facing a gate structure in the trenches on those opposite sides, forming a two sided surround transistor. Optionally, the space between the pillars of a pair is also filled with gate electrode material to define a three-sided surround gate transistor. One of the source/drain regions of each pair extending to a digit line and the other extending to a memory storage device, such as a capacitor. The invention also includes methods of forming semiconductor structures.

Abstract: DRAM memory cells having a feature size of less than about 4F2 include vertical surround gate transistors that are configured to reduce any short channel effect on the reduced size memory cells. In addition, the memory cells may advantageously include reduced resistance word line contacts and reduced resistance bit line contacts, which may increase a speed of the memory device due to the reduced resistance of the word line and bit line contacts.

Abstract: A dynamic random access memory structure includes a recessed-gate transistor disposed in the substrate; a trench capacitor structure disposed in the substrate and electrically connected to a first source/drain of the recessed-gate transistor; a first conductive structure disposed on and contacting the trench capacitor structure; a stack capacitor structure disposed on and contacting the first conductive structure, wherein a bottom electrode of the trench capacitor structure and a top electrode of the stack capacitor structure are electrically connected to serve as a common electrode; and a bit line disposed above a second source/drain of the recessed-gate transistor and electrically connected to the second source/drain, wherein the top of the bit line is lower than the top of the gate conductive layer of the recessed-gate transistor.

Abstract: A method for fabricating an interconnect arrangement with increased capacitive coupling is described. A trench structure is formed in a first dielectric having a capacitor region with a first aspect ratio and an interconnect region with a second aspect ratio connected thereto. The trench structure of the interconnect region is completely filled by a first interconnect. The trench structure of the capacitor region is only partially filled by a first capacitor electrode and is completely filled by a capacitor dielectric and a second capacitor electrode. In a second dielectric formed thereon, a second interconnect with a contact via is formed, which is connected to the second capacitor electrode.

Abstract: A MOS device includes first and second source/drains spaced apart relative to one another. A channel is formed in the device between the first and second source/drains. A gate is formed in the device between the first and second source/drains and proximate the channel, the gate being electrically isolated from the first and second source/drains and the channel. The gate is configured to control a conduction of the channel as a function of a potential applied to the gate. The MOS device further includes an energy filter formed between the first source/drain and the channel. The energy filter includes an impurity band operative to control an injection of carriers from the first source/drain into the channel.

Abstract: An array of memory cells configured to store at least one bit per one F2 includes substantially vertical structures providing an electronic memory function spaced apart a distance equal to one half of a minimum pitch of the array. The structures providing the electronic memory function are configured to store more than one bit per gate. The array also includes electrical contacts to the memory cells including the substantially vertical structures. The cells can be programmed to have one of a number of charge levels trapped in the gate insulator adjacent to the first source/drain region such that the channel region has a first voltage threshold region (Vt1) and a second voltage threshold region (Vt2) and such that the programmed cell operates at reduced drain source current.

Abstract: A semiconductor structure includes a power transistor monolithically integrated with a RC snubber in a die. The power transistor includes body regions extending in a silicon region, gate electrodes insulated from the body region by a gate dielectric, source regions extending in the body regions, the source and the body regions being of opposite conductivity type, and a source interconnect contacting the source regions. The RC snubber comprises including snubber electrodes insulated from the silicon region by a snubber dielectric such that the snubber electrodes and the silicon region form a snubber capacitor having a predetermined value. The snubber electrodes are connected to the source interconnect in a manner so as to form a snubber resistor of a predetermined value between the snubber capacitor and the source interconnect. The snubber capacitor and the snubber resistor are configured to substantially dampen output ringing when the power transistor switches states.

Abstract: A semiconductor structure including a vertical metal-insulator-metal capacitor, and a method for fabricating the semiconductor structure including the vertical metal-insulator-metal capacitor, each use structural components from a dummy metal oxide semiconductor field effect transistor located and formed over an isolation region located over a semiconductor substrate. The dummy metal oxide field effect transistor may be formed simultaneously with a metal oxide semiconductor field effect transistor located over a semiconductor substrate that includes the isolation region. The metal-insulator-metal capacitor uses a gate as a capacitor plate, a uniform thickness gate spacer as a gate dielectric and a contact via as another capacitor plate. The uniform thickness gate spacer may include a conductor layer for enhanced capacitance. A mirrored metal-insulator-metal capacitor structure that uses a single contact via may also be used for enhanced capacitance.

Abstract: A nonvolatile memory device includes a semiconductor wall having an inclination angle and a gate electrode covered with the semiconductor wall. A pair of buried diffusion layers may be formed at a lower surface and upper surface formed by the semiconductor wall. A charge trap insulating layer may be sandwiched between the gate electrode and the semiconductor wall. The semiconductor wall between the buried diffusion layers may correspond to a channel of the memory device. In a method of fabricating the memory device, a pattern having a sidewall may be formed on a semiconductor substrate. A buried oxide layer may be formed at the upper surface and another buried oxide layer may be formed at the lower surface. A charge trap insulating layer may be formed at the sidewall where the buried oxide layers are formed. A gate electrode may be formed on the charge trap insulating layer. A semiconductor substrate may be formed to form a trench, so that the sidewall may be obtained.

Abstract: A method of making a pillar device includes providing an insulating layer having an opening, and selectively depositing germanium or germanium rich silicon germanium semiconductor material into the opening to form the pillar device.

Abstract: A method for fabricating a vertical channel transistor in a semiconductor device includes forming a plurality of pillars arranged in a first direction and a second direction crossing the first direction over a substrate, wherein each of the pillars includes a hard mask pattern thereon, forming a bit line region in the substrate between the pillars, forming a first sidewall insulation layer on a sidewall of each of the pillars, forming an insulation layer for filling a space between the pillars, forming a mask pattern for exposing the substrate between lines of the pillars arranged in the first direction over a resulting structure including the insulation layer, etching the insulation layer and the substrate using the mask pattern as an etch barrier to form a trench for defining a bit line in the substrate, and forming a second sidewall insulation layer over a resulting structure including the trench.

Abstract: A dynamic random access memory (DRAM) is provided. The DRAM comprises a substrate, a vertical transistor, a deep trench capacitor and a buried strap. The substrate has a trench and a deep trench located on one side of the trench thereon. The vertical transistor is disposed in the trench, a portion of which is disposed on the substrate. The deep trench capacitor is disposed in the deep trench, and comprises a bottom electrode, a capacitor dielectric layer and a top electrode. The vertical transistor comprises a gate structure disposed in the trench and above the substrate, a first doped region disposed in the substrate on sidewalls and bottom of the trench, and a second doped region disposed in the substrate on top of the trench. The buried strap is disposed in the substrate below the vertical transistor, and is adjoined to the first doped region and the top electrode.

Abstract: A semiconductor device is disclosed that improves heat dissipation by providing blind contact elements on a dielectric layer. Embodiments are disclosed which include a substrate having at least one electrode contact area accessible at a surface of the substrate and a surface adjacent the electrode contact area, a dielectric layer disposed above the surface; an intermediate oxide layer disposed above the dielectric layer, a current conducting metallization layer disposed above the intermediate oxide layer; and at least one contact element vertically extending from the dielectric layer through the intermediate oxide layer to the metallization layer above the surface adjacent the electrode contact area, the at least one contact element having a heat conductivity that is higher than that of the intermediate oxide layer.

Abstract: A P-N junction device and method of forming the same are disclosed. The P-N junction device may include a P-N diode, a PiN diode or a thyristor. The P-N junction device may have a monocrystalline or polycrystalline raised anode. In one embodiment, the P-N junction device results in a raised polycrystalline silicon germanium (SiGe) anode. In another embodiment, the P-N junction device includes a first terminal (anode) including a conductor layer positioned above an upper surface of a substrate and a remaining structure positioned in the substrate, the first terminal positioned over an opening in an isolation region; and a second terminal (cathode contact) positioned over the opening in the isolation region adjacent the first terminal. This latter embodiment reduces parasitic resistance and capacitance, and decreases the required size of a cathode implant area since the cathode contact is within the same STI opening as the anode.

Abstract: In one embodiment, a transistor fabricated on a semiconductor die is arranged into sections of elongated transistor segments. The sections are arranged in rows and columns substantially across the semiconductor die. Adjacent sections in a row or a column are oriented such that the length of the transistor segments in a first one of the adjacent sections extends in a first direction, and the length of the transistor segments in a second one of the adjacent sections extends in a second direction, the first direction being substantially orthogonal to the second direction. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure.

Abstract: Disclosed are an asymmetric recessed gate MOSFET, and a method for manufacturing the same. The asymmetric recessed gate MOSFET comprises: recess regions formed at a predetermined depth in a semiconductor; recessed gate electrodes formed at a predetermined height on a semiconductor substrate by gap-filling the recess regions, and misaligned with the recess region corresponding to one of the source/drain regions; spacers formed on sides of the recessed gate electrodes; and source/drain regions implanted with a dopant formed in the semiconductor substrate exposed between the spacers. The overlap between the gate electrodes and the source/drain regions can be reduced by having one of the source/drain regions misaligned with the recess regions in the recessed gate structure, and abnormal leakage current caused by consistency between an electron field max point A and a stress max pint B can be sharply reduced by changing the profile of the source/drain regions.

Abstract: The present invention provides a method of coupling substrates together. The method includes providing first and second substrates and then coupling the first and second substrates together. One of the first and second substrates includes devices with an interconnect region positioned thereon and the other substrate carries a device structure.

Abstract: A memory device is disclosed, comprising a substrate, and a capacitor with a specific shape along an orientation parallel to a surface of the substrate, wherein the specific shape includes a curved outer edge, a curved inner edge having a positive curvature, a first line and a second line connecting the curved outer edge with the curved inner edge. A word line is coupled to the capacitor. In an embodiment of the invention, the capacitor is a deep trench capacitor with a vertical transistor. In another embodiment of the invention, the capacitor is a stacked capacitor.

Abstract: A method for forming double-sided capacitors for a semiconductor device includes forming a dielectric structure which supports capacitor bottom plates during wafer processing. The structure is particularly useful for supporting the bottom plates during removal of a base dielectric layer to expose the outside of the bottom plates to form a double-sided capacitor. The support structure further supports the bottom plates during formation of a cell dielectric layer, a capacitor top plate, and final supporting dielectric. An inventive structure is also described.

Abstract: A method for forming an isolation layer in a semiconductor device includes forming a trench in a semiconductor substrate, forming a first liner nitride layer on an exposed surface of the trench, forming a first high density plasma (HDP) oxide layer such that the first HDP oxide layer partially fills the trench to cover a bottom surface and a side surface of the trench and an upper surface of the first liner nitride layer, etching overhangs generated during the forming of the first HDP oxide layer by introducing a hydrofluoric acid (HF) solution into the semiconductor substrate, forming a second liner nitride layer over the first HDP oxide layer, removing the second liner nitride layer formed on the first HDP oxide layer while forming a second HDP oxide layer to fill the trench, and subjecting the second HDP oxide layer to planarization, so as to form a trench isolation layer.

Abstract: It is an object of the present invention to provide a semiconductor device capable of additionally recording data at a time other than during manufacturing and preventing forgery due to rewriting and the like. Moreover, another object of the present invention is to provide an inexpensive, nonvolatile, and highly-reliable semiconductor device. A semiconductor device includes a first conductive layer, a second conductive layer, and an organic compound layer between the first conductive layer and the second conductive layer, wherein the organic compound layer can have the first conductive layer and the second conductive layer come into contact with each other when Coulomb force generated by applying potential to one or both of the first conductive layer and the second conductive layer is at or over a certain level.

Abstract: A transistor having a metal nitride layer pattern, etchant and methods of forming the same is provided. A gate insulating layer and/or a metal nitride layer may be formed on a semiconductor substrate. A mask layer may be formed on the metal nitride layer. Using the mask layer as an etching mask, an etching process may be performed on the metal nitride layer, forming the metal nitride layer pattern. An etchant, which may have an oxidizing agent, a chelate agent and/or a pH adjusting mixture, may perform the etching. The methods may reduce etching damage to a gate insulating layer under the metal nitride layer pattern during the formation of a transistor.

Abstract: A memory device comprising a vertical transistor includes a digit line that is directly coupled to the source regions of each memory cell. Because an electrical plug is not used to form a contact between the digit line and the source regions, a number of fabrication steps may be reduced and the possibility for manufacturing defects may also be reduced. In some embodiments, a memory device may include a vertical transistor having gate regions that are recessed from an upper portion of a silicon substrate. With the gate regions recessed from the silicon substrate, the gate regions are spaced further from the source/drain regions and, accordingly, cross capacitance between the gate regions and the source/drain regions may be reduced.

Abstract: A method of fabricating a semiconductor device includes forming a mask pattern over a semiconductor substrate to define a channel region. A portion of the semiconductor substrate is etched using the mask pattern as an etching mask to form a first pillar. A spacer is formed over a sidewall of the mask pattern and the first pillar. A portion of the semiconductor substrate exposed between the first pillars is etched using the spacer and the mask pattern as an etching mask to form a second pillar elongated from the first pillar. A portion of the second pillar is selectively etched to form a third pillar. The spacer and the mask pattern are removed. An impurity is implanted into an upper part of the first pillar and the semiconductor substrate between the third pillars to form a source/drain region. A surrounding gate is formed over an outside of the third pillar.

Abstract: A design structure for capacitor having a suitably large value for decoupling applications is formed in a trench defined by isolation structures such as recessed isolation or shallow trench isolation. The capacitor provides a contact area coextensive with an active area and can be reliably formed individually or in small numbers. Plate contacts are preferably made through implanted regions extending to or between dopant diffused regions forming a capacitor plate. The capacitor can be formed by a process subsequent to formation of isolation structures such that preferred soft mask processes can be used to form the isolation structures and process commonality and compatibility constraint are avoided while the capacitor forming processes can be performed in common with processing for other structures.

Abstract: A new class of high-density, vertical Fin-FET devices that exhibit low contact resistance is described. These vertical Fin-FET devices have vertical silicon “fins” (12A) that act as the transistor body. Doped source and drain regions (26A, 28A) are formed at the bottoms and tops, respectively, of the fins (12A). Gates (24A, 24B) are formed along sidewalls of the fins. Current flows vertically through the fins (12A) between the source and drain regions (26A, 28A) when an appropriate bias is applied to the gates (24A, 24B). An integrated process for forming pFET, nFET, multi-fin, single-fin, multi-gate and double-gate vertical Fin-FETs simultaneously is described.

Abstract: A semiconductor device and a method for fabricating the same are provided. The method includes: forming a contact plug passing through an inter-layer insulation layer; sequentially forming a lower electrode layer, a dielectric layer and an upper electrode layer on the inter-layer insulation layer; patterning the upper electrode layer; patterning the dielectric layer and the lower electrode layer, thereby obtaining a capacitor including an upper electrode, a patterned dielectric layer and a lower electrode; and sequentially forming a first metal interconnection line connected with the contact plug and second metal interconnection lines connected with the capacitor.

Abstract: A method for forming and the structure of a strained vertical channel of a field effect transistor, a field effect transistor and CMOS circuitry is described incorporating a drain, body and source region on a sidewall of a vertical single crystal semiconductor structure wherein a hetero-junction is formed between the source and body of the transistor, wherein the source region and channel are independently lattice strained with respect to the body region and wherein the drain region contains a carbon doped region to prevent the diffusion of dopants (boron) into the body. The invention reduces the problem of leakage current from the source region via the hetero-junction and lattice strain while independently permitting lattice strain in the channel region for increased mobility via choice of the semiconductor materials.

Abstract: The invention provides a fingered decoupling capacitor in the bulk silicon region that are formed by etching a series of minimum or sub-minimum trenches in the bulk silicon region, oxidizing these trenches, removing the oxide from at least one or more disjoint trenches, filling all the trenches with either in-situ doped polysilicon, intrinsic polysilicon that is later doped through ion implantation, or filling with a metal stud, such as tungsten and forming standard interconnects to the capacitor plates.

Abstract: A method for forming double-sided capacitors for a semiconductor device includes forming a dielectric structure which supports capacitor bottom plates during wafer processing. The structure is particularly useful for supporting the bottom plates during removal of a base dielectric layer to expose the outside of the bottom plates to form a double-sided capacitor. The support structure further supports the bottom plates during formation of a cell dielectric layer, a capacitor top plate, and final supporting dielectric. An inventive structure is also described.

Abstract: In the present invention, an npn junction is formed by circularly forming a p? type impurity region and n+ type impurity regions on a same single-crystalline substrate as a MOS transistor. Multiple npn junctions are formed apart from each other in concentric circular patterns. With this configuration, steep breakdown characteristics can be obtained, which results in good constant-voltage diode characteristics. Being formed in a manufacturing process of a MOS transistor, the present protection diode contributes to process streamlining and cost reduction. By selecting the number of npn junctions according to breakdown voltage, control of the breakdown voltage can be facilitated.

Abstract: A method of fabricating an image sensor which reduces fabricating costs through simultaneous formation of capacitor structures and contact structures may be provided. The method may include forming a lower electrode on a substrate, forming an interlayer insulating film on the substrate, the interlayer insulating film may have a capacitor hole to expose a first portion of the lower electrode.

Abstract: This semiconductor device includes a first conductivity type first semiconductor layer formed on the upper surface of a substrate, a first conductivity type second semiconductor layer formed on the first semiconductor layer, a first conductivity type third semiconductor layer formed on the second semiconductor layer, a second conductivity type fourth semiconductor layer formed on the third semiconductor layer, a first conductivity type fifth semiconductor layer formed on the fourth semiconductor layer and an electrode formed in a trench, so provided as to reach the second semiconductor layer through at least the fifth semiconductor layer, the fourth semiconductor layer and the third semiconductor layer, in contact with an insulating film, while the upper surface of the second semiconductor layer is arranged upward beyond the lower end of the electrode.

Abstract: In a first aspect, a first apparatus is provided. The first apparatus is a memory cell of a substrate that includes (1) a PFET with an orientation approximately planar to a surface of the substrate; and (2) an NFET coupled to the approximately planar PFET. An orientation of the NFET in the substrate is approximately perpendicular to the orientation of the PFET. Numerous other aspects are provided.

Abstract: A field effect transistor includes a vertical fin-shaped semiconductor active region having an upper surface and a pair of opposing sidewalls on a substrate, and an insulated gate electrode on the upper surface and opposing sidewalls of the fin-shaped active region. The insulated gate electrode includes a capping gate insulation layer having a thickness sufficient to preclude formation of an inversion-layer channel along the upper surface of the fin-shaped active region when the transistor is disposed in a forward on-state mode of operation. Related fabrication methods are also discussed.

Abstract: One embodiment relates to an integrated circuit that includes a conductive line that is arranged in a groove in a semiconductor body. An insulating material is disposed over the conductive line. This insulating material includes a first insulating layer comprising a horizontal portion, and a second insulating layer that is disposed over the first insulating layer. Other methods, devices, and systems are also disclosed.

Abstract: An integrated circuit arrangement includes an undulating capacitor in a conductive structure layer. The surface area of the capacitor is enlarged in comparison with an even capacitor. The capacitor is interlinked with dielectric regions at its top side and/or its underside, so that it can be produced by methods which may not have to be altered in comparison with conventional CMP methods.

Abstract: Methods of reducing the floating body effect in vertical transistors are disclosed. The floating body effect occurs when an active region in a pillar is cut off from the substrate by a depletion region and the accompanying electrostatic potential created. In a preferred embodiment, a word line is recessed into the substrate to tie the upper active region to the substrate. The resulting memory cells are preferably used in dynamic random access memory (DRAM) devices.

Abstract: A vertical transistor having an annular transistor body surrounding a vertical pillar, which can be made from oxide. The transistor body can be grown by a solid phase epitaxial growth process to avoid difficulties with forming sub-lithographic structures via etching processes. The body has ultra-thin dimensions and provides controlled short channel effects with reduced need for high doping levels. Buried data/bit lines are formed in an upper surface of a substrate from which the transistors extend. The transistor can be formed asymmetrically or offset with respect to the data/bit lines. The offset provides laterally asymmetric source regions of the transistors. Continuous conductive paths are provided in the data/bit lines which extend adjacent the source regions to provide better conductive characteristics of the data/bit lines, particularly for aggressively scaled processes.

Abstract: A method of manufacturing a semiconductor device includes forming a pillar-shaped active region by etching a portion of a semiconductor substrate, forming a blocking film selectively exposing a sidewall of a lower portion of the pillar-shaped active region, and forming a bit-line selectively on the exposed sidewall of the lower portion of the pillar-shaped active region.

Abstract: A recess channel transistor includes a semiconductor substrate; a trench isolation region in the semiconductor substrate, which defines an active area; a gate trench in the active area, wherein the gate trench includes a round lower portion; a recessed gate embedded in the gate trench with a spherical gate portion situated in the round lower portion; a gate oxide layer in the round lower portion between the semiconductor substrate and the spherical gate portion; a source region in the active area at one side of the recessed gate; a drain region in the active area at the other side of the recessed gate; and a channel region between the source region and the drain region, wherein the channel region presents a convex curve profile when viewed from a channel widthwise direction.

Abstract: A high density vertical merged MOS-bipolar-capacitor gain cell is realized for DRAM operation. The gain cell includes a vertical MOS transistor having a source region, a drain region, and a floating body region therebetween. The gain cell includes a vertical bi-polar transistor having an emitter region, a base region and a collector region. The base region for the vertical bi-polar transistor serves as the source region for the vertical MOS transistor. A gate opposes the floating body region and is separated therefrom by a gate oxide on a first side of the vertical MOS transistor. A floating body back gate opposes the floating body region on a second side of the vertical transistor. The base region for the vertical bi-polar transistor is coupled to a write data word line.

Abstract: A vertical IMOS-type transistor including: a stack of a first semiconductor portion doped with dopant elements of a first type, of a second substantially undoped intrinsic semiconductor portion, and of a third semiconductor portion doped with dopant elements of a second type forming a PIN-type diode; and a conductive gate placed against the stack with an interposed insulating layer.

Abstract: A semiconductor device includes: a semiconductor layer of a first conductivity type; a first semiconductor pillar region of the first conductivity type and a second semiconductor pillar region of a second conductivity type provided on the major surface; a first semiconductor region of the second conductivity type provided on the second semiconductor pillar region; a first and second main electrodes; a control electrode; a third semiconductor region of the first conductivity type provided on the major surface of the semiconductor layer and located on a terminal side of the first semiconductor pillar region and the second semiconductor pillar region; a high resistance semiconductor layer provided on the third semiconductor region; and a fourth semiconductor region of the second conductivity type provided on the high resistance semiconductor layer.

Abstract: Semiconductor structures and methods are provided for a semiconductor device (40) employing a superjunction structure (41) and overlying trench (91) with embedded control gate (48). The method comprises, forming (52-6, 52-9) interleaved first (70-1, 70-2, 70-3, 70-4, etc.) and second (74-1, 74-2, 74-3, etc.

Abstract: A digital logic storage structure includes cross coupled first and second complementary metal oxide semiconductor (CMOS) inverters formed on a semiconductor substrate, the CMOS inverters including a first storage node and a second storage node that is the logical complement of the first storage node; both of the first and second storage nodes each selectively coupled to a deep trench capacitor through a switching transistor, with the switching transistors controlled by a common capacitance switch line coupled to gate conductors thereof; wherein, in a first mode of operation, the switching transistors are rendered nonconductive so as to isolate the deep trench capacitors from the inverter storage nodes and, in a second mode of operation, the switching transistors are rendered conductive so as to couple the deep trench capacitors to their respective storage nodes, thereby providing increased resistance of the storage nodes to single event upsets (SEUs).

Abstract: A field effect transistor includes a plurality of trenches extending into a silicon layer. Each trench has upper sidewalls that fan out. Contact openings extend into the silicon layer between adjacent trenches such that each trench and an adjacent contact opening form a common upper sidewall portion. Body regions extend between adjacent trenches, and source regions extend in the body regions adjacent opposing sidewalls of each trench. The source regions have a conductivity type opposite that of the body regions.

Abstract: In one embodiment, a transistor includes a pillar of semiconductor material arranged in a racetrack-shaped layout having a substantially linear section that extends in a first lateral direction and rounded sections at each end of the substantially linear section. First and second dielectric regions are disposed on opposite sides of the pillar. First and second field plates are respectively disposed in the first and second dielectric regions. First and second gate members respectively disposed in the first and second dielectric regions are separated from the pillar by a gate oxide having a first thickness in the substantially linear section. The gate oxide being substantially thicker at the rounded sections. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure.