Parallel Interleaved Capacitor Electrode Pairs (e.g., Interdigitized) Patents (Class 257/307)
  • Patent number: 10443046
    Abstract: A method of forming a tier of an array of memory cells within an array area, the memory cells individually comprising a capacitor and an elevationally-extending transistor, the method comprising using two, and only two, sacrificial masking steps within the array area of the tier in forming the memory cells. Other methods are disclosed, as are structures independent of method of fabrication.
    Type: Grant
    Filed: January 3, 2019
    Date of Patent: October 15, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Durai Vishak Nirmal Ramaswamy
  • Patent number: 10332885
    Abstract: A capacitor includes a cell array including a plurality of cells and a fine tuning cell electrically coupled to the cell array by a first bus and a second bus. Each cell of the cell array includes a first number of fingers electrically coupled to the first and second bus, and a second number of fingers electrically coupled to the first and second bus. The fine tuning cell includes a third number of fingers electrically coupled to the first and second bus, and a fourth number of fingers electrically coupled to the first and second bus. The directional alignment of the first and second number of fingers is generally perpendicular, the directional alignment of the third and fourth number of fingers is generally perpendicular, and the second number of fingers is different than the fourth number of fingers.
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: June 25, 2019
    Assignee: XILINX, INC.
    Inventor: Jing Jing
  • Patent number: 10237507
    Abstract: An analog-to-digital converter includes a comparator having paired differential input ends, and a first capacitor and a second capacitor each provided at respective differential input ends. The first capacitor includes a plurality of first sub-capacitors that are coupled side by side with one another, and the second capacitor includes a plurality of second sub-capacitors that are coupled side by side with one another. The plurality of first sub-capacitors and the plurality of second sub-capacitors are mixedly arranged in each column of a plurality of columns.
    Type: Grant
    Filed: December 1, 2015
    Date of Patent: March 19, 2019
    Assignee: Sony Corporation
    Inventor: Masaaki Bairo
  • Patent number: 10068699
    Abstract: An inductor includes: a first coil of metal trace laid out to be symmetrical with respect to a first axis; a second coil of metal trace laid out to be substantially a mirror image of the first coil of metal trace with respect to a second axis; a first coupling capacitor configured to provide a capacitive coupling between a first segment within the first coil of metal trace and a counterpart of the first segment within the second coil of metal trace; and a second coupling capacitor configured to provide a capacitive coupling between a second segment within the first coil of metal trace and a counterpart of the second segment within the second coil of metal trace.
    Type: Grant
    Filed: March 1, 2017
    Date of Patent: September 4, 2018
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventors: Poh-Boon Leong, Chia-Liang (Leon) Lin
  • Patent number: 10002864
    Abstract: An intra-metal capacitor is provided. The intra-metal capacitor is formed in a dielectric layer and comprising a first electrode and a second electrode, wherein the first electrode penetrate through the whole thickness of the dielectric layer, and the second electrode does not penetrate through the whole thickness of the dielectric layer.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: June 19, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hsin-Hsien Chen, Sheng-Yuan Hsueh, Yi-Chung Sheng, Chih-Kai Kang, Wen-Kai Lin, Shu-Hung Yu
  • Patent number: 9818796
    Abstract: An interdigitated capacitor includes a substrate and a pair of comb-like electrodes both formed on the semiconductor substrate and horizontally arranged thereon, each of the pair of comb-like electrodes including finger electrodes having a curved profile.
    Type: Grant
    Filed: February 9, 2015
    Date of Patent: November 14, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: David W. Abraham, Jerry M. Chow
  • Patent number: 9806080
    Abstract: A semiconductor device includes a substrate, a memory structure and a capacitor structure including at least one array of capacitors. The memory structure is disposed in a first region of the device. The capacitor structure is disposed in a second region of the device. The capacitor structure may include a first capacitor array, a second capacitor array, a third capacitor array and a first landing pad. The first landing pad is disposed between the substrate and lower electrodes of capacitors of the first and second capacitor arrays, and contacts the lower electrodes so as to electrically connect the first capacitor array and the second capacitor array. Upper electrodes of capacitors of the second and third capacitor arrays are integral such that the second capacitor array and the third capacitor array are electrically connected to each other.
    Type: Grant
    Filed: June 5, 2015
    Date of Patent: October 31, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Han-Sik Yoo, Hyuk-Joon Kwon, Jung-Ha Oh, Jun-Ho Kim
  • Patent number: 9698214
    Abstract: In accordance with some embodiments of the present disclosure, a capacitor structure of an integrated circuit chip includes an insulation layer, a first electrode, and a second electrode. The insulation layer includes an insulation partition and has a first trench and a second trench separated from the first trench by the insulation partition. The first electrode is disposed in the first trench. The second electrode is disposed in the second trench. The first electrode first electrode is arranged along a spiral trajectory and surrounds a spiral channel. The second electrode is disposed within the spiral channel.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: July 4, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Nan-Chi Lu, Chen-Chieh Chiang, Chi-Cherng Jeng
  • Patent number: 9576821
    Abstract: A package includes a die, an encapsulant, and a capacitor. The package has a package first side and a package second side. The die has a die first side corresponding to the package first side, and has a die second side corresponding to the package second side. The die first side is opposite the die second side. The encapsulant surrounds the die. The capacitor includes a first plate and a second plate in the encapsulant, and opposing surfaces of the first plate and the second plate extend in a direction from the package first side to the package second side. The external conductive connectors are attached to at least one of the package first side and the package second side.
    Type: Grant
    Filed: January 13, 2014
    Date of Patent: February 21, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sut-I Lo, Ching-Wen Hsiao, Hsu-Hsien Chen, Chen-Shien Chen
  • Patent number: 9425140
    Abstract: In one embodiment, a capacitor includes a first via level having first metal bars and first vias, such that the first metal bars are coupled to a first potential node. The first metal bars are longer than the first vias. Second metal bars and second vias are disposed in a second via level, the second metal bars are coupled to the first potential node. The second metal bars are longer than the second vias. The second via level is above the first via level and the first metal bars are parallel to the second metal bars. Each of the first metal bars has a first end, an opposite second end, and a middle portion between the first and the second ends. Each of the middle portions of the first metal bars and the second ends of the first metal bars do not contact any metal line.
    Type: Grant
    Filed: November 18, 2013
    Date of Patent: August 23, 2016
    Assignee: Infineon Technologies AG
    Inventors: Sun-Oo Kim, Moosung Chae, Bum Ki Moon
  • Patent number: 9362052
    Abstract: A electronic device is provided. In one configuration, the electronic device includes a first electrode formed in a first layer; a second electrode formed in the first layer, wherein the first electrode and the second electrode are reflection symmetrically disposed; and a first floating metal ring formed in the first layer and enclosing the first electrode and the second electrode. The shape of the first electrode is the same shape as the second electrode.
    Type: Grant
    Filed: January 20, 2015
    Date of Patent: June 7, 2016
    Assignee: MEDIATEK INC.
    Inventor: YuJen Wang
  • Patent number: 9331013
    Abstract: A structure includes first, second, and third conductive leaf structures. The first conductive leaf structure includes a first conductive midrib and conductive veins. The second conductive leaf structure is electrically connected to the first conductive leaf structure, and includes a second conductive midrib, conductive veins extending toward the first conductive midrib, and conductive veins extending away from the first conductive midrib. The third conductive leaf structure includes a third conductive midrib between the first conductive midrib and the second conductive midrib, conductive veins extending toward the first conductive midrib, and conductive veins extending toward the second conductive midrib.
    Type: Grant
    Filed: May 24, 2013
    Date of Patent: May 3, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsiao-Tsung Yen, Cheng-Wei Luo, Jun-Cheng Huang, Chin-Wei Kuo, Min-Chie Jeng
  • Patent number: 9270247
    Abstract: A circuit includes a first finger capacitor having a first bus line coupled to a first plurality of finger elements and a second bus line coupled to a second plurality of finger elements. The first bus line is parallel to the second bus line. The circuit further includes an inductor having a first leg oriented perpendicular to the first bus line and the second bus line. The first leg of the inductor is coupled to a center of the first bus line.
    Type: Grant
    Filed: November 27, 2013
    Date of Patent: February 23, 2016
    Assignee: XILINX, INC.
    Inventors: Jing Jing, Shuxian Wu, Zhaoyin D. Wu
  • Patent number: 9153642
    Abstract: A particular metal-oxide-metal (MOM) capacitor device includes a conductive gate material coupled to a substrate. The MOM capacitor device further includes a first metal structure coupled to the conductive gate material. The MOM capacitor device further includes a second metal structure coupled to the substrate and proximate to the first metal structure.
    Type: Grant
    Filed: March 5, 2013
    Date of Patent: October 6, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Xia Li, Bin Yang
  • Patent number: 9029928
    Abstract: A semiconductor device includes a wafer having a frontside and a backside. The wafer is formed from at least one integrated circuit chip having an electrical connection frontside co-planar with the wafer frontside and a backside co-planar with the wafer backside. A passive component including at least one conductive plate and a dielectric plate is positioned adjacent the integrated circuit chip. An encapsulation block embeds the integrated circuit chip and the passive component, the block having a frontside co-planar with the wafer frontside and a backside co-planar with the wafer backside. An electrical connection is made between the electrical connection frontside and the passive component. That electrical connection includes connection lines placed on the wafer frontside and wafer backside. The electrical connection further includes at least one via passing through the encapsulation block.
    Type: Grant
    Filed: July 11, 2011
    Date of Patent: May 12, 2015
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventors: Laurent Marechal, Yvon Imbs, Romain Coffy
  • Patent number: 9018689
    Abstract: A substrate processing apparatus includes a source gas supply system including a source gas supply pipe connected to a source gas source and a source gas supply controller; a reactive gas supply system including a reactive gas supply pipe connected to a reactive gas source, a reactive gas supply controller, a plasma generation unit and an ion trap unit and an inert gas supply pipe whereat an inert gas supply controller is disposed; a processing chamber supplied with a source gas by the source gas supply system and a reactive gas by the reactive gas supply system; and a control unit configured to control the gas supply controllers. The inert gas supply pipe has a downstream side connected between the reactive gas supply controller and the plasma generation unit and an upstream side connected to an inert gas supply source.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: April 28, 2015
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Yukitomo Hirochi, Naofumi Ohashi
  • Patent number: 8975677
    Abstract: A decoupling capacitor cell includes: a first decoupling capacitor formed by only a pMOS transistor; and a second decoupling capacitor formed by two metal layers. The decoupling capacitor cell is arranged in an unused region not occupied by basic cells in a cell-based IC and is connected to a power wiring and a ground wiring.
    Type: Grant
    Filed: March 22, 2013
    Date of Patent: March 10, 2015
    Assignee: Rohm Co., Ltd.
    Inventor: Yoshiharu Kito
  • Patent number: 8916919
    Abstract: A metal capacitor structure includes a plurality of line level structures vertically interconnected with via level structures. Each first line level structure and each second line level structure includes a set of parallel metal lines that is physically joined at an end to a rectangular tab structure having a rectangular horizontal cross-sectional area. A first set of parallel metal lines within a first line level structure and a second set of parallel metal lines within a second line level structure are interdigitated and parallel to each other, and can collectively form an interdigitated uniform pitch structure. Because the rectangular tab structures do not protrude toward each other within a region between two facing sidewalls of the rectangular tab structures, sub-resolution assist features (SRAFs) can be employed to provide a uniform width and a uniform pitch throughout the entirety of the interdigitated uniform pitch structure.
    Type: Grant
    Filed: June 23, 2011
    Date of Patent: December 23, 2014
    Assignee: International Business Machines Corporation
    Inventors: Eric Thompson, Roger A. Booth, Jr., Ning Lu, Christopher S. Putnam
  • Patent number: 8912586
    Abstract: In a semiconductor device, a polysilicon layer of a lower electrode contact plug is removed by a strip process such that the deposition area of a dielectric film is increased and capacitance of a capacitor is assured. A method for manufacturing the semiconductor device is also disclosed.
    Type: Grant
    Filed: January 10, 2012
    Date of Patent: December 16, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventor: Chan Woo Kim
  • Patent number: 8901710
    Abstract: Disclosed are an interdigitated capacitor and an interdigitated vertical native capacitor, each having a relatively low (e.g., zero) net coefficient of capacitance with respect to a specific parameter. For example, the capacitors can have a zero net linear temperature coefficient of capacitance (Tcc) to limit capacitance variation as a function of temperature or a zero net quadratic voltage coefficient of capacitance (Vcc2) to limit capacitance variation as a function of voltage. In any case, each capacitor can incorporate at least two different plate dielectrics having opposite polarity coefficients of capacitance with respect to the specific parameter due to the types of dielectric materials used and their respective thicknesses. As a result, the different dielectric plates will have opposite effects on the capacitance of the capacitor that cancel each other out such that the capacitor has a zero net coefficient of capacitance with respect to specific parameter.
    Type: Grant
    Filed: February 27, 2013
    Date of Patent: December 2, 2014
    Assignee: International Business Machines Corporation
    Inventors: Frederick G. Anderson, Natalie B Feilchenfeld, Zhong-Xiang He, Theodore J. Letavic, Yves T. Ngu
  • Patent number: 8878274
    Abstract: A capacitor for use in integrated circuits comprises a layer of conductive material. The layer of conductive material including at least a first portion and a second portion, wherein the first portion and the second portion are arranged in a predetermined pattern relative to one another to provide a maximum amount of capacitance per semiconductor die area.
    Type: Grant
    Filed: January 6, 2012
    Date of Patent: November 4, 2014
    Assignee: Micron Technology, Inc.
    Inventors: R. Jacob Baker, Kurt D. Beigel
  • Patent number: 8878272
    Abstract: Methods of fabricating a semiconductor device are provided. The method includes forming a first mold layer on a in a cell region and a peripheral region, forming first storage nodes penetrating the first mold layer in the cell region and a first contact penetrating the first mold layer in the peripheral region, forming a second mold layer on the first mold layer, forming second storage nodes that penetrate the second mold layer to be connected to respective ones of the first storage nodes, removing the second mold layer in the cell and peripheral regions and the first mold layer in the cell region to leave the first mold layer in the peripheral region, and forming a second contact that penetrates a first interlayer insulation layer to be connected to the first contact. Related devices are also provided.
    Type: Grant
    Filed: December 27, 2011
    Date of Patent: November 4, 2014
    Assignee: SK Hynix Inc.
    Inventor: Jun Ki Kim
  • Patent number: 8860115
    Abstract: A capacitor includes a lower electrode having a curved surface, a first seed on a sidewall of the lower electrode, which the first seed includes a metal silicide and has a shape corresponding to the curved surface of the lower electrode, a dielectric layer on the lower electrode, the dielectric layer covering the first seed, and an upper electrode on the dielectric layer.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: October 14, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jong-Ryul Jun
  • Patent number: 8847353
    Abstract: Capacitance blocks (first block and second block) respectively formed on two different adjacent common pad electrodes are electrically connected in series through an upper electrode. A distance between two adjacent capacitance blocks connected in series through an upper electrode film for the upper electrode corresponds to a distance between opposing lower electrodes disposed in an outermost perimeter of each capacitance block, and is two or less times than a total film thickness of the upper electrode film embedded between the two adjacent capacitance blocks.
    Type: Grant
    Filed: December 19, 2011
    Date of Patent: September 30, 2014
    Assignee: PS4 Luxco S.A.R.L.
    Inventor: Eiji Hasunuma
  • Patent number: 8786000
    Abstract: A method of manufacturing a semiconductor device includes: forming a core insulating film that includes first openings, on a semiconductor substrate; forming cylindrical lower electrodes that cover sides of the first openings with a conductive film; forming a support film that covers at least an upper surface of the core insulating film between the lower electrodes; forming a mask film in which an outside of a region where at least the lower electrodes are formed is removed, by using the support film; and performing isotropic etching on the core insulating film so as to leave the core insulating film at a part of an area between the lower electrodes, after the mask film is formed.
    Type: Grant
    Filed: December 28, 2011
    Date of Patent: July 22, 2014
    Assignee: PS4 Luxco S.A.R.L.
    Inventor: Eiji Hasunuma
  • Patent number: 8754462
    Abstract: A semiconductor device includes a first electrode electrically connected to an upper surface of a semiconductor element, a first internal electrode electrically connected to a lower surface of the semiconductor element and having a plurality of first comb finger portions and a first connection portion connecting the plurality of first comb finger portions together, a second electrode electrically connected to the first internal electrode, a second internal electrode electrically connected to a lower surface of the first electrode and having a plurality of second comb finger portions and a second connection portion connecting the plurality of second comb finger portions together, the plurality of second comb finger portions being interdigitated with but not in contact with the plurality of first comb finger portions, and a lower dielectric filling the space between the plurality of first comb finger portions and the plurality of second comb finger portions.
    Type: Grant
    Filed: January 3, 2013
    Date of Patent: June 17, 2014
    Assignee: Mitsubishi Electric Corporation
    Inventors: Noboru Miyamoto, Yoshikazu Tsunoda
  • Patent number: 8735956
    Abstract: A semiconductor device and a method for manufacturing the same are disclosed. An additional spacer is formed at a lateral surface of an upper part of the bit line so that the distance of insulation films between a storage node and a neighboring storage node contact plug is increased. Accordingly, the distance between the storage node and the neighboring storage node contact is guaranteed and a bridge failure is prevented.
    Type: Grant
    Filed: January 10, 2012
    Date of Patent: May 27, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventor: Un Hee Lee
  • Patent number: 8716778
    Abstract: Metal-insulator-metal capacitors are provided that are formed in integrated circuit dielectric stacks. A line-plate-line capacitor is provided that alternates layers that contain metal plates with layers that contain straight or angled parallel lines of alternating polarity. A segmented-plate capacitor is provided that has metal plates that alternate in polarity both within a layer and between layers. The line-plate-line and segmented-plate capacitors may exhibit a reduced parasitic inductive coupling. The capacitances of the line-plate-line capacitor and the metal-insulator-metal capacitor may have an enhanced contribution from an interlayer capacitance component with a vertical electric field than a horizontal intralayer capacitance component with a horizontal electric field.
    Type: Grant
    Filed: November 17, 2008
    Date of Patent: May 6, 2014
    Assignee: Altera Corporation
    Inventors: Shuxian Chen, Jeffrey T. Watt, Mojy Curtis Chian
  • Patent number: 8710569
    Abstract: A semiconductor device includes a semiconductor substrate including a DRAM portion and a logic portion thereon, an interlayer film covering the DRAM portion and logic portion of the semiconductor substrate, and plural contact plugs formed in the interlayer film in the DRAM portion and the logic portion, the plural contact plugs being in contact with a metal suicide layer on a highly-doped region of source and drain regions of first, second and third transistors in the DRAM portion and the logic portion, an interface between the plural contact plugs and the metal silicide layer being formed at a main surface in the DRAM portion and the logic portion.
    Type: Grant
    Filed: January 5, 2012
    Date of Patent: April 29, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Ken Inoue, Masayuki Hamada
  • Patent number: 8698279
    Abstract: The semiconductor device includes a capacitor including a plurality of interconnection layers stacked over each other, the plurality of interconnection layers each including a plurality of electrode patterns extended in a first direction, a plurality of via parts provided between the plurality of interconnection layers and electrically interconnecting the plurality of the electrode patterns between the interconnection layers adjacent to each other, and an insulating films formed between the plurality of interconnection layers and the plurality of via parts. Each of the plurality of via parts is laid out, offset from a center of the electrode pattern in a second direction intersecting the first direction, and the plurality of electrode patterns has a larger line width at parts where the via parts are connected to, and a distance between the electrode patterns and the adjacent electrode patterns is reduced at the parts.
    Type: Grant
    Filed: December 2, 2010
    Date of Patent: April 15, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Kenichi Watanabe, Nobuhiro Misawa
  • Patent number: 8698147
    Abstract: Provided are an organic light emitting display device and a method of manufacturing the same. The organic light emitting display device includes a thin-film transistor (TFT), which includes an active layer, a gate electrode, and source/drain electrodes; an organic electroluminescent device electrically connected to the TFT and includes a pixel electrode formed on the same layer as the gate electrode, an intermediate layer including an organic light emitting layer, and a counter electrode that are stacked in the order stated; and a capacitor, which includes a bottom electrode, which is formed on the same layer and of the same material as the active layer and is doped with an impurity; a top electrode formed on the same layer as the gate electrode; and a metal diffusion medium layer formed on the same layer as the source/drain electrodes and is connected to the bottom electrode.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: April 15, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jong-Hyun Choi, Na-Young Kim, Dae-Woo Lee
  • Patent number: 8692355
    Abstract: A minute capacitance element has a high accuracy capacitance and is resistant to external noises. The minute capacitance element includes: first and second metal electrodes having respective opposite facets facing each other formed on an insulator layer to define a first gap therebetween; and a shield electrode being connectable to an externally applied potential and formed on the insulator layer within the first gap to define a slit confining a synthetic capacitance.
    Type: Grant
    Filed: December 2, 2010
    Date of Patent: April 8, 2014
    Assignee: Oki Semiconductor Co., Ltd.
    Inventors: Daisuke Tanaka, Hiroyoshi Ichikura
  • Patent number: 8680595
    Abstract: A method and structure are disclosed that are advantageous for aligning a contact plug within a bit line contact corridor (BLCC) to an active area of a DRAM that utilizes an insulated sleeve structure. A sleeve insulator layer is deposited in an opening to protect one or more conductor layers from conductive contacts formed in the opening. The sleeve insulator layer electrically insulates a conductive plug from the conductor layer and self-aligns the BLCC so as to improve contact plug alignment tolerances between the BLCC and the capacitor or conductive components.
    Type: Grant
    Filed: June 28, 2011
    Date of Patent: March 25, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Philip J. Ireland, Howard E. Rhodes
  • Patent number: 8629033
    Abstract: A method for manufacturing a semiconductor device prevents a lower electrode from leaning, in a dip-out process of an interlayer insulation film forming a lower electrode. A conductive material of a lower electrode is used as a support layer instead of a conventional nitride film support layer. This prevents a crack from being generated in a nitride film support layer. A method for manufacturing the semiconductor device is also disclosed.
    Type: Grant
    Filed: January 10, 2012
    Date of Patent: January 14, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventor: Byung Wook Bae
  • Patent number: 8618635
    Abstract: In one embodiment, a capacitor includes a first via level having first metal bars and first vias, such that the first metal bars are coupled to a first potential node. The first metal bars are longer than the first vias. Second metal bars and second vias are disposed in a second via level, the second metal bars are coupled to the first potential node. The second metal bars are longer than the second vias. The second via level is above the first via level and the first metal bars are parallel to the second metal bars. Each of the first metal bars has a first end, an opposite second end, and a middle portion between the first and the second ends. Each of the middle portions of the first metal bars and the second ends of the first metal bars do not contact any metal line.
    Type: Grant
    Filed: October 27, 2010
    Date of Patent: December 31, 2013
    Assignee: Infineon Technologies AG
    Inventors: Sunoo Kim, Moosung Chae, Bum Ki Moon
  • Patent number: 8614472
    Abstract: An integrated circuit metal oxide metal (MOM) variable capacitor includes a first plate; one or more pairs of second plates positioned on both sides of the first plate; one or more pairs of control plates positioned on both sides of the first plate and positioned between the pairs of second plates; and a switch coupled to each control plate and a fixed potential.
    Type: Grant
    Filed: August 19, 2011
    Date of Patent: December 24, 2013
    Assignee: Integrated Device Technology, Inc.
    Inventors: Syed S. Islam, Mansour Keramat
  • Patent number: 8610188
    Abstract: A decoupling capacitor arrangement is provided for an integrated circuit. The apparatus includes a plurality of decoupling capacitor arrays electrically connected in parallel with one another. Each of the arrays includes a plurality of decoupling capacitors and a current limiting element. The decoupling capacitors of each array are electrically connected in parallel with one another. The current limiting element is connected in series with the plurality of decoupling capacitors.
    Type: Grant
    Filed: September 15, 2011
    Date of Patent: December 17, 2013
    Assignee: GLOBALFOUNDRIES, Inc.
    Inventors: Andreas Kerber, Tanya Nigam, Dieter Lipp, Marc Herden
  • Patent number: 8594604
    Abstract: Capacitive circuits are implemented with desirable quality factors in various implementations. According to an example embodiment, a fringe capacitor includes two capacitive circuits (e.g., plates), respectively having a plurality of capacitive fingers extending from an end structure, and respectively having a connecting pin that is adjacent the connecting pin of the other capacitive circuit, on a common side fringe capacitor. The capacitive fingers are arranged in stacked layers, with vias connecting the fingers in different layers back to the connecting pins.
    Type: Grant
    Filed: December 18, 2009
    Date of Patent: November 26, 2013
    Assignee: NXP, B.V.
    Inventors: Edwin van der Heijden, Lukas Frederik Tiemeijer, Maristella Spella
  • Patent number: 8569820
    Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a capacitor plate includes a plurality of first parallel conductive members, and a plurality of second parallel conductive members disposed over the plurality of first parallel conductive members. A first base member is coupled to an end of the plurality of first parallel conductive members, and a second base member is coupled to an end of the plurality of second parallel conductive members. A connecting member is disposed between the plurality of first parallel conductive members and the plurality of second parallel conductive members, wherein the connecting member includes at least one elongated via.
    Type: Grant
    Filed: January 6, 2012
    Date of Patent: October 29, 2013
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Barth, Erwin Ruderer, Alexander Von Glasow, Philipp Riess, Erdem Kaltalioglu, Peter Baumgartner, Thomas Benetik, Helmut Horst Tews
  • Patent number: 8546233
    Abstract: A method produces integrated circuit arrangement that includes an undulating capacitor in a conductive structure layer. The surface area of the capacitor is enlarged in comparison with an even capacitor. The capacitor is interlinked with dielectric regions at its top side and/or its underside, so that it can be produced by methods which may not have to be altered in comparison with conventional CMP methods.
    Type: Grant
    Filed: November 9, 2009
    Date of Patent: October 1, 2013
    Assignee: Infineon Technologies AG
    Inventor: Anton Steltenpohl
  • Patent number: 8508019
    Abstract: One or more embodiments are related to a semiconductor chip comprising a capacitor, the capacitor comprising: a plurality of conductive plates, each of the plates including a first conductive strip and a second conductive strip disposed over or under the first conductive strip, the second conductive strip of each plate being substantially parallel to the first conductive strip of the same plate, the second conductive strip of each plate electrically coupled to the first conductive strip of the plate through at least one conductive via, the second conductive strips of each group of at least two consecutive plates being spaced apart from each other in a direction along the length of the plates.
    Type: Grant
    Filed: July 5, 2012
    Date of Patent: August 13, 2013
    Assignee: Infineon Techn. AG
    Inventor: Philipp Riess
  • Patent number: 8497565
    Abstract: In a disclosed embodiment, a stacked capacitor (100) has bottom, middle and top metal electrode layers (141A, 141B, 141C) interleaved with dielectric layers (142A, 142B) conformally disposed within holes (140A, 140B, 140C) in a protective overcoat or backend dielectric layer (110) over a top metal layer (115) of an integrated circuit (105). A top electrode (155) contacts the top metal electrode layer (141C). A bottom electrode (150) electrically couples an isolated part of the top metal electrode layer (141C) through a bottom electrode via (165A) to a first contact node (135A) in the top metal layer (115) which is in contact with the bottom metal electrode layer (141A). A middle electrode (160) electrically couples a part of the middle metal electrode layer (141B) not covered by the top metal layer (115) through a middle electrode via (165B) to a second contact node (135B) in the top metal electrode layer (115).
    Type: Grant
    Filed: March 8, 2011
    Date of Patent: July 30, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Byron Lovell Willaims, Maxwell Walthour Lippitt, III, Betty Mercer, Scott Montgomery, Binghua Hu
  • Patent number: 8492822
    Abstract: A method for manufacturing an LC circuit, including forming a first conductive layer pattern serving as a lower electrode of a capacitor on a first interlayer insulating layer, forming a dielectric layer pattern storing electric charges on the first conductive layer pattern, forming a second conductive layer pattern serving as an upper electrode of the capacitor on the dielectric layer pattern, forming a second interlayer insulating layer on the second conductive layer pattern, forming a contact via exposing one of the first or second conductive layer pattern in the second interlayer insulating layer, and filling the contact via with a contact plug, and forming a third conductive layer pattern on the second interlayer insulating layer having the contact plug, wherein the third conductive layer pattern is electrically connected to the contact plug, and is etched in a metal interconnection type layer and functions as an inductor.
    Type: Grant
    Filed: March 9, 2010
    Date of Patent: July 23, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-Sung Lim, Chul-Ho Chung
  • Patent number: 8487406
    Abstract: At least a first capacitor is formed on a substrate and connected to a first differential node of a differential circuit, and the first capacitor may be variable in capacitance. A second capacitor is formed on the substrate and connected to a second differential node of the differential circuit, and the second capacitor also may be variable. A third capacitor is connected between the first differential node and the second differential node, and is formed at least partially above the first capacitor. In this way, a size of the first capacitor and/or the second capacitor may be reduced on the substrate, and capacitances of the first and/or second capacitor(s) may be adjusted in response to a variable characteristic of one or more circuit components of the differential circuit.
    Type: Grant
    Filed: September 19, 2011
    Date of Patent: July 16, 2013
    Assignee: Broadcom Corporation
    Inventors: Hooman Darabi, Qiang Li, Bo Zhang
  • Patent number: 8482048
    Abstract: A bypass capacitor is directly integrated on top of a MOSFET chip. The capacitor comprises multi layers of conductive material and dielectric material staking on top of each other with connection vias through dielectric layer for connecting different conductive layers. The method of integrating the bypass capacitor comprises repeating steps of depositing a dielectric layer, forming connection vias through the dielectric layer, depositing a conductive layer and patterning the conductive layer.
    Type: Grant
    Filed: November 16, 2010
    Date of Patent: July 9, 2013
    Assignee: Alpha & Omega Semiconductor, Inc.
    Inventors: Yan Xun Xue, Anup Bhalla, Hamza Yilmaz, Jun Lu
  • Patent number: 8445951
    Abstract: A semiconductor integrated circuit device, includes a first electrode including a first semiconductor layer formed on a substrate, a side surface insulating film formed on at least a part of a side surface of the first electrode, an upper surface insulating film formed on the first electrode and the side surface insulating film, a second electrode which covers the side surface insulating film and the upper surface insulating film, and a fin-type field effect transistor. The first electrode, the side surface insulating film, and the second electrode constitute a capacitor element. A thickness of the upper surface insulating film between the first electrode and the second electrode is larger than a thickness of the side surface insulating film between the first electrode and the second electrode, and the fin-type field effect transistor includes a second semiconductor layer which protrudes with respect to the plane of the substrate.
    Type: Grant
    Filed: February 28, 2012
    Date of Patent: May 21, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Hiroshi Furuta, Takayuki Shirai, Shunsaku Naga
  • Patent number: 8384144
    Abstract: An interdigitated Metal-Insulator-Metal (MIM) capacitor provides self-shielding and accurate capacitance ratios with small capacitance values. The MIM capacitor includes two terminals that extend to a plurality of interdigitated fingers separated by an insulator. Metal plates occupy layers above and below the fingers and connect to fingers of one terminal. As a result, the MIM capacitor provides self-shielding to one terminal. Additional shielding may be employed by a series of additional shielding layers that are isolated from the capacitor. The self-shielding and additional shielding may also be implemented at an array of MIM capacitors.
    Type: Grant
    Filed: October 6, 2008
    Date of Patent: February 26, 2013
    Assignee: Kenet, Inc.
    Inventor: Michael P. Anthony
  • Patent number: 8330251
    Abstract: An integrated circuit chip includes a first electronic device, a second electronic device, and a common electrode feature. The first electronic device includes a first feature. The first electronic device has a first footprint area in a given layer. The second electronic device includes a second feature. The second electronic device has a second footprint area in the given layer. The first and second electronic devices are electrically matched. The common electrode feature is common to the first and second electronic devices. The common electrode is at least partially located in the given layer. More than a majority of the first footprint area overlaps with the second footprint area. A first spacing between the first feature and the common electrode feature is about the same as a second spacing between the second feature and the common electrode feature.
    Type: Grant
    Filed: June 26, 2006
    Date of Patent: December 11, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Long Chang, Chia-Yi Chen, Chih-Ping Chao
  • Patent number: 8324069
    Abstract: A method of fabricating a high-performance capacitor that may be incorporated into a standard CMOS fabrication process suitable for submicron devices is described. The parameters used in the standard CMOS process may be maintained, particularly for the definition and etch of the lower electrode layer. To reduce variation in critical dimension width, an Anti-Reflective Layer (ARL) is used, such as a Plasma Enhanced chemical vapor deposition Anti-Reflective Layer (PEARL) or other Anti-Reflective Coatings (ARCS), such as a conductive film like TiN. This ARL formation occurs after the capacitor specific process steps, but prior to the masking used for defining the lower electrodes. A Rapid Thermal Oxidation (RTO) is performed subsequent to removing the unwanted capacitor dielectric layer from the transistor poly outside of the capacitor regions, but prior to the PEARL deposition.
    Type: Grant
    Filed: May 31, 2011
    Date of Patent: December 4, 2012
    Assignee: IXYS CH GmbH
    Inventors: Timothy K. Carns, John L. Horvath, Lee J. DeBruler, Michael J. Westphal
  • Patent number: 8314452
    Abstract: Structures and methods of forming an ideal MIM capacitor are disclosed. The single capacitor includes a first and a second metal structure overlying a substrate, a first dielectric material disposed between a first portion of the first metal structure and a first portion of the second metal structure. A second dielectric material is disposed between a second portion of the first metal structure and a second portion of the second metal structure. No first dielectric material is disposed between the second portion of the first and second metal structures, and no second dielectric material is disposed between the first portion of the first and second metal structures. The first and second dielectric material layers include materials with opposite coefficient of capacitance.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: November 20, 2012
    Assignee: Infineon Technologies AG
    Inventors: Philipp Riess, Armin Fischer