Abstract: An integrated circuit device includes a gate region extending above a semiconductor substrate and extending in a first longitudinal direction. A first fin has a first sidewall that extends in a second longitudinal direction above the semiconductor substrate such that the first fin intersects the gate region. A second fin has a second sidewall extending in the second direction above the semiconductor substrate such that the second fin intersects the gate region. A shallow trench isolation (STI) region is formed in the semiconductor substrate between the first and second sidewalls of the first and second fins. A conductive layer disposed over the first insulating layer and over top surfaces of the first and second fins. A first insulating layer is disposed between an upper surface of the STI region and a lower surface of the conductive layer to separate the STI region from the conductive layer.

Abstract: Embodiments relate to an improved tri-gate device having gate metal fills, providing compressive or tensile stress upon at least a portion of the tri-gate transistor, thereby increasing the carrier mobility and operating frequency. Embodiments also contemplate method for use of the improved tri-gate device.

Abstract: The present application discloses a method for manufacturing a gate-all-around field effect transistor, comprising the steps of: forming a suspended fin in a semiconductor substrate; forming a gate stack around the fin; and forming source/drain regions in the fin on both sides of the gate stack, wherein an isolation dielectric layer is formed in a portion of the semiconductor substrate which is adjacent to bottom of both the fin and the gate stack. The present invention relates to a method for manufacturing a gate-all-around device on a bulk silicon substrate, which suppress a self-heating effect and a floating-body effect of the SOI substrate, and lower a manufacture cost. The inventive method is a conventional top-down process with respect to a reference plane, which can be implemented as a simple manufacture process, and is easy to be integrated into and compatible with a planar CMOS process. The inventive method suppresses a short channel effect and promotes miniaturization of MOSFETs.

Abstract: A wiring substrate in which a capacitor is provided, the capacitor comprising a capacitor body including a plurality of dielectric layers and internal electrode layers provided between the different dielectric layers, wherein said capacitor body has, in at least one side face of said capacitor body, recesses extending in a thickness direction of said capacitor body from at least one of a first principal face of said capacitor body and a second principal face positioned on the side opposite to the first principal face.

Abstract: A method of forming a capacitor includes providing material having an opening therein over a node location on a substrate. A shield is provided within and across the opening, with a void being received within the opening above the shield and a void being received within the opening below the shield. The shield comprises a nitride. Etching is conducted within the opening through the nitride-comprising shield. After the etching, a first capacitor electrode is formed within the opening in electrical connection with the node location. A capacitor dielectric and a second capacitor electrode are formed operatively adjacent the first capacitor electrode. Other aspects and implementations are contemplated.

Abstract: Nonvolatile memory elements that are based on resistive switching memory element layers are provided. A nonvolatile memory element may have a resistive switching metal oxide layer. The resistive switching metal oxide layer may have one or more layers of oxide. A resistive switching metal oxide may be doped with a dopant that increases its melting temperature and enhances its thermal stability. Layers may be formed to enhance the thermal stability of the nonvolatile memory element. An electrode for a nonvolatile memory element may contain a conductive layer and a buffer layer.

Abstract: The invention includes methods in which silicon is removed from titanium-containing container structures with an etching composition having a phosphorus-and-oxygen-containing compound therein. The etching composition can, for example, include one or both of ammonium hydroxide and tetra-methyl ammonium hydroxide. The invention also includes methods in which titanium-containing whiskers are removed from between titanium-containing capacitor electrodes. Such removal can be, for example, accomplished with an etch utilizing one or more of hydrofluoric acid, ammonium fluoride, nitric acid and hydrogen peroxide.

Abstract: A method of forming a metal-insulator-metal capacitor has the following steps. A stack dielectric structure is formed by alternately depositing a plurality of second dielectric layers and a plurality of third dielectric layers. A wet etch selectivity of the second dielectric layer relative to said third dielectric layer is of at least 5:1. An opening is formed in the stack dielectric structure, and then a wet etch process is employed to remove relatively-large portions of the second dielectric layers and relatively-small portions of the third dielectric layers to form a plurality of lateral recesses in the second dielectric layers along sidewalls of the opening. A bottom electrode layer is formed to extend along the serrate sidewalls, a capacitor dielectric layer is formed on the bottom electrode layer, and a top electrode layer is formed on the capacitor dielectric layer.

Abstract: Methods and apparatuses to increase a surface area of a memory cell capacitor are described. An opening in a second insulating layer deposited over a first insulating layer on a substrate is formed. The substrate has a fin. A first insulating layer is deposited over the substrate adjacent to the fin. The opening in the second insulating layer is formed over the fin. A first conducting layer is deposited over the second insulating layer and the fin. A third insulating layer is deposited on the first conducting layer. A second conducting layer is deposited on the third insulating layer. The second conducting layer fills the opening. The second conducting layer is to provide an interconnect to an upper metal layer. Portions of the second conducting layer, third insulating layer, and the first conducting layer are removed from a top surface of the second insulating layer.

Abstract: Capacitive structures in integrated circuits are disclosed. The capacitive structures are formed on a substrate. Each capacitive structure includes a first conductive finger and a second conductive finger. The first and second conductive fingers are arranged in parallel with each other and separated from each other by a dielectric material. The first finger is connected to a first interconnect and the second conductive finger is connected to a second interconnect. A first capacitor is formed from a first group of the plurality of capacitive structures having respective interconnects coupled together. A second capacitor is formed from a second group of the plurality of capacitive structures having respective interconnects coupled together. The capacitive structures of the first group are intertwined with the capacitive structures of the second group.

Abstract: Semiconductor memory devices include a semiconductor substrate and a plurality of semiconductor material pillars in a spaced relationship on the semiconductor substrate. Respective surrounding gate electrodes surround ones of the pillars. A first source/drain region is in the semiconductor substrate between adjacent ones of the pillars and a second source/drain region is in an upper portion of at least one of the adjacent pillars. A buried bit line is in the first source/drain region and electrically coupled to the first source/drain region and a storage node electrode is on the upper portion of the at least one of the adjacent pillars and electrically contacting with the second source/drain region.

Abstract: Embedded memories. The devices include a substrate, a first dielectric layer, a second dielectric layer, a third dielectric layer, and a plurality of capacitors. The substrate comprises transistors. The first dielectric layer, embedding first and second conductive plugs electrically connecting the transistors therein, overlies the substrate. The second dielectric layer, comprising a plurality of capacitor openings exposing the first conductive plugs, overlies the first dielectric layer. The capacitors comprise a plurality of bottom plates, respectively disposed in the capacitor openings, electrically connecting the first conductive plugs, a plurality of capacitor dielectric layers respectively overlying the bottom plates, and a top plate, comprising a top plate opening, overlying the capacitor dielectric layers. The top plate opening exposes the second dielectric layer, and the top plate is shared by the capacitors.

Abstract: A semiconductor device and its manufacture method wherein the semiconductor substrate has first and second insulating films, the first insulating film being an insulating film other than a silicon nitride film formed at least on a side wall of a conductive pattern including at least one layer of metal or metal silicide, and the second insulating film being a silicon nitride film formed to cover the first insulating film and the upper surface and side wall of the conductive pattern. The first insulating film may be formed to cover the upper surface and side wall of the conductive pattern. A semiconductor device and its manufacture method are provided which can realize high integrated DRAMs of 256 M or larger without degrading reliability and stability.

Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a capacitor plate includes a plurality of first parallel conductive members, and a plurality of second parallel conductive members disposed over the plurality of first parallel conductive members. A first base member is coupled to an end of the plurality of first parallel conductive members, and a second base member is coupled to an end of the plurality of second parallel conductive members. A connecting member is disposed between the plurality of first parallel conductive members and the plurality of second parallel conductive members, wherein the connecting member includes at least one elongated via.

Abstract: A semiconductor device, and a method of fabricating the semiconductor device, which is able to prevent a leaning phenomenon from occurring between the adjacent storage nodes. The method includes forming a plurality of multi-layered pillar type storage nodes each of which is buried in a plurality of mold layers, wherein the uppermost layers of the multi-layered pillar type storage nodes are fixed by a support layer, etching a portion of the support layer to form an opening, and supplying an etch solution through the opening to remove the multiple mold layers. A process of depositing and etching the mold layer by performing the process 2 or more times to form the multi-layered pillar type storage node. Thus, the desired capacitance is sufficiently secured and the leaning phenomenon is avoided between adjacent storage nodes.

Abstract: Disclosed herein are improved fin-type field effect transistor (FinFET) structures and the associated methods of manufacturing the structures. In one embodiment FinFET drive current is optimized by configuring the FinFET asymmetrically to decrease fin resistance between the gate and the source region and to decrease capacitance between the gate and the drain region. In another embodiment device destruction at high voltages is prevented by ballasting the FinFET. Specifically, resistance is optimized in the fin between the gate and both the source and drain regions (e.g., by increasing fin length, by blocking source/drain implant from the fin, and by blocking silicide formation on the top surface of the fin) so that the FinFET is operable at a predetermined maximum voltage.

Abstract: Disclosed is a container capacitor structure and method of constructing it. An etch mask and etch are used to expose portions of an exterior surface of electrode (“bottom electrodes”) of the container capacitor structure. The etch provides a recess between proximal pairs of container capacitor structures, which recess is available for forming additional capacitance. Accordingly, a capacitor dielectric and a top electrode are formed on and adjacent to, respectively, both an interior surface and portions of the exterior surface of the first electrode. Advantageously, surface area common to both the first electrode and second electrodes is increased over using only the interior surface, which provides additional capacitance without a decrease in spacing for clearing portions of the capacitor dielectric and the second electrode away from a contact hole location.

Abstract: A capacitor and method of manufacturing the same include an insulating interlayer, a lower electrode, a protection structure, a dielectric layer and an upper electrode. The insulating interlayer may include a conductive pattern formed on a substrate. The lower electrode may be electrically connected to the conductive pattern. The protection structure may be formed on an outer sidewall of the cylindrical lower electrode and on the insulating interlayer.

Abstract: Disclosed herein are improved fin-type field effect transistor (FinFET) structures and the associated methods of manufacturing the structures. In one embodiment FinFET drive current is optimized by configuring the FinFET asymmetrically to decrease fin resistance between the gate and the source region and to decrease capacitance between the gate and the drain region. In another embodiment device destruction at high voltages is prevented by ballasting the FinFET. Specifically, resistance is optimized in the fin between the gate and both the source and drain regions (e.g., by increasing fin length, by blocking source/drain implant from the fin, and by blocking silicide formation on the top surface of the fin) so that the FinFET is operable at a predetermined maximum voltage.

Abstract: A method of forming a buried digit line is disclosed. Sacrificial spacers are formed along the sidewalls of an isolation trench, which is then filled with a sacrificial material. One spacer is masked while the other spacer is removed and an etch step into the substrate beneath the removed spacer forms an isolation window. Insulating liners are then formed along the sidewalls of the emptied trench, including into the isolation window. A digit line recess is then formed through the bottom of the trench between the insulating liners, which double as masks to self-align this etch. The digit line recess is then filled with metal and recessed back, with an optional prior insulating element deposited and recessed back in the bottom of the recess.

Abstract: Apparatuses and methods for increasing well distributed, high quality-factor on-chip capacitance of integrated circuit devices are disclosed. In one aspect, an integrated circuit device structure includes a first metal line implemented on a metallization layer of a semiconductor substrate, the first metal line having a first set of metal fingers extending therefrom; and a second metal line electrically isolated from the first metal line, the second metal line having a second set of metal fingers extending therefrom, the first set of metal fingers and the second set of metal fingers capacitively coupled. The basic structure of metal lines with interlocking metal fingers may be repeated on multiple adjacent metallization layers, with the metal lines oriented either in parallel or perpendicular.

Abstract: A semiconductor device may include a substrate having a cell active region. A cell gate electrode may be formed in the cell active region. A cell gate capping layer may be formed on the cell gate electrode. At least two cell epitaxial layers may be formed on the cell active region. One of the at least two cell epitaxial layers may extend to one end of the cell gate capping layer and another one of the at least two cell epitaxial layers may extend to an opposite end of the cell gate capping layer. Cell impurity regions may be disposed in the cell active region. The cell impurity regions may correspond to a respective one of the at least two cell epitaxial layers.

Abstract: A cell structure of a semiconductor device includes an active region, having a concave portion, and an inactive region that defines the active region. A gate pattern in the active region is arranged perpendicular to the active region. A landing pad on the active region and the inactive region contacts the active region. A bit line pattern on the inactive region intersects the gate pattern perpendicularly, the bit line pattern being electrically connected to the landing pad and having a first protrusion corresponding to the concave portion of the active region.

Abstract: A movable substrate is placed over a bottom substrate where both substrates contain Coulomb islands. The Coulomb islands can be adjusted in charge and are used to develop a force between two opposing Coulomb islands. Information from sensors is applied to a control unit to control the movement of the movable substrate. Coulomb islands are formed in the juxtaposed edges of a first substrate and second substrate, respectively. The islands generate edge Coulomb forces. These edge Coulomb forces can be used to detach, repel, move, attract and reattach the edges of substrates into new configurations. One possibility is to combine a plurality of individual substrates into one large planar substrate.

Abstract: A semiconductor device for preventing the leaning of storage nodes and a method of manufacturing the same is described. The semiconductor device includes support patterns that are formed to support a plurality of cylinder type storage nodes. The support patterns are formed of a BN layer and have a hexagonal structure. The BN layer forming the support patterns has compressive stress as opposed to tensile stress and can therefore withstand cracking in the support patterns.

Abstract: A semiconductor memory device includes a semiconductor substrate, a semiconductor layer, a source/drain layer, first and second insulating films, and first and second gate electrodes. The semiconductor layer of one conductivity type is formed on a principal surface of the semiconductor substrate. The source/drain layer is formed on the principal surface with being in contact with one end of the semiconductor layer, and has a conductivity type opposite to the one conductivity type. The first insulating film is formed on one side surface of the semiconductor layer. The second insulating film is formed on another side surface of the semiconductor layer. The first gate electrode is formed on the one side surface via the first insulating film. The second gate electrode is formed on the other side surface of the semiconductor layer via the second insulating film, and is opposed to the first gate electrode.

Abstract: A semiconductor device is manufactured by forming a hole as being extended through a first insulating film and an insulating interlayer stacked over a semiconductor substrate, allowing side-etching of the inner wall of the hole to proceed specifically in a portion of the insulating interlayer, to thereby form a structure having the first insulating film projected out from the edge towards the center of the hole; forming a lower electrode film as being extended over the top surface, side face and back surface of the first insulating film, and over the inner wall and bottom surface of the hole; filling a protective film in the hole; removing the lower electrode film specifically in portions fallen on the top surface and side face of the first insulating film; removing the protective film; and forming a cylindrical capacitor in the hole.

Abstract: The present disclosure provides on-chip decoupling capacitor structures having trench capacitors integrated with a passive capacitor formed in the back-end-of-line wiring to provide an improved overall capacitance density. In some embodiments, the structure includes at least one deep trench capacitor and a passive capacitor formed in at least two back-end-of-line wiring levels. The trench and passive capacitors are in electrical communication through one of the wiring levels. In other embodiments, the structure includes at least one deep trench capacitor, a first back-end-of-line wiring level, and a second back-end-of-line wiring level. The deep trench capacitor with a dielectric that has an upper edge that terminates at a lower surface of a shallow trench isolation region. The first wiring level is in electrical communication with the trench capacitor. The second wiring level is vertically electrically connected to the first wiring level by vertical connectors so as to form a passive capacitor.

Abstract: This invention provides a capacitor device with a high dielectric constant material and multiple vertical electrode plates. The capacitor devices can be directly fabricated on a wafer with low temperature processes so as to be integrated with active devices formed on the wafer. This invention also forms vertical conducting lines in the capacitor devices using the through-silicon-via technology to facilitate the three-dimensional stacking of the capacitor devices.

Abstract: A storage node structure includes a substrate having thereon a conductive block region; an etching stop layer covering the conductive block region; a conductive layer penetrating the etching stop layer and electrically connecting the conductive block region; an annular shaped conductive spacer on sidewall of the conductive layer, wherein the annular shaped conductive spacer is disposed on the etching stop layer and wherein the annular shaped conductive spacer and the conductive layer constitute a storage node pedestal; and an upper node portion stacked on the storage node pedestal.

Abstract: A semiconductor memory device in which a plurality of capacitors each including a columnar lower electrode, a capacitor insulation film and an upper electrode are stacked with interlayer films therebetween, a contact plug connects an upper face of each lower electrode of a lower layer with a bottom face of each lower electrode of an upper layer, and another contact plug connects upper electrodes of the capacitors in respective layers with each other.

Abstract: A method that includes forming a semiconductor fin, forming a sacrificial material adjacent the semiconductor fin, covering the sacrificial material with a dielectric material, forming a cavity by removing the sacrificial material from under the dielectric material, and forming a gate in the cavity. System and devices are also provided.

Abstract: This disclosure concerns a semiconductor memory device including a substrate; an insulating film provided above the substrate; a semiconductor layer provided above the insulating film and extending in a plane which is parallel to a surface of the substrate; a first gate dielectric film provided on an inner wall of a opening penetrating through the semiconductor layer; a first gate electrode penetrating through the opening and isolated from the semiconductor layer by the first gate dielectric film; a second gate dielectric film formed on a side surface and an upper surface of the semiconductor layer located on the first gate electrode; and a second gate electrode provided on the side surface and the upper surface of the semiconductor layer via the second gate dielectric film, isolated from the first gate electrode, and superimposed on the first gate electrode.

Abstract: A capacitor pair structure for increasing the match thereof has two finger electrode structures interlacing with each other in parallel and a common electrode being between the two finger electrode structures to form a capacitor pair structure with an appropriate ratio. Also, the capacitor pair structure could further increase its entire capacitance through vias connecting the same capacitor pair structures on different metal layers.

Abstract: A capacitor of a semiconductor memory device, and methods of forming the same, are disclosed. A pad interlayer insulating layer is disposed on a semiconductor substrate of an active region. Landing pads and a central landing pad are disposed in peripheral portions and a central portion of the active region, respectively, to penetrate the pad interlayer insulating layer. The upper surface of the central landing pad has a different area from the upper surfaces of the landing pads. A buried interlayer insulating layer is formed on the pad interlayer insulating layer to cover the landing pads and the central landing pad. Buried plugs are formed on the respective landing pads to penetrate the buried interlayer insulating layer. Lower electrodes are formed on the buried plugs.

Abstract: A capacitance cell 21 is wired while using adjacent wiring layers Ma and Mb as a pair of electrode layers T1 and T2 orthogonally to opposed lateral end faces out of lateral end faces X1, X2, Y1, and Y2 that section the cell in a plane direction. Contact surfaces of electrode surfaces T1 and T2 with the lateral end faces are second connection terminals T12 and T22. For longitudinal pathways, first and second via contact layers V1 and V2are connected. The first via contact layer V1 interconnects the wiring layers Ma and Mb. The second via contact layer V2 is connected to a wiring layer located outside beyond an upper or lower end face Z2, Z1. The second via contact layer V2 is connected to a first connection terminal T11, T21 located on the upper or lower end faces Z2, Z1. The capacitance cells 21 are linked via the first and second connection terminals so that a capacitance element having a free shape is formed.

Abstract: A capacitor pair structure for increasing the match thereof has two finger electrode structures interlacing with each other in parallel and a common electrode being between the two finger electrode structures to form a capacitor pair structure with an appropriate ratio. Also, the capacitor pair structure could further increase its entire capacitance through vias connecting the same capacitor pair structures on different metal layers.

Abstract: The invention provides a memory cell. The memory cell is disposed on a substrate and comprises a plurality of isolation structures defining at least a fin structure in the substrate. Further, the surface of the fin structure is higher than the surface of the isolation structure. The memory cell comprises a doped region, a gate, a charge trapping structure and a source/drain region. The doped region is located in a top of the fin structure and near a surface of the top of the fin structure and the doped region has a first conductive type. The gate is disposed on the substrate and straddled the fin structure. The charge trapping structure is disposed between the gate and the fin structure. The source/drain region with a second conductive type is disposed in the fin structures exposed by the gate and the first conductive type is different from the second conductive type.

Abstract: Disclosed is a method of fabricating a semiconductor device including a multi-gate transistor. The method of fabricating a semiconductor device includes providing a semiconductor device having a number of active patterns which extend in a first direction, are separated by an isolation layer, and covered with a first insulating layer; forming a first groove by etching the isolation layer located between the active patterns adjacent to each other in the first direction; burying the first groove with a passivation layer; forming a second groove exposing at least a portion of both sides of the active patterns by etching the isolation layer located between the active patterns in a second direction intersecting the first direction; removing the passivation layer in the first groove; and forming a gate line filling at least a portion of the second groove and extending in the second direction.

Abstract: An electronic device can include a first semiconductor fin and a second semiconductor fin, each spaced-apart from the other. The electronic device can also include a bridge lying between and contacting each of the first semiconductor fin and the second semiconductor fin along only a portion of length of each of the first semiconductor fin and the second semiconductor fin, respectively. In another aspect, a process for forming an electronic device can include forming a first semiconductor fin and a second semiconductor fin from a semiconductor layer, each of the first semiconductor fin and the second semiconductor fin spaced-apart from the other. The process can also include forming a bridge that contacts the first semiconductor fin and second semiconductor fin. The process can further include forming a conductive member, including a gate electrode, lying between the first semiconductor fin and second semiconductor fin.

Abstract: The capacitor structure includes a first electrode having a plurality of teeth protruding in a comb shape from an electrode base of a first electrode line and a second electrode having a plurality of teeth protruding in a comb shape from an electrode base of a second electrode line, both formed in a first wiring layer. The first and second electrodes face each other with their teeth interdigitated with each other via a dielectric. At least one of the teeth of the first electrode is electrically connected with a third electrode line formed in a second wiring layer.

Abstract: Each pixel has a photoelectric conversion unit configured to convert light into electrical charges and to store the electrical charges, an amplifying unit configured to amplify a signal based on the electrical charges stored in the photoelectric conversion unit and to output the signal to an output line, and a reset unit configured to reset a input part of the amplifying unit. A clip unit, which is configured to limit an electric voltage of the output line, includes an amplifying circuitry for amplifying a signal based on the electric voltage of the output line and an MOS transistor for limiting the electric voltage of the output line based on the difference in electric potential between the gate and source. The clip unit controls the electric potential of the gate of the MOS transistor by the amplifying circuitry.

Abstract: Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes an insulating layer that is formed on a supporting layer and has a contact hole. A first contact plug is formed on an inner wall and bottom of the contact hole. A second contact plug buries the contact hole and is formed on the first contact plug. A conductive layer is connected to the first contact plug and the second contact plug. The bottom thickness of the first contact plug formed on the bottom of the contact hole is thicker than the inner wall thickness of the first contact plug formed on the inner wall of the contact hole.

Abstract: The semiconductor memory device includes: an interlayer insulating film that is formed on a semiconductor substrate; an insulating film that is formed on the interlayer insulating film and has a cylinder hole; and a capacitor that has an impurity-containing silicon film, a lower metal electrode, a capacitive insulating film and an upper electrode, which are formed so as to cover a bottom and a side of the cylinder hole, wherein the cylinder hole extends through the insulating film so as to expose an end side of the contact plug, the end side facing opposite from the source electrode; and the impurity-containing silicon film has a silicide layer near an interface between the impurity-containing silicon film and the lower metal electrode, the silicide layer being produced by a reaction of impurity-containing silicon included in the impurity-containing silicon film with metal included in the lower metal electrode.

Abstract: Recessed gate transistor structures and methods for making the same prevent a short between a gate conductive layer formed on a non-active region and an active region by forming an insulation layer therebetween, even though a misalignment is generated in forming a gate. The method and structure reduce the capacitance between gates. The method includes forming a device isolation film for defining an active region and a non-active region, on a predetermined region of a semiconductor substrate. First and second insulation layers are formed on an entire face of the substrate. A recess is formed in a portion of the active region. A gate insulation layer is formed within the recess, and then a first gate conductive layer is formed within the recess. A second gate conductive layer is formed on the second insulation layer and the first gate conductive layer. Subsequently, source/drain regions are formed.

Abstract: A semiconductor component has an insulating layer which is formed on a semiconductor substrate and in which a capacitance structure (K) is formed. The capacitance structure (K) has at least two metallization planes (1 to 7) which are arranged parallel to one another and are each connected to an electrical connecting line. Arranged between the metallization planes (1 to 7) is at least one electrically conductive region (1a to 1j; 2a to 2j; 31a to 36a; 41a to 46a; 5a to 5f) for producing a capacitance surface, the electrically conductive region (1a to 1j; 2a to 2j; 31a to 36a; 41a to 46a; 5a to 5f) being electrically connected only to one of the metallization planes (1 to 7).

Abstract: A method of forming a buried digit line is disclosed. Sacrificial spacers are formed along the sidewalls of an isolation trench, which is then filled with a sacrificial material. One spacer is masked while the other spacer is removed and an etch step into the substrate beneath the removed spacer forms an isolation window. Insulating liners are then formed along the sidewalls of the emptied trench, including into the isolation window. A digit line recess is then formed through the bottom of the trench between the insulating liners, which double as masks to self-align this etch. The digit line recess is then filled with metal and recessed back, with an optional prior insulating element deposited and recessed back in the bottom of the recess.

Abstract: A technique is provided which makes it possible to achieve both of a reduction in contact resistance in a memory device and a reduction in contact resistance in a logic device even when oxidation is performed during formation of dielectric films of capacitors. Conductive barrier layers (82) are provided in the top ends of contact plugs (83b) electrically connected to ones of source/drain regions (59). Lower electrodes (70) of capacitors (73) are formed in contact with the conductive barrier layers (82) of the contact plugs (83b) and then dielectric films (71) and upper electrodes (72) of the capacitors (73) are sequentially formed. In the logic region, contact plugs (25) are formed in an upper layer so that they are in contact respectively with contact plugs (33) electrically connected to source/drain regions (9).

Abstract: A semiconductor device includes a capacitor having a bottom electrode, a dielectric layer formed on the bottom electrode, a top electrode formed on the dielectric layer, and a contact plug having a metal that is connected with the top electrode, wherein the top electrode includes a doped poly-Si1-xGex layer and a doped polysilicon layer epitaxially deposited on the doped poly-Si1-xGex layer and the contact plug makes a contact with the doped polysilicon layer.

Abstract: A semiconductor device may include a MOS transistor having source and drain regions in a semiconductor substrate, a first inter-layer insulator having first contact holes that reach the source and drain regions over the MOS transistor. Cell contact plugs in the first contact holes contact with the source and drain regions. A second inter-layer insulator over the first inter-layer insulator and the cell contact plugs has second contact holes that reach the cell contact plugs. Contact plugs each have first and second portions. The first portion is in the second contact hole. The second portion extends over the first second inter-layer insulator. Metal barrier layers cover the upper surfaces of the second portions of the contact plugs. Capacitors each have a bottom electrode layer, a capacitive insulating layer and a top electrode layer. The bottom electrode layers each have a contact portion that contacts with the metal barrier layer.