Abstract: A method for fabricating buried decoupling capacitors in an integrated circuit is disclosed. The method forms decoupling capacitors by creating an opening within a substrate which has fin-like spacers, depositing a dielectric material over the spacers, depositing an electrode material over the dielectric material, depositing an insulative material over the electrode material, and forming integrated circuit components over the insulative material.

Abstract: A DRAM of an open bit line structure has a cell area smaller than that of a DRAM of a folded bit line structure and is susceptible to noise. A conventional DRAM of an open bit line structure has a large bit line capacitance and is susceptible to noise or has a large cell area. There has been no DRAM of an open bit line structure having a small bit line capacitance, unsusceptible to noise and having a small cell area. The present invention forms capacitor lower electrode plug holes not aligned with bit lines to reduce bit line capacitance. Bit lines are formed in a small width, capacitor lower electrode plugs are dislocated from positions corresponding to the centers of the bit lines in directions away from the bit lines and the contacts are formed in a reduced diameter to avoid increasing the cell area. Thus a semiconductor storage device of an open bit line structure resistant to noise and having a small cell area is provided.

Abstract: A method for manufacturing DRAM cells in a semiconductor wafer including MOS control transistors and capacitors, the source/drain regions and the gates of the control transistors being covered with a protection layer and with an insulating layer, in which the capacitors are formed at the level of openings formed in the insulating layer which extend to the protection layer covering the gates, and in which first capacitor electrodes are connected to source/drain regions of the control transistors by conductive vias crossing the insulating layer and the protection layer.

Abstract: A semiconductor device includes a diffusion region in a semiconductor substrate, a gate insulation film on the semiconductor substrate, a gate electrode on the gate insulation film, an interlayer insulation film on the semiconductor substrate covering the gate electrode, and a capacitor on the interlayer insulation film. The capacitor includes a laminated structure made up of a lower electrode, a dielectric film, and an upper electrode. The diffusion region, the gate electrode, and the lower electrode are connected to one another by a common contact in the interlayer insulation film.

Abstract: The bit lines composed of a conductive film containing the tungsten as a principal component are formed inside the side wall spacers formed on the side walls of the wiring grooves. The TiN film having a higher adhesive strength to the silicon oxide than the tungsten is formed on the boundary faces between the bit lines and the side wall spacers, which functions as an adhesive layer that prevents strippings on the boundary faces between the bit lines and the side wall spacers. Thereby, the invention prevents disconnections, even when the width of the wirings having the tungsten as the principal component is fined to 0.1 &mgr;m or less.

Abstract: The present invention is directed to fabrication of a capacitor formed with a substantially concave shape and having optional folded or convoluted surfaces. The concave shape optimizes surface area within a small volume and thereby enables the capacitor to hold a significant charge so as to assist in increased miniaturization efforts in the microelectronic field. The capacitor is fabricated in microelectronic fashion consistent with a dense DRAM array. Methods of fabrication include stack building with storage nodes that extend above a semiconductor substrate surface.

Abstract: An apparatus and fabrication process for a capacitor formed in conjunction with a dual damascene process. A bottom capacitor plate is electrically connected to an overlying first conductive via formed according to the dual damascene process. A top capacitor plate is connected to an overlying second conductive via. A dielectric material is disposed between the top and the bottom plates. The capacitor is formed by successively forming the bottom plate, the dielectric layer, and the top plate, patterning these layers as required after their formation. The first conductive via is formed over and electrically connected to the bottom plate and the second conductive via is formed over and connected to the top capacitor plate thereby providing for interconnection of the capacitor to other circuit elements by way of the dual damascene conductive runners connected to the conductive vias.

Abstract: Integrated circuit capacitor electrodes include a first conductive ring on a face of an integrated circuit substrate. A second conductive ring is provided on the first conductive ring opposite the substrate. A third conductive ring also is provided on the first conductive ring opposite the substrate. The third ring is located at least partially within the second ring. A conductive layer electrically connects the first, second and third rings. To form the electrodes, a first conductive layer is conformally deposited in the areas in which the electrodes will be formed and on a mold oxide layer. A first buffer dielectric layer is deposited on the first conductive layer. The first buffer dielectric layer and the first conductive layer are etched to separate nodes of the first conductive layer. Recessed portions are formed by further etching the first conductive layer.

Abstract: The present teachings describe a container capacitor that utilizes an etchant permeable lower electrode for the formation of single or double-sided capacitors without excessive etching back of the periphery of the use of sacrificial spacers. The present teachings further describe a method of forming at least one capacitor structure on a substrate. For example, the method comprises forming at least one recess in the substrate, depositing a first conductive layer on the substrate so as to overlie the at least one recess, and defining at least one lower electrode within the at least one recess formed in the substrate by removing at least a portion of the first conductive layer. The method further comprises diffusing an etchant through the at least one lower electrode so as to remove at least a portion of the substrate to thereby at least partially isolate the at least one lower electrode.

Abstract: A thin-film resistor includes a resistive element with a predetermined length and width deposited on a substrate. An insulator layer is patterned so as to cover all of the resistive element except the ends in the width direction and is tapered. Electrodes are connected to respective ends of the resistive element via a plating base layer. The electrodes have a reduced resistance. The thin-film resistor can exhibit high accuracy and a small range of variation of the resistance.

Abstract: The semiconductor device having the capacitor comprises a plurality of switching elements formed on a semiconductor substrate 1 at a distance, a plurality of capacitors formed in areas between a plurality of switching elements formed in the first direction respectively and each having a lower electrode, a dielectric film and an upper electrode, first wirings for connecting the upper electrodes of the capacitors and the switching elements in the first direction on a one-by-one base, and second wirings formed over a part of the first wirings, the switching elements, and the capacitors to extend in the second direction that intersects with the first direction. Accordingly, the higher speed operation than the prior art can be achieved.

Abstract: There is described a semiconductor device having a storage node capacitor structure suitable for rendering memory cells compact, and storage nodes are prevented from tilting. The device includes a storage node which has a vertical surface extending in the direction perpendicular to the surface of a semiconductor substrate, and a dielectric film for tilt prevention purposes which is brought into close contact with the side surface of the vertical surface and which prevents the vertical surface from tilting.

Abstract: The present invention relates to double-gate FinFET devices and fabricating methods thereof. More particularly, the invention relates to an electrically stable double-gate FinFET device and the method of fabrication in which the Fin active region on a bulk silicon substrate where device channel and the body are to be formed has a nano-size width and is connected to the substrate and is formed with the shape of a wall along the channel length direction.

Abstract: A semiconductor memory device comprises select transistors formed on side surfaces of plural silicon columns defined by a grid-like trenches on a surface of a silicon substrate, each select transistor having a source and a drain on the top surface and the bottom of the silicon column. A capacitor is formed on the top surface of the silicon column to form a DRAM cell. The source/drain layers on the bottom of a greater number of memory cells are commonly connected, or the source/drain layers on the bottom of adjacent memory cells are commonly connected, to be brought out to the surface of the silicon substrate by a connection line to be connected to a constant voltage or a bit line.

Abstract: It is an object to provide a semiconductor device in which a structure of a capacitor is simplified. Any electrical connection of a capacitor (CP10) and source—drain regions (11) and (13) is carried out by a contact plug (101) inserted in the capacitor (CP10) and reaching the source—drain regions (11) and (13). The capacitor (CP10) has a capacitor upper electrode (103) provided to be embedded in an upper main surface of an interlayer insulating film (3) and a capacitor dielectric film (102) provided to cover a side surface and a lower surface of the capacitor upper electrode (103). Moreover, the capacitor dielectric film (102) is also provided to cover a side surface of the contact plug (101) formed to penetrate through the capacitor upper electrode (103), and a portion of the contact plug (101) which is covered with the capacitor dielectric film (102) functions as the capacitor lower electrode (101).

Abstract: The preferred embodiment of the present invention provides unique structure for connecting between a storage capacitor and a transfer device in a memory cell and a method for fabricating the same. The preferred embodiment of the present invention forms a capacitor structure having a “lip” at its top on the side the connection is to be made. To form the connection, dopant is diffused from the lower surface of the capacitor step and into the substrate, forming a surface strap to connect between the storage capacitor and the transfer device. This surface strap has the advantage of being self aligned with the storage capacitor and the transfer device, facilitating higher memory cell densities. The present invention can be used to form connections between storage capacitors and memory cells in a wide variety of devices.

Abstract: In a DRAM memory cell that is a semiconductor memory device, a bit line connected to a bit line plug and local interconnect are provided on a first interlayer insulating film. A contact is not provided on a Pt film constituting an upper electrode, and a dummy lower electrode is in direct contact with a dummy barrier metal. That is, the upper electrode is connected to upper layer interconnect (Cu interconnect) by the dummy lower electrode, a dummy cell plug and the local interconnect. Since the Pt film is not exposed to a reducing atmosphere, deterioration of characteristics of a capacitive insulating film can be prevented.

Abstract: A method of forming a capacitor includes, a) providing a node to which electrical connection to a first capacitor plate is to be made; b) then, providing a finned lower capacitor plate in ohmic electrical connection with the node using no more than one photomasking step; and c) providing a capacitor dielectric layer and a conductive second capacitor plate layer over the conductive layer.

Abstract: A capacitor sheet includes a laminate sheet, interface-connection feedthrough conductors for electrically connecting faces of the laminate sheet, and capacitor-connection feedthrough conductors. The laminate sheet has at least one laminate which is composed of a power source layer electrode, a grounding layer electrode, and a dielectric layer interposed between the power source layer electrode and the grounding layer electrode. The interface-connection feedthrough conductors are formed in through holes that pass through the dielectric layer, the power source layer electrode, and the grounding layer electrode, and are insulated by insulation walls from the power source layer electrode and the grounding layer electrode provided inside. The capacitor-connection feedthrough conductors are formed in regions where only either the power source layer electrode or the grounding layer electrode is provided, and are connected electrically with either the power source layer electrode or the grounding layer electrode.

Abstract: A capacitor of a semiconductor device is provided which includes a semiconductor substrate and insulating interlayer formed on the semiconductor substrate. The insulating interlayer has a contact hole which exposes a portion of the semiconductor substrate. A plug fills in the contact hole and the plug comes into contact with the semiconductor substrate. A contact layer is formed on the insulating interlayer. The contact layer comes into contact with the plug. First and second barrier layers are formed on the surface and sides of the contact layer, and a lower electrode is formed on the first barrier layer. A dielectric layer formed on the second barrier layer and lower electrode, and an upper electrode is formed on the dielectric layer.

Abstract: A semiconductor device having MIM capacitors is configured so that the bottom surface of the lower electrode and a top surface area of an oxidation barrier pattern are substantially equal. Related methods for forming the device are also described.

Abstract: The present invention describes methods, apparatus, and systems related to polysilicon gate contact openings over active regions formed by a separate mask to provide enough control of dielectric removal to produce a contact opening at least down to the gate layer but not down to the junction layers. Embodiments include, self-aligned polysilicon contacts done by timed contact etch, by a two layer dielectric, by adding a dielectric etch stop layer, and by partially planarizing a dielectric or etch stop layer over the gate layer. Thus, even if mis-aligned, the gate contact openings will be deep enough to reach active region gates, but not deep enough to reach junctions. As a result, by using a separate mask and by selecting a period of time for etching to active gates, gate contact openings can be formed during manufacture of ICs, semiconductors, MOS memory cells, SRAM, flash memory, and various other memory cells.

Abstract: Briefly, in accordance with an embodiment of the invention, a phase change memory and a method to manufacture a phase change memory is provided. The phase change memory may include an electrode, an adhesive material, an insulating material between the electrode and the adhesive material, wherein a portion of the adhesive material, a portion of the insulating material, and a portion of the electrode form a substantially planar surface. The phase change memory may further include a phase change material on the substantially planar surface and contacting the electrode, the adhesive material, and the insulating material.

Abstract: The present invention is directed to fabrication of a capacitor formed with a substantially concave shape and having optional folded or convoluted surfaces. The concave shape optimizes surface area within a small volume and thereby enables the capacitor to hold a significant charge so as to assist in increased miniaturization efforts in the microelectronic field. The capacitor is fabricated in microelectronic fashion consistent with a dense DRAM array. Methods of fabrication include stack building with storage nodes that extend above a semiconductor substrate surface.

Abstract: An apparatus including a capacitor formed between metallization layers on a circuit, the capacitor including a bottom electrode coupled to a metal layer and a top electrode coupled to a metal via wherein the capacitor has a corrugated sidewall profile. A method including forming an interlayer dielectric including alternating layers of dissimilar dielectric materials in a multilayer stack over a metal layer of a device structure; forming a via having a corrugated sidewall; and forming a decoupling capacitor stack in the via that conforms to the sidewall of the via.

Abstract: A memory structure having a vertically oriented access transistor with an annular gate region and a method for fabricating the structure. More specifically, a transistor is fabricated such that the channel of the transistor extends outward with respect to the surface of the substrate. An annular gate is fabricated around the vertical channel such that it partially or completely surrounds the channel. A buried annular bitline may also be implemented. After the vertically oriented transistor is fabricated with the annular gate, a storage device may be fabricated over the transistor to provide a memory cell.

Abstract: An integrated device having: a first conductive region; a second conductive region; an insulating layer arranged between the first and the second conductive region; at least one through opening extending in the insulating layer between the first and the second conductive region; and a contact structure formed in the through opening and electrically connecting the first conductive region and the second conductive region. The contact structure is formed by a conductive material layer that coats the side surface and the bottom of the through opening and surrounds an empty region which is closed at the top by the second conductive region. The conductive material layer preferably comprises a titanium layer and a titanium-nitride layer arranged on top of one another.

Abstract: A masking and etching technique during the formation of a memory cell capacitor which simultaneously separates storage poly into individual storage poly nodes and etches recesses into the storage poly nodes which increase the surface area of the storage poly nodes and thereby increase the capacitance of a completed memory cell without additional processing steps.

Abstract: A method for ion implantation of high dielectric constant materials with dopants to reduce film leakage and improve resistance degradation is disclosed. Particularly, the invention relates to ion implantation of (Ba,Sr)TiO3 (BST) with donor dopants to reduce film leakage and improve resistance degradation of the BST film. The invention also relates to varying the ion implantation angle of the dopant to uniformly dope the high dielectric constant materials when they have been fabricated over a stepped structure. The invention also relates to integrated circuits having a doped thin film high dielectric material used as an insulating layer in a capacitor structure.

Abstract: A semiconductor memory device includes a bit line stack and a storage node contact hole which are aligned at bit line spacers formed at both side walls of the bit line stack and exposes a pad. The semiconductor memory device includes a multi-layered storage node contact plug in which a first storage node contact plug and a second storage node contact plug are sequentially formed. The first storage node contact plug is formed of titanium nitride and the second storage node contact plug is formed of polysilicon. An ohmic layer may be formed on the pad and under the first storage node contact plug. A barrier metal layer, which acts as a third storage node contact plug, may be formed on the second storage node contact plug.

Abstract: This is related to a method for the manufacture of a capacitor with wing extensions and the capacitor device. The method comprises: (1) causing multiple contact areas to be disposed in alternate positions, such that two adjacent contact areas are complements of each other, (2) depositing electroplating base material (EBM) over the contact area, (3) electroplating a conductive material on the sidewalls of the EBM slab to form plate electrode; and then (4) etching back the EBM leaving only the electrode portion. The capacitor formed by the above method has a larger surface area on the electrode compared with that made by the conventional method, and the cell capacitance is also better. This method is especially effective for the manufacture of high-density memory device.

Abstract: A chip interface assembly and method of assembling a chip interface provide enhanced performance. The chip interface assembly includes a semiconductor package and a socket. The semiconductor package has a female contact architecture, where the female contact architecture is mated with a male contact architecture of the socket. By reversing the traditional male/female arrangement of conventional interconnection interfaces, difficulties associated with signaling throughput, clearance, hardware complexity and electrical losses can be obviated.

Abstract: The invention includes a number of methods and structures pertaining to semiconductor circuit technology, including: methods of forming DRAM memory cell constructions; methods of forming capacitor constructions; DRAM memory cell constructions; capacitor constructions; and monolithic integrated circuitry. The invention includes a method of forming a capacitor comprising the following steps: a) forming a mass of silicon material over a node location, the mass comprising exposed doped silicon and exposed undoped silicon; b) substantially selectively forming rugged polysilicon from the exposed undoped silicon and not from the exposed doped silicon; and c) forming a capacitor dielectric layer and a complementary capacitor plate proximate the rugged polysilicon and doped silicon.

Abstract: A semiconductor memory device includes a conductive layer filling a contact hole, a bottom electrode having a depression and electrically connected to the conductive layer, a dielectric film formed on the bottom electrode along the depression, and a top electrode formed on the dielectric film. The conductive layer and the dielectric film directly contact each other at a top surface of the conductive layer. The conductive layer contains polycrystalline silicon and dopant having a relatively low concentration and the bottom electrode contains polycrystalline silicon and dopant having a relatively high concentration. The semiconductor memory device can thus have a capacitor small in size and still sufficiently large in capacitance.

Abstract: A masking and etching technique during the formation of a memory cell capacitor which simultaneously separates storage poly into individual storage poly nodes and etches recesses into the storage poly nodes which increase the surface area of the storage poly nodes and thereby increase the capacitance of a completed memory cell without additional processing steps.

Abstract: A semiconductor device having a capacitor according to the present invention has a storage node and a cell plate opposed to each other through a capacitor dielectric layer, and at least either the storage node or the cell plate is formed to have a mixed crystal layer of SiGe containing a p-type impurity. Thus, a semiconductor device having a capacitor capable of effectively preventing reduction of the capacitance can be obtained.

Abstract: A stacked DRAM cell capacitor having HSG silicon only on a top portion of a storage node, not on a bottom portion thereof. The storage node has a double layer structure including a bottom layer and a top layer. The bottom layer is made of a conductive material that suppresses the growth of HSG seeds. Accordingly, electrical bridges between adjacent storage nodes, particularly at a bottom portion, can be prevented.

Abstract: The new structure of a memory cell which enables avoiding the problem of a step without increasing the number of processes, the structure of a semiconductor integrated circuit in which a common part of the same substrate in a manufacturing process is increased and the structure of the semiconductor integrated circuit which allows measures for environment obstacles without increasing the number of processes are disclosed. Memory cell structure in which a capacitor is formed in the uppermost layer of plural metal wiring layers by connecting the storage node of the capacitor to a diffusion layer via plugs and pads is adopted. It is desirable that a dielectric film formed in a metal wiring layer under the uppermost layer and a supplementary capacitor composed of a storage node and a plate electrode are connected to the capacitor. It is also desirable that the plate electrode of the capacitor covers the chip.

Abstract: A self-aligned vertical transistor DRAM structure comprising a self-aligned trench structure and a self-aligned common-drain structure are disclosed by the present invention, in which the self-aligned trench structure comprises a deep-trench capacitor region having a vertical transistor and a second-type shallow-trench-isolation region being defined by a spacer technique and the self-aligned common-drain structure comprises a common-drain region being defined by another spacer technique. The self-aligned vertical transistor DRAM structure is used to implement two contactless DRAM arrays. A first-type contactless DRAM array comprises a plurality of metal bit-lines integrated with planarized common-drain conductive islands and a plurality of highly conductive word-lines. A second-type contactless DRAM array comprises a plurality of metal word-lines integrated with planarized common-gate conductive islands and a plurality of common-drain conductive bit-lines.

Abstract: A rugged polysilicon electrode for a capacitor has high surface area enhancement with a thin layer by high nucleation density plus gas phase doping which also enhances grain shape and oxygen-free dielectric formation.

Abstract: A storage node of a DRAM cell capacitor includes a first insulating layer in which a bit line pattern is formed, a second insulating layer formed on the first insulating layer of which material is different from that of the second insulating layer, a first conductive layer formed on the second insulating layer that has an etching rate different from that of the first conductive layer, a material layer formed on the first conductive layer, which has a smaller width than the first conductive layer and is made of material with different etching characteristics from that of the first conductive layer, a second conductive layer that is formed on the material layer and has the same width as that of the material layer, and a sidewall conductive spacer that is an contact with the second conductive layer and the material layer and is formed on the top surface of the first conductive layer and on sides of the material layer and the second conductive layer.

Abstract: Disclosed is a container capacitor structure and method of constructing it. An etch mask and etch are used to expose portions of an exterior surface of electrode (“bottom electrodes”) of the container capacitor structure. The etch provides a recess between proximal pairs of container capacitor structures, which recess is available for forming additional capacitance. Accordingly, a capacitor dielectric and a top electrode are formed on and adjacent to, respectively, both an interior surface and portions of the exterior surface of the first electrode. Advantageously, surface area common to both the first electrode and second electrodes is increased over using only the interior surface, which provides additional capacitance without a decrease in spacing for clearing portions of the capacitor dielectric and the second electrode away from a contact hole location.

Abstract: A parallel-plate, voltage-variable capacitor is designed to have an increased current conducting perimeter relative to its area. In one approach, the perimeter is increased by changing the shape of the plates. In another approach, the varactor is implemented by a number of disjoint plates, which are coupled in parallel.

Abstract: The present invention discloses a semiconductor memory device having a bit line and a metal contact stud, wherein the metal contact stud is formed on a different layer from a layer on which the bit lines are formed.

Abstract: A decoupling capacitor is provided for a semiconductor device and may include a first low dielectric insulator layer and a low resistance conductor formed into at least two interdigitized patterns on the surface of the first low dielectric insulator in a single interconnect plane. A high dielectric constant material may be provided between the two patterns. A circuit for testing a plurality of these capacitors is also provided which includes a charge monitoring circuit, a coupling circuit and a control circuit.

Abstract: An active matrix organic electroluminescence display device and a method of fabricating the same are disclosed in the present invention. The device includes gate and data lines defining a pixel region on a substrate, a switching thin film transistor connected to the gate and data lines, a driving thin film transistor connected to the switching thin film transistor, a power line connected to the driving thin film transistor, a transparent first capacitor electrode connected to and overlapping the power line, a second capacitor electrode connected to the driving thin film transistor, and a pixel electrode formed at the pixel region and connected to the driving thin film transistor.

Abstract: A method of forming a ferroelectric capacitor includes forming a lower electrode on a substrate. The lower electrode is oxidized to form a metal oxide film. A ferroelectric film is formed on the metal oxide film while reduction of the oxygen content of the metal oxide film is inhibited. An upper electrode is formed on the ferroelectric film.

Abstract: The method of forming a ferroelectric memory device includes forming capacitor patterns over a substrate, each capacitor pattern having an adhesive assistant pattern, a lower electrode, a ferroelectric pattern, and an upper electrode. An oxygen barrier layer is formed over the substrate and is etched to expose a sidewall of the ferroelectric pattern but not a sidewall of the adhesive assistant pattern. Then, a thermal process for curing ferroelectricity of the ferroelectric pattern is performed.

Abstract: The present invention provides a memory cell and method for forming the same that results in improved cell density without overly increasing fabrication cost and complexity. The preferred embodiment of the present invention provides a fin design to form the memory cell. Specifically, a fin Field Effect Transistor (FET) is formed to provide the access transistor, and a fin capacitor is formed to provide the storage capacitor. By forming the memory cell with a fin FET and fin capacitor, the memory cell density can be greatly increased over traditional planar capacitor designs. Additionally, the memory cell can be formed with significantly less process cost and complexity than traditional deep trench capacitor designs.

Abstract: Capacitance for MIM capacitors is increased by connecting another interdigitated pattern at the poly level in parallel with overlying patterns at the metal levels. The poly layout is optimized to maximize intralevel capacitive coupling through sidewall nitride.