Additional Control Electrode Is Doped Region In Semiconductor Substrate Patents (Class 257/318)
  • Patent number: 12010843
    Abstract: According to an embodiment, a non-volatile storage device includes a first layer, a second layer formed on the first layer, a stacked body including a plurality of conductive films stacked on the second layer, and a semiconductor pillar which penetrates the stacked body and the second layer and reaches the first layer. The semiconductor pillar includes a semiconductor film formed along an extending direction of the semiconductor pillar, and a memory film which covers a periphery of the semiconductor film. The memory film includes a first portion formed between the stacked body and the semiconductor film and a second portion formed between the second layer and the semiconductor film. An outer periphery of the second portion in a plane perpendicular to the extending direction is wider than an outer periphery of the first portion on a second layer side of the stacked body.
    Type: Grant
    Filed: March 18, 2021
    Date of Patent: June 11, 2024
    Assignee: Kioxia Corporation
    Inventors: Masaaki Higuchi, Masaru Kito, Masao Shingu
  • Patent number: 11729961
    Abstract: Asymmetric, semiconductor memory cells, arrays, devices and methods are described. Among these, an asymmetric, bi-stable semiconductor memory cell is described that includes: a floating body region configured to be charged to a level indicative of a state of the memory cell; a first region in electrical contact with the floating body region; a second region in electrical contact with the floating body region and spaced apart from the first region; and a gate positioned between the first and second regions, such that the first region is on a first side of the memory cell relative to the gate and the second region is on a second side of the memory cell relative to the gate; wherein performance characteristics of the first side are different from performance characteristics of the second side.
    Type: Grant
    Filed: September 6, 2021
    Date of Patent: August 15, 2023
    Assignee: Zeno Semiconductor, Inc.
    Inventor: Yuniarto Widjaja
  • Patent number: 11417394
    Abstract: Methods, systems, and devices for decoding for a memory device are described. A decoder of a memory device may include transistors in a first layer between a memory array and a second layer that includes one or more components associated with the memory array. The second layer may include CMOS pre-decoding circuitry, among other components. The decoder may include CMOS transistors in the first layer. The CMOS transistors may control which voltage source is coupled with an access line based on a gate voltage applied to a p-type transistor and a n-type transistor. For example, a first gate voltage applied to a p-type transistor may couple a source node with the access line and bias the access line to a source voltage. A second gate voltage applied to the n-type transistor may couple a ground node with the access line and bias the access line to a ground voltage.
    Type: Grant
    Filed: December 11, 2020
    Date of Patent: August 16, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Lorenzo Fratin, Paolo Fantini, Fabio Pellizzer, Thomas M. Graettinger
  • Patent number: 11275885
    Abstract: A semiconductor cell structure includes four transistors, two gate-strips, four pairs of conductive segments, and a plurality of horizontal routing lines. Each of the two gate-strips intersects a first-type active zone and a second-type active zone. A first conductive segment is configured to have a first supply voltage. A second conductive segment is configured to have a second supply voltage. The first gate-strip is conductively connected to the second conductive segment. Each of the horizontal routing lines intersects one or more conductive segments over one or more corresponding intersections while conductively isolated from the one or more conductive segments at each of the one or more corresponding intersections.
    Type: Grant
    Filed: October 27, 2020
    Date of Patent: March 15, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shun Li Chen, Li-Chun Tien, Ting Yu Chen, Wei-Ling Chang
  • Patent number: 10932362
    Abstract: A circuit board according to an embodiment of the present invention comprises: a first metal layer; an insulating layer disposed on the first metal layer and comprising boron nitride agglomerate particles coated with a resin; and a second metal layer disposed on the insulating layer, wherein: one of both surfaces of the first metal layer, on which the insulating layer is disposed, is in at least partial contact with one surface of the insulating layer; one of both surfaces of the second metal layer, on which the insulating layer is disposed, is in at least partial contact with the other surface of the insulating layer; a plurality of grooves are formed on a surface which is one of both surfaces of at least one of the first metal layer and the second metal layer and which has the insulating layer disposed thereon; at least some of the particles are arranged in at least some of the plurality of grooves; the width (W) of at least one of the plurality of grooves is 1 to 1.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: February 23, 2021
    Assignee: LG INNOTEK CO., LTD.
    Inventors: Jong Sik Lee, Jin A Gu, Soo Jung Yoon, Gyung Seok Lee, Hyun Gu Im
  • Patent number: 10922605
    Abstract: A neuron circuit can switch between two functions: as an input neuron circuit, and as a hidden neuron circuit. An error circuit can switch between two functions: as a hidden error circuit, and as an output neuron circuit. A switching circuit is configured to be capable of changing the connections between the neuron circuit, a synapse circuit, and the error circuit. The synapse circuit includes an analog memory that stores data that corresponds to the connection strength between the input neuron circuit and the hidden neuron circuit or between the hidden neuron circuit and the output neuron circuit, a writing circuit that changes the data in the analog memory, and a weighting circuit that weights an input signal in reaction to the data of the analog memory and outputs the weighted output signal. The analog memory includes a transistor comprising an oxide semiconductor with extremely low off-state current.
    Type: Grant
    Filed: October 18, 2016
    Date of Patent: February 16, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yoshiyuki Kurokawa
  • Patent number: 10879257
    Abstract: The present disclosure relates to a method of forming an embedded flash memory cell that provides for improved performance by providing for a tunnel dielectric layer having a relatively uniform thickness, and an associated apparatus. The method is performed by forming a charge trapping dielectric structure over a logic region, a control gate region, and a select gate region within a substrate. A first charge trapping dielectric etching process is performed to form an opening in the charge trapping dielectric structure over the logic region, and a thermal gate dielectric layer is formed within the opening. A second charge trapping dielectric etching process is performed to remove the charge trapping dielectric structure over the select gate region. Gate electrodes are formed over the thermal gate dielectric layer and the charge trapping dielectric structure remaining after the second charge trapping dielectric etching process.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: December 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jui-Yu Pan, Cheng-Bo Shu, Chung-Jen Huang, Jing-Ru Lin, Tsung-Yu Yang, Yun-Chi Wu, Yueh-Chieh Chu
  • Patent number: 10818785
    Abstract: A charge sensing device for sensing charge variations in a charge storage area includes: a TFET having at least one sense gate; and a capacitive coupling for coupling the charge storage area with the sense gate.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: October 27, 2020
    Assignee: ECOLE POLYTECHNIQUE FEDERALE DE LAUSANNE (EPFL)
    Inventors: Cem Alper, Mihai Adrian Ionescu, Teodor Rosca
  • Patent number: 10468425
    Abstract: A non-volatile memory includes cells arranged in rows and columns. Each memory cell includes an access portion and a control portion. The access and control portions share an electrically floating layer of conductive material defining a first capacitive coupling with the access portion and a second capacitive coupling with the control portion. The first capacitive coupling defines a first capacity lower than a second capacity defined by the second capacitive coupling. The control portion is configured so that an electric current extracts charge carriers from the electrically floating layer through Fowler-Nordheim tunneling to store a first logic value in the memory cell. The access portion is configured so that an electric current injects charge carriers in the electrically floating layer by injection of band-to-band tunneling-induced hot electrons to store a second logic value, respectively, in the memory cell.
    Type: Grant
    Filed: January 26, 2015
    Date of Patent: November 5, 2019
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Luca Milani, Fabrizio Torricelli, Anna Richelli, Luigi Colalongo, Zsolt Miklos KovĂ cs-Vajna
  • Patent number: 10347784
    Abstract: A semiconductor device includes a semiconductor structure formed on a substrate, a gate dielectric formed on a first side of the semiconductor structure, and a dielectric layer formed on a second side of the semiconductor structure.
    Type: Grant
    Filed: April 26, 2018
    Date of Patent: July 9, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Xin Miao, Wenyu Xu, Chen Zhang
  • Patent number: 10325964
    Abstract: The present disclosure relates to an organic light emitting device including a logic device that comprises a dummy pattern and a merged spacer, and an associated fabrication method. In some embodiments, the organic light emitting device is disposed over a substrate. The logic device is coupled to the organic light emitting device, and comprises a pair of source/drain regions disposed within the substrate and separated by a channel region. A gate structure overlies the channel region and comprises a gate electrode and a dummy pattern separated from the gate electrode by a merged spacer. By arranging the dummy pattern and the merged spacer between the gate electrode and the source/drain regions, a distance between the gate electrode and the source/drain region is enlarged, and therefore reducing the gate induced drain leakage (GIDL) effect.
    Type: Grant
    Filed: November 15, 2016
    Date of Patent: June 18, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Huan Chen, Fu-Jier Fan, Kong-Beng Thei, Ker-Hsiao Huo, Li-Hsuan Yeh, Yu-Bin Zhao
  • Patent number: 10283510
    Abstract: A semiconductor structure includes a semiconductor substrate, at least one raised dummy feature, at least one memory cell, and at least one word line. The raised dummy feature is present on the semiconductor substrate and defines a cell region on the semiconductor substrate. The memory cell is present on the cell region. The word line is present adjacent to the memory cell.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: May 7, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chiang-Ming Chuang, Chien-Hsuan Liu, Chih-Ming Lee, Kun-Tsang Chuang, Hung-Che Liao, Hsin-Chi Chen
  • Patent number: 10249378
    Abstract: This invention introduces a flash memory device and a method which are capable of quickly recovering the over-erased memory cells while preventing adverse influence to normal cells that are not over-erased. The flash memory device comprises a memory array and a memory controller coupled to the memory array. The memory controller is configured to select a memory block which comprises at least one over-erased memory cell. The memory controller is further configured to apply a negative voltage to the common bulk line and the common source line of the selected memory block. The memory controller is further configured apply a positive voltage to word lines that are coupled to the at least one over-erased memory cell in the selected memory block, and apply the positive voltage to word lines that are not coupled to any one of the at least one over-erased memory cell in the selected memory block.
    Type: Grant
    Filed: November 9, 2017
    Date of Patent: April 2, 2019
    Assignee: Winbond Electronics Corp.
    Inventor: Im-Cheol Ha
  • Patent number: 10102911
    Abstract: A non-volatile semiconductor memory device in which, while voltage from a first control line is applied, as a memory gate voltage, to a sub control line through a switching transistor, another switching transistor can block voltage application to a corresponding sub control line. Thus, while a plurality of memory cells are arranged in one direction along the first control line, the number of memory cells to which a memory gate voltage is applied can reduced by the switching transistor, which reduces the occurrence of disturbance, accordingly. The sub control line to which the memory gate voltage is applied from the first control line is used as the gates of memory transistors, and thus the sub control line and the gates are disposed in a single wiring layer, thereby achieving downsizing as compared to a case in which the sub control line and the gates are disposed in separate wiring layers.
    Type: Grant
    Filed: December 11, 2015
    Date of Patent: October 16, 2018
    Assignee: FLOADIA CORPORATION
    Inventors: Hideo Kasai, Yasuhiro Taniguchi, Yutaka Shinagawa, Ryotaro Sakurai, Yasuhiko Kawashima, Kosuke Okuyama
  • Patent number: 10048893
    Abstract: An electronic circuit includes transmit-side circuitry and receive-side circuitry. The transmit-side circuitry belongs to a first domain of the circuit and is configured to transmit a data signal from the first domain to a second domain of the circuit. The receive-side circuitry belongs to the second domain and is configured to receive the transmitted data signal. The receive-side circuitry is configured to transfer to the transmit-side circuitry a read pointer value indicative of a readout position in a buffer memory that buffers the data signal, and to retain the read pointer value in a non-volatile element that is accessible to the transmit-side circuitry.
    Type: Grant
    Filed: May 7, 2015
    Date of Patent: August 14, 2018
    Assignee: APPLE INC.
    Inventors: Mark Goikhman, Tzach Zemer
  • Patent number: 9899395
    Abstract: A semiconductor device includes a pair of erase gate lines, a pair of control gate lines and a pair of word lines. The pair of control gate lines are disposed on the erase gate lines. Each one of the control gate lines includes a plurality of segments between which portions of one of the pair of erase gate lines are seen in a plan view. In a plan view of the semiconductor device, the pair of word lines are disposed between the control gate lines and extending along edges of the control gate lines.
    Type: Grant
    Filed: July 26, 2016
    Date of Patent: February 20, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Ming Lee, Po-Wei Liu, Chiang-Ming Chuang, Yung-Lung Hsu, Hsin-Chi Chen
  • Patent number: 9874856
    Abstract: An EEPROM memory cell includes a dual-gate MOS transistor in which the two gates are separated by an insulation layer. The insulation layer includes a first portion and a second portion having lower insulation properties than the first one. The second portion is located at least partially above a channel region of the transistor.
    Type: Grant
    Filed: October 14, 2015
    Date of Patent: January 23, 2018
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Pascal Fornara
  • Patent number: 9859190
    Abstract: Provided herein is a resin structure having high heat dissipation, and desirable adhesion at the interface with a heat generating device. The resin structure is provided on a substrate to dissipates heat of the substrate to outside, and includes: a water-based coating material layer provided on the substrate and including a water-based coating material, and fillers having an average particle size of 30 ?m to 150 ?m; and a resin layer provided on the water-based coating material layer and containing a thermosetting resin. The fillers have a far-infrared emissivity of 0.8 or more, and an average aspect ratio of 1 to 12 as measured as a ratio of lengths along the long axis and the short axis through the center of gravity of the fillers. At least 80% of the total number of fillers has a length that is at least 1.
    Type: Grant
    Filed: January 18, 2017
    Date of Patent: January 2, 2018
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Honami Nawa, Hirohisa Hino
  • Patent number: 9768182
    Abstract: A semiconductor structure includes a semiconductor substrate, at least one raised dummy feature, at least one memory cell, and at least one word line. The raised dummy feature is present on the semiconductor substrate and defines a cell region on the semiconductor substrate. The memory cell is present on the cell region. The word line is present adjacent to the memory cell.
    Type: Grant
    Filed: May 18, 2016
    Date of Patent: September 19, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chiang-Ming Chuang, Chien-Hsuan Liu, Chih-Ming Lee, Kun-Tsang Chuang, Hung-Che Liao, Hsin-Chi Chen
  • Patent number: 9659951
    Abstract: A single poly nonvolatile memory (NVM) cell includes first and second active regions disposed to face each other and third and fourth active regions spaced apart from the first and second active regions. A drain region, a junction region and a source region are disposed in the fourth active region. A floating gate is disposed on the first and second active regions and is disposed to extend onto the third and fourth active regions. A read/selection gate is disposed to cross the fourth active region between the drain region and the junction region. The first active region is coupled to a first array control gate line, and the second active region is coupled to a second array control gate line. The source region, the junction region and the floating gate constitute a floating gate transistor. The drain region, the junction region and the read/selection gate constitute a read/selection transistor.
    Type: Grant
    Filed: July 12, 2016
    Date of Patent: May 23, 2017
    Assignee: SK Hynix Inc.
    Inventor: Jeong Hoon Kim
  • Patent number: 9599587
    Abstract: An ISFET includes a control gate coupled to a floating gate in a CMOS device. The control gate, for example, a poly-to-well capacitor, is configured to receive a bias voltage and effect movement of a trapped charge between the control gate and the floating gate. The threshold voltage of the ISFET can therefore by trimmed to a predetermined value, thereby storing the trim information (the amount of trapped charge in the floating gate) within the ISFET itself.
    Type: Grant
    Filed: September 5, 2014
    Date of Patent: March 21, 2017
    Assignee: NXP USA, INC.
    Inventors: Patrice M. Parris, Weize Chen, Richard J. De Souza, Md M. Hoque, John M. McKenna
  • Patent number: 9520160
    Abstract: A memory module includes a plurality of semiconductor memory devices and a circuit board. The circuit board is electrically connected to the plurality of semiconductor memory devices, and a signal line is disposed in the outermost layer of the circuit board. An electrical reference for the signal line is provided in a layer of the circuit board that is not adjacent to the outermost layer. Accordingly, an impedance of the signal line may be increased, and signal integrity of a signal transmitted through the signal line may be improved.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: December 13, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chil-Nam Yoon, Seon-Ryeong Kang, Hui-Chong Shin
  • Patent number: 9485877
    Abstract: A structure for which the electrical reliability is improved is provided. A structure in accordance with one embodiment includes an inorganic insulating layer including amorphous silicon oxide and having an elastic modulus which is 45 GPa or less. A method for manufacturing a structure in accordance with one embodiment includes applying an inorganic insulating sol including inorganic insulating particles composed of amorphous silicon oxide, and forming an inorganic insulating layer including amorphous silicon oxide and having an elastic modulus which is 45 GPa or less by heating the inorganic insulating particles at a temperature lower than a crystallization onset temperature of silicon oxide to each other.
    Type: Grant
    Filed: September 28, 2010
    Date of Patent: November 1, 2016
    Assignee: KYOCERA CORPORATION
    Inventor: Katsura Hayashi
  • Patent number: 9450052
    Abstract: An EEPROM memory cell with a coupler region is disclosed. The coupler region has a well and at least one feeder region formed in the well. The at least one feeder region is configured to provide majority carriers to a channel region defined in the well so that a portion of the channel region adjoining the top surface of the coupler region is inverted during an erase operation.
    Type: Grant
    Filed: July 1, 2015
    Date of Patent: September 20, 2016
    Assignee: CHENGDU MONOLITHIC POWER SYSTEMS CO., LTD.
    Inventors: Albert Bergemont, Eric Braun, Joel M. McGregor
  • Patent number: 9437697
    Abstract: A semiconductor device includes a device isolation region defining an active region in a substrate, and gate structures buried in the active region of the substrate. At least one of the gate structures includes a gate trench, a gate insulating layer conformally formed on an inner wall of the gate trench, a gate barrier pattern conformally formed on the gate insulating layer disposed on a lower portion of the gate trench, a gate electrode pattern formed on the gate barrier pattern and filling the lower portion of the gate trench, an electrode protection layer conformally formed on the gate insulating layer disposed on an upper portion of the gate trench to be in contact with the gate barrier pattern and the gate electrode pattern, a buffer oxide layer conformally formed on the electrode protection layer, and a gate capping insulating layer formed on the buffer oxide layer to fill the upper portion of the gate trench.
    Type: Grant
    Filed: November 24, 2014
    Date of Patent: September 6, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Min-Hee Cho
  • Patent number: 9424924
    Abstract: A non-volatile semiconductor memory device is proposed that has an unprecedented novel structure in which carriers can be injected into a floating gate by applying various voltages of the same polarity.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: August 23, 2016
    Assignee: Floadia Corporation
    Inventors: Yasuhiro Taniguchi, Kosuke Okuyama
  • Patent number: 9373613
    Abstract: Disclosed herein are systems and method for voltage clamping in semiconductor circuits using through-silicon via (TSV) positioning. A semiconductor die is disclosed that includes a silicon substrate, a bipolar transistor having collector, emitter, base and sub-collector regions disposed on the substrate, and a through-silicon via (TSV) positioned within 35 ?m of the sub-collector region in order to clamp a peak voltage of the bipolar transistor at a voltage limit level.
    Type: Grant
    Filed: December 23, 2014
    Date of Patent: June 21, 2016
    Assignee: Skyworks Solutions, Inc.
    Inventors: Anthony Francis Quaglietta, Michael Joseph McPartlin
  • Patent number: 9202759
    Abstract: A semiconductor manufacturing method includes exposing on a photoresist film a first partial pattern of a contact hole, overlapping a part of a gate interconnection in alignment with an alignment mark formed simultaneously with forming the gate interconnection, exposing on the photoresist film a second partial pattern, overlapping a part of an active region in alignment with an alignment mark formed simultaneously with forming the active region, developing the photoresist film to form an opening at the portion where the first partial pattern and the second partial pattern have been exposed, and etching an insulation film to form a contact hole down to the gate interconnection and the source/drain diffused layer.
    Type: Grant
    Filed: February 27, 2014
    Date of Patent: December 1, 2015
    Assignee: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Masaki Okuno, Hajime Yamamoto
  • Patent number: 9196363
    Abstract: Provided is a semiconductor device having improved performance. The semiconductor device includes the memory cells of a flash memory. Each of the memory cells includes a capacitor element for writing/erasing data having a gate electrode formed of a part of a floating gate electrode, and a MISFET for reading data having a gate electrode formed of another part of the floating gate electrode. The capacitor element for writing/erasing data has a p-type semiconductor region and an n-type semiconductor region which have opposite conductivity types. The length of the floating gate electrode in a gate length direction in the capacitor element for writing/erasing data is smaller than the length of the floating gate electrode in the gate length direction in the MISFET for reading data.
    Type: Grant
    Filed: December 29, 2014
    Date of Patent: November 24, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Hideaki Yamakoshi, Daisuke Okada
  • Patent number: 9142667
    Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes: forming a plurality of trenches; forming a gate insulating film; burying a gate electrode; burying an insulating member; projecting the insulating member; forming a base layer; forming a mask film; forming a first semiconductor layer; forming a carrier ejection layer; forming a first electrode; and forming a second electrode. The projecting includes projecting the insulating member from the upper surface of the semiconductor substrate by removing an upper layer portion of the semiconductor substrate. The mask film is formed so as to cover the projected insulating member. The forming the first semiconductor layer includes forming a first semiconductor layer of the first conductivity type in an upper layer portion of the base layer by doping the base layer with impurity, the upper layer portion having a lower surface below an upper end of the gate electrode.
    Type: Grant
    Filed: September 12, 2014
    Date of Patent: September 22, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hideki Okumura, Hiroto Misawa, Takahiro Kawano
  • Patent number: 9048137
    Abstract: Scalable Gate Logic Non-Volatile Memory (SGLNVM) devices fabricated with the conventional CMOS process is disclosed. Floating gates of SGLNVM with the minimal length and width of the logic gate devices form floating gate Metal-Oxide-Semiconductor Field Effect Transistor. The floating gates with the minimal gate length extend over silicon active areas to capacitively couple control gates embedded in silicon substrate (well) through an insulation dielectric. The embedded control gate is formed by a shallow semiconductor type opposite to the type of the silicon substrate or well. Plurality of SGLNVM devices are configured into a NOR-type flash array where a pair of SGLNVM devices share a common source electrode connected to a common ground line with two drain electrodes connected to two separate bitlines. The pairs of the NOR-type SGLNVM cells are physically separated and electrically isolated by dummy floating gates to minimize cell sizes.
    Type: Grant
    Filed: February 17, 2012
    Date of Patent: June 2, 2015
    Assignee: FLASHSILICON INCORPORATION
    Inventor: Lee Wang
  • Patent number: 9040971
    Abstract: A thin film transistor (TFT) that includes a control electrode, a semiconductor pattern, a first input electrode, a second input electrode, and an output electrode is disclosed. in one aspect, the semiconductor pattern includes a first input area, a second input area, a channel area, and an output area. The channel area is formed between the first input area and the output area and overlapped with the control electrode to be insulated from the control electrode. The second input area is formed between the first input area and the channel area and doped with a doping concentration different from a doping concentration of the first input areas. The second input electrode makes contact with the second input area and receives a control voltage to control a threshold voltage.
    Type: Grant
    Filed: September 24, 2013
    Date of Patent: May 26, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventor: Yong Soo Lee
  • Patent number: 9006814
    Abstract: A semiconductor memory device includes a substrate including a cell region and a peripheral region, word lines on the substrate of the cell region, each of the word lines including a charge storing part and a control gate electrode sequentially stacked, and a peripheral gate pattern on the substrate of the peripheral region. Each of the control gate electrode and the peripheral gate pattern includes a high-carbon semiconductor pattern and a low-carbon semiconductor pattern, the low-carbon semiconductor pattern being on the high-carbon semiconductor pattern.
    Type: Grant
    Filed: May 29, 2014
    Date of Patent: April 14, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jae-Hwang Sim
  • Patent number: 8941167
    Abstract: An erasable programmable single-poly nonvolatile memory includes a first PMOS transistor comprising a select gate, a first p-type doped region, and a second p-type doped region, wherein the select gate is connected to a select gate voltage, and the first p-type doped region is connected to a source line voltage; a second PMOS transistor comprising the second p-type doped region, a third p-type doped region, and a floating gate, wherein the third p-type doped region is connected to a bit line voltage; and an erase gate region adjacent to the floating gate, wherein the erase gate region is connected to an erase line voltage.
    Type: Grant
    Filed: March 8, 2012
    Date of Patent: January 27, 2015
    Assignee: Ememory Technology Inc.
    Inventors: Wei-Ren Chen, Te-Hsun Hsu, Shih-Chen Wang, Hsin-Ming Chen, Ching-Sung Yang
  • Patent number: 8933516
    Abstract: A three-dimensional nonvolatile memory array includes a select layer that selectively connects vertical bit lines to horizontal bit lines. Individual select switches of the select layer include two separately controllable transistors that are connected in series between a horizontal bit line and a vertical bit line. Each transistor in a select switch is connected to a different control circuit by a different select line.
    Type: Grant
    Filed: June 24, 2013
    Date of Patent: January 13, 2015
    Assignee: SanDisk 3D LLC
    Inventors: Ming-Che Wu, Wei-Te Wu, Yung-Tin Chen
  • Patent number: 8932931
    Abstract: Aspects of the invention provide a method of forming a bipolar junction transistor. The method includes: providing a semiconductor substrate including a uniform silicon nitride layer over an emitter pedestal, and a base layer below the emitter pedestal; applying a photomask at a first end and a second end of a base region; and performing a silicon nitride etch with the photomask to simultaneously form silicon nitride spacers adjacent to the emitter pedestal and exposing the base region of the bipolar junction transistor. The silicon nitride etch may be an end-pointed etch.
    Type: Grant
    Filed: February 13, 2012
    Date of Patent: January 13, 2015
    Assignee: International Business Machines Corporation
    Inventors: Margaret A. Faucher, Paula M. Fisher, Thomas H. Gabert, Joseph P. Hasselbach, Qizhi Liu, Glenn C. MacDougall
  • Patent number: 8921916
    Abstract: A single poly electrically erasable programmable read only memory (single poly EEPROM) device is provided, including: a semiconductor on insulator (SOI) substrate having a P-type semiconductor layer over an insulator layer; a P-well region formed in a portion of the P-type semiconductor layer; a trench isolation formed in the P-type semiconductor layer, surrounding the P-well region; an NMOS transistor formed over a portion of the P-type semiconductor layer of the P-well region; a P+ doping region formed over another portion of the P-type semiconductor layer of the P-well region; and a control gate formed in another portion of the P-type semiconductor layer, adjacent to the trench isolation.
    Type: Grant
    Filed: November 9, 2012
    Date of Patent: December 30, 2014
    Assignee: Vanguard International Semiconductor Corporation
    Inventor: Chih-Jen Huang
  • Patent number: 8921922
    Abstract: This technology relates to a nonvolatile memory device and a method for fabricating the same. The nonvolatile memory device may include a pipe connection gate electrode configured to have a lower part buried in a groove formed in a substrate, one or more pipe channel layers formed within the pipe connection gate electrode, pairs of main channel layers each coupled with the pipe channel layer and extended in a direction substantially perpendicular to the substrate; and a plurality of interlayer insulating layers and a plurality of cell gate electrodes alternately stacked along the main channel layers. In accordance with this technology, a lower part of the pipe connection gate electrode is buried in the substrate. Accordingly, electric resistance may be reduced because the pipe connection gate electrode may have an increased volume without a substantial increase of the height.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: December 30, 2014
    Assignee: SK Hynix Inc.
    Inventors: Min-Soo Kim, Young-Jin Lee, Sung-Jin Whang
  • Patent number: 8890228
    Abstract: Provided are a semiconductor device and a method of manufacturing the same. The semiconductor device includes: a memory array on a first substrate; and a peripheral circuit on a second substrate, wherein the first substrate and the second substrate may be attached to each other so that the memory array and the peripheral circuit are electrically connected to each other.
    Type: Grant
    Filed: November 21, 2008
    Date of Patent: November 18, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Myoung-jae Lee, Young-soo Park, Chang-bum Lee, Seung-eon Ahn, Ki-hwan Kim, Bo-soo Kang
  • Patent number: 8872249
    Abstract: The technology of the present invention relates to a non-volatile memory device and a fabrication method thereof. The non-volatile memory device includes channel layers protruding vertically from a substrate, a plurality of hole-supply layers and a plurality of gate electrodes, which are alternately stacked along the channel layers, and a memory film interposed between the channel layers and the gate electrodes and between the hole-supply layers and the gate electrodes. According to this technology, the hole-supply layers are formed between the memory cells such that sufficient holes are supplied to the memory cells during the erase operation of the memory cells, whereby the erase operation of the memory cells is smoothly performed without using the GIDL current, and the properties of the device are protected from being deteriorated due to program/erase cycling.
    Type: Grant
    Filed: September 5, 2012
    Date of Patent: October 28, 2014
    Assignee: SK Hynix Inc.
    Inventor: Sung-Wook Jung
  • Patent number: 8816421
    Abstract: According to one exemplary implementation, a semiconductor device includes a channel, a source, and a drain situated in a first semiconductor fin. The channel is situated between the source and the drain. The semiconductor device also includes a control gate situated in a second semiconductor fin. A floating gate is situated between the first semiconductor fin and the second semiconductor fin. The semiconductor device can further include a first dielectric region situated between the floating gate and the first semiconductor fin and a second dielectric region situated between the floating gate and the second semiconductor fin.
    Type: Grant
    Filed: April 30, 2012
    Date of Patent: August 26, 2014
    Assignee: Broadcom Corporation
    Inventors: Frank Hui, Neal Kistler
  • Patent number: 8759900
    Abstract: A semiconductor memory device includes a substrate including a cell region and a peripheral region, word lines on the substrate of the cell region, each of the word lines including a charge storing part and a control gate electrode sequentially stacked, and a peripheral gate pattern on the substrate of the peripheral region. Each of the control gate electrode and the peripheral gate pattern includes a high-carbon semiconductor pattern and a low-carbon semiconductor pattern, the low-carbon semiconductor pattern being on the high-carbon semiconductor pattern.
    Type: Grant
    Filed: January 16, 2013
    Date of Patent: June 24, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jae-Hwang Sim
  • Patent number: 8748967
    Abstract: An aspect of the present embodiment, there is provided a semiconductor device, including a semiconductor substrate, a first insulator above the semiconductor substrate, the first insulator containing tungsten, germanium and silicon, a charge storage film on the first insulator, a second insulator on the charge storage film and, a control gate electrode on the second insulator.
    Type: Grant
    Filed: February 27, 2013
    Date of Patent: June 10, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kenichiro Toratani, Masayuki Tanaka
  • Patent number: 8716780
    Abstract: A memory device includes a planar substrate, a plurality of horizontal conductive planes above the planar substrate, and a plurality of horizontal insulating layers interleaved with the plurality of horizontal conductive planes. An array of vertical conductive columns, perpendicular to the pluralities of conductive planes and insulating layers, passes through apertures in the pluralities of conductive planes and insulating layers. The memory device includes a plurality of programmable memory elements, each of which couples one of the horizontal conductive planes to a respective vertical conductive column.
    Type: Grant
    Filed: August 26, 2010
    Date of Patent: May 6, 2014
    Assignee: Rambus Inc.
    Inventors: Mark D. Kellam, Gary B. Bronner
  • Patent number: 8710575
    Abstract: A semiconductor device is formed in a semiconductor substrate comprising a first main surface and includes a control gate disposed in a lower portion of a first trench formed in the first main surface, a floating gate disposed in the first trench above the control gate and insulated from the control gate, a source region of a first conductivity type, a body region of a second conductivity type, and a drain region of the first conductivity type.
    Type: Grant
    Filed: January 31, 2013
    Date of Patent: April 29, 2014
    Assignee: Infineon Technologies AG
    Inventors: Andreas Meiser, Werner Schwetlick
  • Publication number: 20140097483
    Abstract: A 3-D Single Floating Gate Non-Volatile Memory (SFGNVM) device based on the 3-D fin Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) is disclosed. The disclosed Non-Volatile Memory (NVM) device consists of a pair of semiconductor fins and one floating metal gate. The floating metal gate for storing electrical charges to alter the threshold voltage of the fin MOSFET crosses over the pair of semiconductor fins on top of coupling and tunneling dielectrics above the surfaces of the two semiconductor fins. One semiconductor fin with the same type impurity forms the control gate of the non-volatile memory device. The other semiconductor fin is doped with opposite type of impurity in the channel regions under the metal floating gate and with the same type of impurity in the source and drain regions on the sides of the crossed metal floating gate.
    Type: Application
    Filed: October 4, 2012
    Publication date: April 10, 2014
    Applicant: FLASHSILICON INCORPORATION
    Inventor: Lee WANG
  • Patent number: 8664712
    Abstract: The invention relates to a flash memory cell having a FET transistor with a floating gate on a semiconductor-on-insulator (SOI) substrate composed of a thin film of semiconductor material separated from a base substrate by an insulating buried oxide (BOX) layer, The transistor has in the thin film, a channel, with two control gates, a front control gate located above the floating gate and separated from it by an inter-gate dielectric, and a back control gate located within the base substrate directly under the insulating (BOX) layer and separated from the channel by only the insulating (BOX) layer. The two control gates are designed to be used in combination to perform a cell programming operation. The invention also relates to a memory array made up of a plurality of memory cells according to the first aspect of the invention, which can be in an array of rows and columns, and a method of fabricating such memory cells and memory arrays.
    Type: Grant
    Filed: November 15, 2010
    Date of Patent: March 4, 2014
    Assignee: Soitec
    Inventors: Carlos Mazure, Richard Ferrant
  • Patent number: 8659069
    Abstract: A method of forming a gate structure includes forming a tunnel insulation layer pattern on a substrate, forming a floating gate on the tunnel insulation layer pattern, forming a dielectric layer pattern on the floating gate, the dielectric layer pattern including a first oxide layer pattern, a nitride layer pattern on the first oxide layer pattern, and a second oxide layer pattern on the nitride layer pattern, the second oxide layer pattern being formed by performing an anisotropic plasma oxidation process on the nitride layer, such that a first portion of the second oxide layer pattern on a top surface of the floating gate has a larger thickness than a second portion of the second oxide layer pattern on a sidewall of the floating gate, and forming a control gate on the second oxide layer.
    Type: Grant
    Filed: December 30, 2011
    Date of Patent: February 25, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-Hwan Kim, Sung-Ho Heo, Jae-Ho Choi, Hun-Hyeong Lim, Ki-Hyun Hwang, Woo-Sung Lee
  • Patent number: 8610193
    Abstract: Some embodiments include methods of forming semiconductor constructions. Alternating layers of n-type doped material and p-type doped material may be formed. The alternating layers may be patterned into a plurality of vertical columns that are spaced from one another by openings. The openings may be lined with tunnel dielectric, charge-storage material and blocking dielectric. Alternating layers of insulative material and conductive control gate material may be formed within the lined openings. Some embodiments include methods of forming NAND unit cells. Columns of alternating n-type material and p-type material may be formed. The columns may be lined with a layer of tunnel dielectric, a layer of charge-storage material, and a layer of blocking dielectric. Alternating layers of insulative material and conductive control gate material may be formed between the lined columns. Some embodiments include semiconductor constructions, and some embodiments include NAND unit cells.
    Type: Grant
    Filed: February 12, 2013
    Date of Patent: December 17, 2013
    Assignee: Micron Technology Inc.
    Inventor: D. V. Nirmal Ramaswamy
  • Patent number: 8592979
    Abstract: A conductive pattern structure includes a first insulating interlayer on a substrate, metal wiring on the first insulating interlayer, a second insulating interlayer on the metal wiring, and first and second metal contacts extending through the second insulating interlayer. The first metal contacts contact the metal wiring in a cell region and the second metal contact contacts the metal wiring in a peripheral region. A third insulating interlayer is disposed on the second insulating interlayer. Conductive segments extend through the third insulating interlayer in the cell region and contact the first metal contacts. Another conductive segment extends through the third insulating interlayer in the peripheral region and contacts the second metal contact. The structure facilitates the forming of uniformly thick wiring in the cell region using an electroplating process.
    Type: Grant
    Filed: April 5, 2012
    Date of Patent: November 26, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hei-Seung Kim, Gil-Heyun Choi, Ji-Soon Park, Jong-Myeong Lee