Abstract: A flash memory structure having high coupling ratio and the manufacturing method thereof are provided.

Abstract: The integration period of an imaging cell, or the time that an imaging cell is exposed to light energy, is substantially increased by utilizing a single-poly, electrically-programmable, read-only-memory (EPROM) structure to capture the light energy. Photogenerated electrons are formed in the channel region of the EPROM structure from the light energy. The photogenerated electrons are then accelerated into having ionizing collisions which, in turn, leads to electrons being injected onto the floating gate of the EPROM structure at a rate that is proportionate to the number of photons captured by the channel region.

Abstract: According to one exemplary embodiment, a method for fabricating a floating gate memory array comprises a step of removing a dielectric material from an isolation region situated in a substrate to expose a trench, where the trench is situated between a first source region and a second source region, where the trench defines sidewalls in the substrate. The method further comprises implanting an N type dopant in the first source region, the second source region, and the sidewalls of the trench, where the N type dopant forms an N+ type region. The method further comprises implanting a P type dopant in the first source region, the second source region, and the sidewalls of the trench, where the P type dopant forms a P type region, and where the P type region is situated underneath the N+ type region.

Abstract: An integrated non-volatile memory circuit is formed by first growing a thin dielectric layer on a semiconductor substrate surface, followed by depositing a layer of conductive material such as doped polysilicon on this dielectric layer, the conductive material then being separated into rows and columns of individual floating gates. Cell source and drain diffusions in the substrate are continuously elongated across the rows. Field dielectric deposited between the rows of floating gates provides electrical isolation between the rows. Shallow trenches may be included between rows without interrupting the conductivity of the diffusions along their lengths. A deep dielectric filled trench is formed in the substrate between the array and peripheral circuits as electrical isolation. Various techniques are included that increase the field coupling area between the floating gates and a control gate.

Abstract: A memory device includes a coupling capacitor and a field-effect transistor. The coupling capacitor is formed from (1) a first dopant region in a second dopant region on a substrate, (2) a gate dielectric atop the first dopant region, and (3) a first gate conductor atop the gate dielectric. The coupling capacitor has the first gate conductor coupled to a second gate conductor of the field-effect transistor. A voltage can be applied to the second dopant region to isolate the coupling capacitor from the substrate by reverse biasing a PN junction formed between the first dopant region and the second dopant region.

Abstract: A nonvolatile semiconductor memory device having MONOS type memory cells of increased efficiency by hot electron injection and improved scaling characteristics includes a channel forming region in the vicinity of a surface of a substrate, first and second impurity regions, acting as a source and a drain in operation, formed in the vicinity of the surface of the substrate sandwiching the channel forming region between them, a gate insulating film stacked on the channel forming region and having a plurality of films, and a charge storing means that is formed in the gate insulating film dispersed in the plane facing the channel forming region. A bottom insulating film includes a dielectric film that exhibits a FN type electroconductivity and makes the energy barrier between the bottom insulating film and the substrate lower than that between silicon dioxide and silicon.

Abstract: A semiconductor device including an IGFET (insulated gate field effect transistor) (30) is disclosed. IGFET (30) may include a source/drain area (15) having an impurity concentration distribution that may be formed shallower at a higher concentration than the impurity concentration distribution in another source/drain area (7). A gate oxide film may include a first gate oxide film (5) adjacent to source/drain area (7) and a second gate oxide film (12) adjacent to source drain area (15). Second gate oxide film (12) may be thinner than first gate oxide film (5). An impurity concentration distribution of a second channel impurity area (11) under second gate oxide film (12) may be at a higher concentration than an impurity concentration distribution of a first channel impurity area (9) under first gate oxide film (5). In this way, an electric field at a PN junction of source/drain area (7) may be reduced.

Abstract: A semiconductor device includes a substrate and an insulating layer formed on the substrate. A first device may be formed on the insulating layer. The first device may include a first fin formed on the insulating layer, a first dielectric layer formed on the first fin, and a partially silicided gate formed over a portion of the first fin and the first dielectric layer. A second device also may be formed on the insulating layer. The second device may include a second fin formed on the insulating layer, a second dielectric layer formed on the second fin, and a fully silicided gate formed over a portion of the second fin and the second dielectric layer.

Abstract: NAND-type flash memory devices and methods of fabricating the same are provided. The NAND-type flash memory device includes a plurality of isolation layers running parallel with each other, which are formed at predetermined regions of a semiconductor substrate. This device also includes a string selection line pattern, a plurality of word line patterns and a ground selection line pattern which cross over the isolation layers and active regions between the isolation layers. Source regions are formed in the active regions adjacent to the ground selection line patterns and opposite the string selection line pattern. The source regions and the isolation layers between the source regions are covered with a common source line running parallel with the ground selection line pattern.

Abstract: A block alterable memory cell has a select control gate extending from a floating gate region to a drain region. The block alterable memory cell comprises a substrate layer that further includes a source implant region, an active region, a floating gate transistor region, and a drain implant region. A tunnel oxide layer overlies the substrate layer and is deposited to a thickness of approximately 70 angstroms. The select control gate comprises a first oxide layer overlying the tunnel oxide layer, an inter poly layer overlying over the first oxide layer, and a second layer extending over the floating gate transistor region and the active region to an edge of the drain implant region.

Abstract: The present invention provides a code implantation process for the mask read only memory (MROM). A gate oxide layer and a wordline are formed sequentially over a substrate having a buried bitline, with a cap layer formed on the top of the wordline. A dielectric layer is formed on the substrate that is not covered by the wordline and the cap layer. A resist layer with a line/space pattern is formed on the dielectric layer and the cap layer, while the line/space pattern has a first extending direction different to a second extending direction of the cap layer. After removing the cap layer not covered by the resist layer, a code mask layer is formed over the substrate. An ion implantation step is performed to implant dopants into a predetermined code channel region by using the code mask layer, the dielectric layer and the remained cap layer as a mask.

Abstract: An EEPROM memory cell and a method of forming the same are provided. A portion of a floating gate is formed on walls of a trench formed on the substrate. An inside of the trench is filled with a gate electrode layer constituting a sensing line. This leads to increases in opposite areas of a floating gate and a control gate of a sensing transistor, and a decrease in an area of the floating gate in the substrate.

Abstract: A memory transistor of an EEPROM has a floating gate electrode of a shape such that it covers the entirety of a tunnel film and a channel region and does not cover a region between the channel region and an embedded layer. And, a control gate electrode is formed on an interlayer insulating film on the floating gate electrode into a shape such that it is wider than the floating gate electrode above the tunnel film, and is narrower than the floating gate electrode above the channel region.

Abstract: An integrated circuit has a high voltage area, a logic area and a memory array for forming a system on a chip that includes linear, logic and memory devices. The memory array has floating gate transistors disposed in a triple well structure with a raised drain bit line 13 substantially vertically aligned with a buried source bit line 14. The memory array separates the columns with deep trenches 46 that may also be formed into charge pump capacitors.

Abstract: An array of floating gate memory cells, and a method of making same, where each pair of memory cells includes a pair of trenches formed into a surface of a semiconductor substrate, with a strip of the substrate disposed therebetween, a source region formed in the substrate strip, a pair of drain regions, a pair of channel regions each extending between the source region and one of the drain regions, a pair of floating gates each disposed in one of the trenches, and a pair of control gates. Each channel region has a first portion disposed in the substrate strip and extending along one of the trenches, a second portion extending underneath the one trench, a third portion extending along the one trench, and a fourth portion extending along the substrate surface and under one of the control gates.

Abstract: First of all, a semiconductor substrate is provided, and then a first/second wells with a first conductivity are formed therein so as to individually form a first part of the floating gate of single-level EEPROM and a low-voltage device thereon, wherein the first and the second wells are used to separate the high-voltage device, and the depth of the first well is the same as the second well. Furthermore, the high-voltage device and the second part of the floating gate of single-level EEPROM are individually formed on the semiconductor substrate between the first and the second wells, and the control gate of the floating gate of single-level EEPROM is formed in the third well located under the second part of the floating gate of single-level EEPROM, wherein the high-voltage device can be operated in the opposite electric field about 18V, such as ?6V˜12V, ?12V˜6V, ?9V˜9V etc.

Abstract: In this invention a process for a flash memory cell and an architecture for using the flash memory cell is disclosed to provide a nonvolatile memory having a high storage density. Adjacent columns of cells share the same source and the source line connecting these sources runs vertically in the memory layout, connecting to the sources of adjacent columns memory cells. Bit lines connect to drains of cells in adjacent columns and are laid out vertically, alternating with source lines in an every other column scheme. Wordlines made of a second layer of polysilicon form control gates of the flash memory cells and are continuous over the full width of a memory partition. Programming is done in a vertical page using hot electrons to inject charge onto the floating gates. the cells are erased using Fowler-Nordheim tunneling of electrons from the floating gate to the control gate by way of inter polysilicon oxide formed on the walls of the floating gates.

Abstract: A structure of a non-volatile flash memory, in which a punch-through current is suppressed and the area of a memory cell is reduced, is provided. The non-volatile flash memory being a NOR type non-volatile flash memory provides floating gates and a common source line, and drains. And at the structure of the non-volatile flash memory, a region overlapped one of the drains and one of the floating gates in a memory cell is larger than a region overlapped the common source and one of the floating gates in the memory cell.

Abstract: A method and system for improving short channel effect on a floating gate device is disclosed. In one embodiment, a p-type implant is applied to a source side of the floating gate device. In addition, the present embodiment applies a p-type implant to a drain side of the floating gate device. The p-type implant to the drain side is performed at a different angle than the p-type implant to the source side. The p-type implant to the drain side is implanted to a greater depth than that of the p-type implant to the source side.

Abstract: An electrically erasable and programmable memory cell is provided. The memory cell includes a floating gate MOS transistor and a bipolar transistor for injecting an electric charge into the floating gate. The floating gate transistor has a source region and a drain region formed in a first well with a channel defined between the drain and source regions, a control gate region, and a floating gate extending over the channel and the control gate region. The bipolar transistor has an emitter region formed in the first well, a base region consisting of the first well, and a collector region consisting of the channel. The memory cell includes a second well that is insulated from the first well, and the control gate region is formed in the second well. Further embodiments of the present invention provide a memory including at least one such memory cell, an electronic device including such a memory, and methods of integrating a memory cell and erasing a memory cell.

Abstract: A low-voltage nonvolatile memory array includes a cell well of a first conductivity type formed in a substrate; columns of buried bit lines of a second conductivity type formed within the cell well, wherein columns of the buried bit lines are isolated from each other and each is further divided into of sub-bit line segments with deeply doped source wells of the first conductivity type connected to the cell well; a plurality of memory cell blocks serially arranged over one of the columns of buried bit lines, wherein a memory cell block corresponds to a sub-bit line segment, and each memory cell block includes at least one memory transistor having a stacked gate, source, and drain; and a local bit line overlying the memory cell blocks and electrically connected to the drain of the memory transistor via a contact plug short-circuiting the drain and the subjacent buried bit line.

Abstract: Disclosed is a self-aligned non-volatile memory cell including a small sidewall spacer electrically coupled and being located next to a main floating gate region. Both the small sidewall spacer and the main floating gate region are formed on a substrate and both form the floating gate of the non-volatile memory cell. Both are isolated electrically from the substrate by an oxide layer which is thinner between the small sidewall spacer and the substrate; and is thicker between the main floating gate region and the substrate. The small sidewall spacer can be made small; therefore, the thin oxide layer area can also be made small to create a small pathway for electrons to tunnel into the floating gate.

Abstract: In a semiconductor integrated circuit device having a system-on-chip structure in which a DRAM and a logic integrated circuit are mixedly mounted on a chip, a silicide layer is formed on the surfaces of the source and the drain of a MISFET of a direct peripheral circuit of the DRAM, the surfaces of the source and the drain of a MISFET of an indirect peripheral circuit of the DRAM, and the surfaces of the source and the drain of a MISFET of the logic integrated circuit, and the silicide layer is not formed on the surfaces of the source and the drain of a memory cell selective MISFET of the memory cell of the DRAM.

Abstract: A split gate flash memory device and method of fabricating the same. A cell of the split gate flash memory device in accordance with the invention is disposed in a cell trench within a substrate to achieve higher integration of memory cells.

Abstract: A semiconductor device of this invention is a single-layer gate nonvolatile semiconductor memory in which a floating gate having a predetermined shape is formed on a semiconductor substrate. This floating gate opposes a diffusion layer serving as a control gate via a gate oxide film and is capacitively coupled with the diffusion layer by using the gate oxide film as a dielectric film. The diffusion layer immediately below the dielectric film is insulated from the semiconductor substrate by an insulating film such as a silicon oxide film. A pair of diffusion layers are formed in surface regions of the semiconductor substrate on the two sides of the floating gate extending on a tunnel oxide film.

Abstract: In the semiconductor integrated circuit device, an AND-type flash memory is formed on a substrate in which stripe-like element separation regions 5 are formed and active regions L sandwiched between the element separation regions 5 are formed like stripes. A silicon monocrystal substrate containing nitrogen or carbon is used as the semiconductor substrate, to reduce dislocation defects and junction leakages so that the reliability and yield are improved.

Abstract: A split gate structure is disclosed for improved programming and erasing efficiency. Source/drain regions are equally spaced along the active regions and are electrically connected by source/drain towers that run perpendicular to the active regions. Floating gate towers are situated between each pair of source/drain towers. A floating gate tower has insulating layers separating floating gates, which exist only over active regions crossed by the floating gate tower, from a semiconductor region. An insulating layer separates the floating gates from a top gate and an insulating layer is disposed over the top gate. Insulator spacers are disposed over the sidewalls. Programming injectors, in electrical contact with the semiconductor region, are disposed against the sidewalls of the floating gate towers except where there are source/drain towers and taper to a sharp edge at a height so that they face the floating gates. Selected gates are disposed over the active regions.

Abstract: Dopant of an n-type is deposited in the channel area of a p-type well of isolated gate floating gate NMOS transistors forming the memory cells of a memory device array connected in a NAND gate architecture. The dopant is provided by a tilt angle around the existing floating gate/control gate structure at the stage of the fabrication process where the floating gate/control structure is in existence, the field oxidation step may also have occurred, and implantation of the source and drain dopants may also have occurred. This forms a retrograde n-type distribution away from the direction of the surface of the substrate in the channel, which is also concentrated laterally toward the centerline axis of the gate structure and decreases towards the opposing source and drain regions. This deposition promotes buried-channel-like performance of the NMOS transistors connected in series in the NAND gate memory architecture.

Abstract: A 2-bit cell is made up by first and second diffusion regions provided in a substrate surface in separation from each other, first and second dielectric films provided on the substrate adjacent to the first and second diffusion region, first and second gate electrodes provided on first and second dielectric films, a third insulating film provided on the substrate and a third gate electrode provided on the third insulating film. The first and second gate electrodes are connected common to form word line electrodes. A control gate electrode extending in a direction at right angles to the word line electrodes and a third diffusion region in the substrate surface disposed at a longitudinal end of the control gate electrode are provided.

Abstract: A non-volatile memory (NVM) system includes a NVM cell having: a semiconductor region having a first conductivity type; a gate dielectric layer located over the semiconductor region; a gate electrode located over the gate dielectric layer; a source region and a drain region of a second conductivity type, opposite the first conductivity type, located in the semiconductor region and aligned with the gate electrode; a crown electrode having a base that contacts the gate electrode and walls that extend vertically from the base region, away from the gate electrode; a dielectric layer located over the crown electrode, wherein the dielectric layer extends over at least interior surfaces of the walls; and a plate electrode located over the dielectric layer, wherein the plate electrode extends over at least interior surfaces of the walls.

Abstract: A floating gate (110) of a nonvolatile memory cell is formed in a trench (114) in a semiconductor substrate (220). A dielectric (128) covers the surface of the trench. The wordline (140) has a portion overlying the trench. The cell's floating gate transistor has a first source/drain region (226), a channel region (224), and a second source/drain region (130). The dielectric (128) is stronger against leakage near at least a portion of the first source/drain region (122) than near at least a portion of the channel region. The stronger portion (128.1) of the additional dielectric improves data retention without increasing the programming and erase times if the programming and erase operations do not rely on a current through the stronger portion. Additional dielectric (210) has a portion located below the top surface of the substrate between the trench and a top part of the second source/drain region (130). The second source/drain region has a part located below the additional dielectric and meeting the trench.

Abstract: Non-volatile memory devices according to embodiments of the invention can include, for example, a semiconductor substrate, a source region, a drain region, an impurity region, a vertical structure, a control gate insulating layer, a control gate electrode, a gate insulating layer, and a gate electrode. The impurity region is in a floating state between the source region and the drain region. The vertical structure is formed of a tunneling layer, a charge trapping layer, and a blocking layer sequentially stacked between the source region and the impurity region. The control gate insulating layer is between the source region and the impurity region and adjacent to the vertical structure. The control gate electrode is formed on the vertical structure and the control gate insulating layer. The gate insulating layer is between the impurity region and the drain region. The gate electrode is formed on the gate insulating layer.

Abstract: Systems and methods are provided for nonvolatile memory devices that incorporate a band-gap engineered gate stack with asymmetric tunnel barriers. One embodiment of a memory device includes first and second source/drain regions separated by a channel region in a substrate, a control gate, and a gate stack between the control gate and the channel region. The gate stack includes a first insulator region in contact with the channel region, a floating charge-storage region in contact with the first insulator region, and a second insulator region in contact with the floating charge-storage region and the control gate. The gate stack includes selected material, in conjunction with control gate metallurgy, for providing desired asymmetric energy barriers that are adapted to primarily restrict carrier flow during programming to a selected carrier between the control gate and the floating charge-storage region, and to retain a programmed charge in the floating charge-storage region. Other aspects are provided herein.

Abstract: A method for forming an integrated circuit on an insulating substrate is described comprising the steps of forming a semiconductor layer on a seed wafer substrate containing an at least partially crystalline porous release layer, processing the semiconductor layer to form a “transferable” device layer containing at least one semiconductor device, and bonding said transferable device layer to a final, insulating substrate before or after separating said device layer from the seed wafer substrate. A second method, for separating a semiconductor layer from a seed wafer substrate, is described wherein an at least partially crystalline porous layer initially connecting the semiconductor layer and seed wafer substrate is split or broken apart by the steps of (i) introducing a fluid including water into the pores of said porous layer, and (ii) expanding said fluid by solidifying or freezing to break apart the porous layer.

Abstract: In FLASH EPROM cells, source diffusion continuity between horizontal and vertical source lines is provided by an arsenic implant under the stack in vertical source lines.

Abstract: A programmable memory transistor (PMT) comprising an IGFET and a coupling capacitor in a semiconductor substrate. The IGFET comprises source and drain regions, a channel therebetween, a gate insulator overlying the channel, and a first floating gate over the gate insulator. The capacitor comprises a lightly-doped well of a first conductivity type, heavily-doped contact and injecting diffusions of opposite conductivity types in the lightly-doped well, a control gate insulator overlying a surface region of the lightly-doped well between the contact and injecting diffusions, a second floating gate on the control gate insulator, and a conductor contacting the lightly-doped well through the contact and injecting diffusions. The first and second floating gates are preferably patterned from a single polysilicon layer, such that the second floating gate is capacitively coupled to the lightly-doped well, and the latter defines a control gate for the first floating gate.

Abstract: A nonvolatile semiconductor memory includes rewritable nonvolatile memory cell transistors connected in series. The nonvolatile memory cell transistors includes at least two charge storage layers formed on a first insulating film, a control gate shared by two adjacent transistors which are two of the nonvolatile memory cell transistors and which are adjacent to each other, and a second insulating film formed between the at least two charge storage layers and the control gate. A top of the control gate has a flat surface that covers the at least two charge storage layers that correspond to the two adjacent transistors, and the flat surface extends from one of the at least two charge storage layers to the other of the at least two charge storage layers.

Abstract: A nonvolatile reprogrammable switch for use in a PLD or FPGA has a nonvolatile memory cell connected to the gate of an MOS transistor with the terminals of the MOS transistor connected to the source of the signal and to the circuit. The nonvolatile memory cell is of a split gate type having a floating gate positioned over a first portion of the channel and a control gate positioned over a second portion of the channel with electrons being injected onto the floating gate by hot electron injection mechanism. The nonvolatile memory cell is erased by the action of the electrons from the floating gate being tunneled through Fowler-Nordheim tunneling onto the control gate, which is adjacent to the second region. As a result, no high voltage is ever applied to the second region during program or erase. Thus, the nonvolatile memory cell with the second region can be connected directly to the gate of the MOS transistor, which together therewith forms a nonvolatile reprogrammable switch.

Abstract: A double-gate field effect transistor (DGFET) structure and method of forming such a structure in which the parasitic capacitance under the source/drain regions is substantially reduced are provided. Two new means to reduce the parasitic capacitance under the source/drain regions are provided. Firstly, the silicon area outside the gate is converted to oxide while protecting a silicon ledge adjacent to the gate with a first spacer. The oxidation can be facilitated using a self-aligned oxygen implant, or implant of some other species. Secondly, the first spacer is removed, replaced with a second spacer, and a new silicon source/drain area is grown by employing lateral selective epi overgrowth and using the now exposed silicon ledge as a seed, over the self-aligned oxide isolation region. This achieves a low-capacitance to the back-plane, while retaining control of the threshold voltages.

Abstract: A programmable memory transistor (PMT) comprising an IGFET and a coupling capacitor in a semiconductor substrate. The IGFET comprises source and drain regions, a channel therebetween, a gate insulator overlying the channel, and a first floating gate over the gate insulator. The capacitor comprises a lightly-doped well of a first conductivity type, heavily-doped contact and injecting diffusions of opposite conductivity types in the lightly-doped well, a control gate insulator overlying a surface region of the lightly-doped well between the contact and injecting diffusions, a second floating gate on the control gate insulator, and a conductor contacting the lightly-doped well through the contact and injecting diffusions. The first and second floating gates are preferably patterned from a single polysilicon layer, such that the second floating gate is capacitively coupled to the lightly-doped well, and the latter defines a control gate for the first floating gate.

Abstract: The present invention improves a productivity in growing an a-Si film in a thin film transistor and to obtain an excellent thin film transistor characteristic. More specifically, disclosed is a thin film transistor in which an amorphous silicon film 2, a gate insulating film 3 and a gate electrode are sequentially stacked on an insulating substrate 1. The amorphous silicon film 2 includes a low defect-density amorphous silicon layer 5 formed at a low deposition rate and a high deposition rate amorphous silicon layer 6 formed at a deposition rate higher than that of the low defect-density amorphous silicon layer 5. The low defect-density amorphous silicon layer 5 in the amorphous silicon film 2 is grown closer to the insulating substrate 1, and the high deposition rate amorphous silicon layer 6 is grown closer to the gate insulating film 3.

Abstract: A memory device includes a memory node (1) to which charge is written through a tunnel barrier configuration (2) from a control electrode (9). The stored charge effects the conductivity of a source/drain path (4) and data is read by monitoring the conductivity of the path. The charge barrier configuration comprises a multiple tunnel barrier configuration, which may comprise alternating layers (16) of polysilicon of 3 nm thickness and layers (15) of Si3N4 of 1 nm thickness, overlying polycrystalline layer of silicon (1) which forms the memory node. Alternative barrier configurations (2) are described, including a Schottky barrier configuration, and conductive nanometer scale conductive islands (30, 36, 44), which act as the memory node, distributed in an electrically insulating matrix.

Abstract: A low voltage single-poly flash memory cell includes a first ion well of a first conductivity type, a second ion well of a second conductivity type formed on the first ion well, a charge storage layer comprising a first insulating layer, a trapping layer, and a second insulating layer, located on the second ion well, a gate located on the charge storage layer, a sourceand a drain of the second conductivity type located in two sides of the charge storage layer, and an ion doped region of the first conductivity type formed in the second ion well and under and surrounding the source and at least a portion of a bottom of the first insulating layer.

Abstract: A semiconductor device has a gate-insulating film formed on a semiconductor substrate. Gate electrodes comprised of P- and N-type polysilicon thin films and thin conductive films are formed over the gate-insulating film. The P- and N-type polysilicon thin films are doped with impurities at an impurity concentration sufficient to prevent depletion layers from being formed in the P- and N-type polysilicon thin films when a voltage is applied between each of the conductive thin films and the semiconductor substrate. Source and drain regions are formed over the semiconductor substrate in spaced-apart relation to one another and on opposite sides of the gate electrodes.

Abstract: A non-volatile memory compatible with logic devices and processes is described. The non-volatile memory has a substrate, a first dielectric layer, a first gate, a second gate, a second dielectric layer, a plurality of spacers and a source/drain. A first active region and a second active region are formed on the substrate. When hot carrier effect occurs near the drain, the second dielectric layer located under the spacers is able to retain electrons so that the non-volatile memory is programmed.

Abstract: A process for producing a semiconductor memory device comprises the steps of: (a) forming a floating gate on a semiconductor substrate having a dielectric film; (b) forming a side wall spacer comprising an insulating film on a side wall of the floating gate; (c) forming a groove by etching the semiconductor substrate using the side wall spacer as a mask; and (d) forming a low concentration impurity layer from one side wall to a bottom surface of the groove by an oblique ion implantation to the semiconductor substrate thus resulting, and forming a high concentration impurity layer from the other side wall to the bottom surface of the groove by in inverse oblique ion implantation.

Abstract: A nonvolatile semiconductor memory device having MONOS type memory cells of increased efficiency by hot electron injection and improved scaling characteristics includes a channel forming region in the vicinity of a surface of a substrate, first and second impurity regions, acting as a source and a drain in operation, formed in the vicinity of the surface of the substrate sandwiching the channel forming region between them, a gate insulating film stacked on the channel forming region and having a plurality of films, and a charge storing means that is formed in the gate insulating film dispersed in the plane facing the channel forming region. A bottom insulating film includes a dielectric film that exhibits a FN type electroconductivity and makes the energy barrier between the bottom insulating film and the substrate lower than that between silicon dioxide and silicon.

Abstract: A NAND type semiconductor device is disclosed, in which a first insulating film embedded between the memory cell gates and between the memory cell gates and the selecting gate does not contain nitrogen as a major component, a second insulating film is formed on the first insulating film, and an interlayer insulating film is formed on the second insulating film whose major component is different from a major component of the second insulating film.

Abstract: An electrically erasable and programmable memory cell is provided. The memory cell includes a floating gate MOS transistor and a bipolar transistor for injecting an electric charge into the floating gate. The floating gate transistor has a source region and a drain region formed in a first well with a channel defined between the drain and source regions, a control gate region, and a floating gate extending over the channel and the control gate region. The bipolar transistor has an emitter region formed in the first well, a base region consisting of the first well, and a collector region consisting of the channel. The memory cell includes a second well that is insulated from the first well, and the control gate region is formed in the second well. Further embodiments of the present invention provide a memory including at least one such memory cell, an electronic device including such a memory, and methods of integrating a memory cell and erasing a memory cell.

Abstract: An embodiment of the memory cell for an EEPROM device may comprise a trench coupling capacitor wherein the coupling oxide of the coupling capacitor is formed only in the trench (i.e., such that coupling occurs only in the trench). In addition, a first portion of a floating gate of the memory cell is formed in the trench to function as a part of the coupling capacitor as well as a floating gate. A floating gate second portion is electrically connected to the first portion. A control gate is connected to a doped region of the substrate and a thin tunnel dielectric physically separates the floating gate second portion from the coupling oxide layer and from the doped region of the substrate.