Abstract: An embodiment of the memory cell for an EEPROM device may comprise a trench coupling capacitor wherein the coupling oxide of the coupling capacitor is formed only in the trench (i.e., such that coupling occurs only in the trench). In addition, a first portion of a floating gate of the memory cell is formed in the trench to function as a part of the coupling capacitor as well as a floating gate. A floating gate second portion is electrically connected to the first portion. A control gate is connected to a doped region of the substrate and a thin tunnel dielectric physically separates the floating gate second portion from the coupling oxide layer and from the doped region of the substrate.

Abstract: The invention relates to an electrically erasable, non-volatile memory device, having a memory cell of the floating gate type (16), defined by a source zone, a drain zone, a channel zone (8) and a control gate zone (6), the latter being separated from the channel zone by an insulation zone (14), said five zones being implemented in a semiconductor film formed on an insulating layer (4), said memory cell being laterally insulated by one or more insulation zones (10, 12) in contact with the insulating layer.

Abstract: A semiconductor structure (and method for forming) having transistors having both metal gates and polysilicon gates on a single substrate in a single process is disclosed. The method forms a gate dielectric layer on the substrate and forms the metal seed layer on the gate oxide layer. The method patterns the metal seed layer to leave metal seed material in metal gate seed areas above the substrate. Next, the method patterns a polysilicon layer into polysilicon structures above the substrate. Some of the polysilicon structures comprise sacrificial polysilicon structures on the metal gate seed areas and the remaining ones of the polysilicon structures comprise the polysilicon gates. The patterning of the polysilicon gates forms the sacrificial gates above all the metal gate seed areas. Following that, the invention forms sidewall spacers, and source and drain regions adjacent the polysilicon structures.

Abstract: A non-volatile storage cell manufactured in a standard CMOS process in silicon on insulator is described. The cell is manufactured in a standard single polysilicon layer CMOS process applied to silicon on insulator starting substrates. Two versions of the cell are described with distinct mechanisms for writing onto a floating polysilicon layer storage node. The basic cell comprises crossed N- and P- transistors which share a common channel region and a common floating gate over the channel. Current in the channel results in charge injection through the gate oxide and onto the polysilicon gate conductor where it is permanently stored. Since both N and P type transistors are available, charge of both polarities can be injected. Application of a voltage to either of the transistors results in a current or voltage which is used to perform the reading function. Multiple variations of the cell and its operation are also described along with unique applications of the cell.

Abstract: A non-volatile semiconductor memory device includes a p-type Si substrate, an n-type well formed in the Si substrate, a control gate of a p-type buried diffusion region formed in the n-type well, an active region formed in the Si substrate in the vicinity of the n-type well and covered by a tunneling insulation film, and a floating gate electrode formed on the Si substrate so as to achieve a capacitance coupling with the p-type buried diffusion region, wherein the floating gate electrode extends on the active region over the tunneling insulation film, and the active region including a pair of n-type diffusion regions are formed at both sides of the floating gate electrode as source and drain regions, the n-type diffusion region forming the source region having an n−-type diffusion region at the side facing the n-type diffusion region forming said drain region.

Abstract: A nonvolatile semiconductor memory device capable of readily distinctively forming transistors in a peripheral circuit part and a transistor in a memory cell part while minimizing the number of times of high-temperature heat treatment are obtained. In the peripheral circuit part, at least one of a first transistor and a second transistor has a lower conductive layer having the same perpendicular structure as a floating gate, an intermediate insulator film including an insulator film of the same perpendicular structure as an inter-gate isolation film and an upper conductive layer of the same perpendicular structure as a conductive layer of a control gate in ascending order on a gate insulator film thereof, and the intermediate insulator film includes a conduction part electrically connecting the upper conductive layer and the lower conductive layer with each other.

Abstract: A split gate flash memory cell. The memory cell includes a substrate, a conductive stud, source/drain regions, an insulating layer, a conductive spacer, an insulating stud, a first conductive layer, and a first insulating spacer. The conductive stud is disposed in the lower trench of the substrate. The source region is formed in the substrate adjacent to the upper conductive stud having the insulating layer thereon. The conductive spacer is disposed on the upper sidewall of the trench serving as a floating gate. The insulating stud is disposed on the insulating layer. The first conductive layer is disposed over the substrate of the outside conductive spacer serving as a control gate. The first insulating spacer is disposed on the sidewall of the insulating stud to cover the first conductive layer. The drain region is formed in the substrate of the outside first conductive layer.

Abstract: This invention provides a semiconductor device including a semiconductor substrate, a transistor having a gate insulation film on the semiconductor substrate and a gate electrode on the gate insulation film, and a device isolating insulation film having a first portion which extends from a surface of the semiconductor substrate to an inner part of the semiconductor substrate and a second portion which protrudes from the semiconductor substrate, wherein a side surface of the second portion is in direct contact with a side surface of the gate electrode at least partially and a cross section of the gate electrode is reverse tapered. This invention also provides a manufacturing method thereof.

Abstract: A method and system for insulating a lower layer of a semiconductor device from an upper layer of the semiconductor device is disclosed. The method and system include providing an interlayer dielectric on the lower layer. The interlayer dielectric is capable of gap filling while using only species of relatively low mobility. The method and system also include planarizing a surface of the interlayer dielectric.

Abstract: A method of forming a local interconnect for a semiconductor integrated circuit, the local interconnect comprising a refractory silicide contact having a substantially small sheet resistance formed at an exhumed surface of a gate stack, wherein the local interconnect electrically couples a gate electrode of the gate stack with an active region of the semiconductor substrate. The method of forming the local interconnect comprises depositing a gate oxide layer over the substrate, a first polysilicon layer over the gate oxide layer, a laterally conducting layer over the polysilicon layer, a second polysilicon layer over the laterally conducting layer, and an insulating layer over the second polysilicon layer. The intermediate structure is then etched so as to form a plurality of gate stacks. A surface of the second polysilicon layer of a gate stack is exhumed so as to allow subsequent formation of the refractory silicide contact at the exhumed surface.

Abstract: Various emdodiments include a transistor device that is controlled by a gate current and that exhibits low power consumption as well as high speed characteristics. In various embodiments, an enhancement mode MESFET device exhibits channel drain current that is controlled by the application of bias current into the gate. Complementary n- and p-channel devices can be realized for, for example, micropower analog and digital circuit applications.

Abstract: A flash memory device having improved gate capacitive coupling ratio between a floating gate and a control gate and a fabrication method therefor. The disclosed flash memory device comprises a semiconductor substrate having a first trench with a width including an active region and an isolation region at either side thereof; an isolation layer formed on the isolation regions of the first trench; a second trench in the first trench defined by the isolation layer and exposing only the active region; a groove-shaped floating gate formed on the surface of the second trench and having a tunnel oxide layer on the lower part thereof; a control gate formed on the floating gate and having a gate insulating layer on the lower part thereof; a source region and a drain region formed in the substrate at both sides of the floating gate; and metal wirings formed to be in contact with the source and drain regions, respectively, through the isolation layer on the substrate.

Abstract: A non-volatile memory cell at least partially formed in a semiconductor substrate. The cell comprises a first transistor comprising a high voltage NMOS transistor having a first active region and a second active region; a second transistor sharing said second active region and having a third active region in said substrate; an active control gate region formed in said substrate; a polysilicon layer having a first portion forming a gate for said first transistor, and a second portion forming gate for said second transistor and a floating gate overlying said active control gate region. In one embodiment, an oxynitride separates said second portion and said active control gate region.

Abstract: A method is disclosed to form a reliable silicon nitride spacer between the lower edges of the floating gate and the control gate of a split-gate flash memory cell. This is accomplished by forming a floating gate with vertical sidewalls, forming a high temperature oxide layer followed by silicon nitride layer over the floating gate including the vertical sidewalls, ion implanting the nitride layer and then selectively etching it to form a robust silicon nitride spacer of well defined rectangular shape.

Abstract: Provided is a “castled” active area mask. A castled active area mask is one which has been lengthened to extend beyond its intended intersection with a tunnel dielectric to form the tunnel window of an EEPROM cell, and has also been widened in at least a portion of the extension. For example, in one preferred embodiment, a castled extension may have a “T” shape. The castled active area generated by such a mask provides a buffer to absorb field oxide encroachment before it reaches the EEPROM cell's TD window. A mask in accordance with the present invention may be used to fabricate EEPROM cells which are not subject to TD window size variations due to field oxide encroachment, and EEPROM cell arrays of increased density.

Abstract: An electrically erasable programmable logic device (EEPLD) includes a P type semiconductor substrate. An N type well is formed on the P type semiconductor substrate. A first PMOS transistor is formed on the N well. The first PMOS transistor comprises a floating gate, a first P+ doped region serving as a drain of the first PMOS transistor, and a P− doped region encompassing an N+ doped region for erasing the first PMOS transistor. A second PMOS transistor is also formed on the N well and serially connected to the first PMOS transistor. The first P+ doped region functions as a source of the second PMOS transistor, and the second PMOS transistor further comprises a select gate and a second P+ doped region serving as a drain of the second PMOS transistor.

Abstract: An information retention capability based on a memory cell which includes pair of nonvolatile memory elements in a differential form is improved. A nonvolatile memory element (130) constituting a flash memory is so constructed that its tunnel oxide film (GO3) and floating gate electrode (FGT) are respectively formed by utilizing the gate oxide film (GT2) and gate electrode (GT2) of a transistor for a circuit which is formed on the same semiconductor substrate as that of the element (130). A memory cell is constructed in a 2-cells/1-bit scheme in which a pair of nonvolatile memory elements can be respectively connected to a pair of complementary data lines, and threshold voltage states different from each other are set for the nonvolatile memory elements so as to differentially read out data.

Abstract: A new capacitor structure of a Flash memory (Flash) cells on a supporting substrate's existing topography, including existing topography provided by adjacent word lines is provided. The gate of the Flash memory cell is constructed as an integral part of the new capacitor cell structure. An increased capacitive coupling ratio is achieved whereby reduced programming voltage is required while yielding more a more compact memory cell structure. Hence, the requirements of low power densely packed integrated circuits is realized for smaller, portable microprocessor devices.

Abstract: A non-volatile memory comprising a semiconductor active layer provided on an insulating substrate, an insulating film provided on the semiconductor active layer, a floating gate electrode provided on the insulating film, an anodic oxidized film obtained by anodic oxidation of the floating gate electrode, and a control gate electrode provided in contact with the anodic oxidized film, and a semiconductor device, particularly a liquid crystal display device comprising the non-volatile memory.

Abstract: A shallow junction EEPROM device and process for fabricating the device includes the formation of a control-gate region and a tunnel region in a semiconductor substrate in which the control-gate region has a substantially higher total doping concentration than the tunnel region. To compensate for rate enhanced oxidation of the silicon surface overlying the control-gate region, nitrogen is selectively introduced into the control-gate region, such that the resulting dielectric layer thickness overlying the control-gate region is substantially the same as that overlying the tunnel region. The relatively high doping concentration of the control-gate region enables fabrication of an EEPROM device having high capacitance coupling, shallow junctions, and a relatively small capacitor area.

Abstract: Memory cell having a floating gate with lateral edges which are aligned directly above edges of the active area in the substrate, a control gate positioned directly above the floating gate, and a select gate spaced laterally from the control gate. The floating gate has a bottom wall and side walls which face corresponding walls of the control gate in capacitive coupling relationship, with the height of the side walls being on the order of 80 to 160 percent of the width of the bottom wall. In some embodiments, the floating gate is wider than the overlying control gate and has projecting portions which overlie the shallow and deep diffusion regions of the stack transistor.

Abstract: A testing circuit made on a silicon wafer including a plurality of identical cells, each of which includes a primary capacitor of given characteristics, which includes a test capacitor of same characteristics as each primary capacitor and of surface at least equal to the sum of the surfaces of the primary capacitors.

Abstract: The memory cell is of the type with a single level of polysilicon, and comprises a sensing transistor and a select transistor. The sensing transistor comprises a control gate region with a second type of conductivity, formed in a first active region of a substrate of semiconductor material, and a floating gate region which extends transversely relative to the first active region. The control gate region of the sensing transistor is surrounded by a first well with the first type of conductivity, and in turn is surrounded, below and laterally, by a second well with the second type of conductivity, thus forming a triple-well structure. A second triple-well structure can be formed in a second active region adjacent to the first active region, and can accommodate conduction regions of the sensing transistor and of the select transistor.

Abstract: A trench region is formed in a memory cell P-type well. Two NAND-type memory cell units are respectively formed along both side wall portions of this trench region. A floating gate and a control gate in these NAND-type memory cell units are formed self-aligningly without using a photoresist. One bit line connected to the two NAND-type memory cell units is formed via an interlayer dielectric. The bit line pitch of this bit line is set at 2 F. Hence, the size of a nonvolatile semiconductor memory can be reduced.

Abstract: An EEPROM cell having one layer of polycrystalline silicon in which a memory cell area is reduced without damaging cell characteristics by providing a channel length of a select gate transistor and a channel length of a cell transistor to extend perpendicularly to each other, and that a select gate electrode and a control gate electrode of an impurity diffusion layer are arranged in parallel with each other, and a cell source wiring is made of a metal wiring through a contact, so that a parasitic transistor on the control gate wiring is eliminated and it becomes possible to effectively reduce the cell area.

Abstract: An EPROM structure includes a NMOS transistor integrated with a capacitor. The terminal names of the NMOS transistor follow the conventional nomenclature: drain, source, body and gate. The gate of the NMOS transistor is connected directly and exclusively to one of the capacitor plates. In this configuration, the gate is now referred to as the “floating gate”. The remaining side of the capacitor is referred to as the “control gate”.

Abstract: A self aligned method of forming a semiconductor memory array of floating gate memory cells in a semiconductor substrate, along with strap regions interlaced within the array. The array includes word lines and source lines that connect together control gates and source regions from memory cells contained in row within the array. The strap regions include word line strap cells through which the word lines traverse, wherein the word lines completely traverse across the strap regions, and source line strap cells in which the source lines terminate without completely traversing across the strap region. A first plurality of conductive metal contacts are each connected to one of the word lines in one of the word line strap cells. A second plurality of conductive metal contacts are each connected to one of the source lines in one of the source line strap cells.

Abstract: Non-volatile memory cells store a level of charge corresponding to the data being stored in a dielectric material storage element that is sandwiched between a control gate and the semiconductor substrate surface over channel regions of the memory cells. More than two memory states are provided by one of more than two levels of charge being stored in a common region of the dielectric material. More than one such common region may be included in each cell. In one form, two such regions are provided adjacent source and drain diffusions in a cell that also includes a select transistor positioned between them.

Abstract: A non-volatile memory device includes gate insulating films formed on a semiconductor substrate and spaced apart from each other. A tunnel insulating film is formed on the semiconductor substrate and interposed between the adjacent gate insulating films. A memory transistor gate is formed on the tunnel insulating film and the gate insulating film interposing the tunnel insulating film therebetween. A select transistor gate is formed on the gate insulating film spaced apart from the memory transistor gate. A first doped region is formed in a portion of the semiconductor substrate under the memory transistor gate and extending to overlap one end of the select transistor gate. A second doped region is formed in a portion of the semiconductor substrate spaced apart from the first doped region and overlapping one end of the memory transistor opposite to the select transistor gate.

Abstract: The present invention provides a bipolar transistor for use in increasing a speed of a flash memory cell having a source region and a drain region and first and second complementary tubs. In one embodiment, a base for the bipolar transistor is located in the first complementary tub. The first complementary tub functions as a collector for the bipolar transistor. The bipolar transistor base also uniquely functions as the source region. The bipolar transistor's emitter is also located in the first complementary tub and proximate the base. For example, the emitter may be located adjacent the base or actually located in the base. In an additional embodiment, the opposing bases and emitters are located on opposing sides of and proximate to the flash memory cell.

Abstract: In the semiconductor device, a first impurity region and a second impurity region are formed in a surface of a semiconductor substrate at a regular interval, and a gate insulating layer is formed on the semiconductor substrate between the first impurity region and the second impurity region. At least two gate electrodes are formed on the gate insulating layer, and are insulated from one another by an intergate insulation layer.

Abstract: An information retention capability based on a memory cell which includes a pair of nonvolatile memory elements in a differential form is improved. A nonvolatile memory element (130) constituting a flash memory is so constructed that its tunnel oxide film (G03) and floating gate electrode (FGT) are respectively formed by utilizing the gate oxide film (GT2) and gate electrode (GT2) of a transistor for a circuit which is formed on the same semiconductor substrate as that of the element (130). A memory cell is constructed in a 2-cells/1-bit scheme in which a pair of nonvolatile memory elements can be respectively connected to a pair of complementary data lines, and threshold voltage states different from each other are set for the nonvolatile memory elements so as to differentially read out data.

Abstract: A semiconductor device of this invention is a single-layer gate nonvolatile semiconductor memory in which a floating gate having a predetermined shape is formed on a semiconductor substrate. This floating gate opposes a diffusion layer serving as a control gate via a gate oxide film and is capacitively coupled with the diffusion layer by using the gate oxide film as a dielectric film. The diffusion layer immediately below the dielectric film is insulated from the semiconductor substrate by an insulating film such as a silicon oxide film. A pair of diffusion layers are formed in surface regions of the semiconductor substrate on the two sides of the floating gate extending on a tunnel oxide film.

Abstract: A novel flash memory structure is disclosed, which includes a tunnel oxide layer on a semiconductor substrate, an array of gate electrode stacks formed on the tunnel oxide layer, and alternating source/drain regions formed between the stacks. A first dielectric layer is formed over the stacks and the substrate with a source line opening down to the source regions. A source line is formed above the source regions, partially filling the source line opening. The source line is located between the gate electrode stacks and has a surface level below a top surface of the stacks. A second dielectric layer is formed over the source line and the first dielectric layer with a plug opening down to the drain regions. A drain metal plug is formed over the drain regions, filling the plug opening. A metal bit line is formed over the second dielectric layer contacting the drain metal plug.

Abstract: A contactless channel write/erase flash memory cell structure and its fabricating method for increasing the level of integration is disclosed. The present invention utilizes a buried diffusion method to form an N+-doped region that acts as a drain of the flash memory cell and a P-doped region underneath an oxide layer. The N+-doped region and the P-doped region extend to in a bit line direction and a metal contact is used to connect the two away from any of the N+-doped region and the P-doped region of the flash memory cell for decreasing the numbers of the metal contacts in the flash memory cell and reducing dimensions of the device.

Abstract: Semiconductor devices are disclosed utilizing at least one polysilicon structure in a stacked gate region according to the present invention. The stacked gate region includes a substrate, at least one trench, an oxide layer, at least one floating gate layer and the at least one polysilicon structure. The at least one polysilicon structure is formed adjacent to vertical edges of the at least one floating gate layer and above the oxide layer. The polysilicon structure, which includes polysilicon wings and ears, is used to increase the capacitive coupling of memory cells in memory devices, thereby allowing for further reduction or scaling in the size of memory cells and devices.

Abstract: The generation of leakage currents between gate electrodes can be minimized while maintaining the dimensional accuracy and height of the gate electrodes. For example by lamp heating, an oxide film (7) is formed on gate electrodes (4) having a nitride film (8) on their upper surfaces. Thus, even if silicon dust particles are redeposited in between the gate electrodes 4 in a subsequent cleaning process, the generation of leakage currents between the electrodes can be minimized in semiconductor devices. The oxide film (7) is formed only on the side surfaces of the gate electrodes (4), which prevents a decrease in the film thickness in the upper surfaces of the gate electrodes (4) during the process of forming the oxide film (7). Further, there is no need to thicken a gate electrode material film (3) beforehand in order to maintain the height of the gate electrodes (4), which minimizes degradation in dimensional accuracy of the gate electrodes (4).

Abstract: Various semiconductor device structures that include one or more capacitors can be formed using a semiconductor structure having a monocrystalline silicon substrate, an amorphous oxide material overlying the monocrystalline silicon substrate, a monocrystalline perovskite oxide material overlying the amorphous oxide material; and a monocrystalline compound semiconductor material overlying the monocrystalline perovskite oxide material, and/or other types of material such as metals and non-metals.

Abstract: The present invention relates to a non-volatile semiconductor memory device and a fabricating method thereof, which prevents a programming disturbance and enables to have a programming operated by a byte unit by achieving a programming and an erasing of a memory device through a F-N tunneling.

Abstract: A process for manufacturing an electronic device having an HV MOS transistor with a low multiplication coefficient and a high threshold in a non-implanted area of the substrate, this area having the same conductivity type and the same doping level as the substrate. The transistor is obtained by forming, over the non-implanted substrate area, a first gate region of semiconductor material having the same doping type as the non-implanted substrate area; and forming, inside the non-implanted substrate area, first source and drain regions of a second conductivity type, arranged at the sides of the first gate region. At the same time, a dual-gate HV MOS transistor is formed, the source and drain regions of which are housed in a tub formed in the substrate and having the first conductivity type, but at a higher concentration than the non-implanted substrate area. It is moreover possible to form a nonvolatile memory cell simultaneously in a second tub of the substrate of semiconductor material.

Abstract: A testing circuit made on a silicon wafer including a plurality of identical cells, each of which includes a primary capacitor of given characteristics, which includes a test capacitor of same characteristics as each primary capacitor and of surface at least equal to the sum of the surfaces of the primary capacitors.

Abstract: A method of manufacturing a semiconductor device is provided in which a tunnel dielectric layer and a gate layer are formed on a semiconductor wafer and a trench forming technique is used to define a floating gate structure. An insulator is deposited in the trench whereby the gate layer and the tunnel dielectric layer form a gate which is self-aligned to a tunnel dielectric.

Abstract: A flash memory formed by a process wherein at least two parallel stacked gate strips are formed on a silicon substrate such that the stacked gate strips are separated by field oxide islands. Asymmetrical first and second junctions are formed in each of a set of source/drain regions and a chemical etch is applied to form the field oxide islands into oxide spacers that align a dual-function control line to the first and second junctions. The resulting flash memory includes a plurality of stacked gate islands, one or more source/drain regions between at least a subset of the plurality of stacked gate islands, first junctions in each of the source/drain regions, second junctions in each of the source/drain regions and dual function control lines in the source/drain regions.

Abstract: A semiconductor device of this invention is a single-layer gate nonvolatile semiconductor memory in which a floating gate having a predetermined shape is formed on a semiconductor substrate. This floating gate opposes a diffusion layer serving as a control gate via a gate oxide film and is capacitively coupled with the diffusion layer by using the gate oxide film as a dielectric film. The diffusion layer immediately below the dielectric film is insulated from the semiconductor substrate by an insulating film such as a silicon oxide film. A pair of diffusion layers are formed in surface regions of the semiconductor substrate on the two sides of the floating gate extending on a tunnel oxide film.

Abstract: A split gate type memory cell is a series combination of a stacked gate type memory transistor and a selecting field effect transistor, and the control gate insulating layer and the selecting gate oxide layer are to be thick and thin, respectively; an upper silicon oxide layer and the selecting gate oxide layer are thermally grown after deposition of a lower silicon oxide layer and a silicon nitride layer on the floating gate electrode, and the previous deposition of the lower silicon oxide layer/the silicon nitride layer and the thermal oxidation independently regulate the control gate insulating layer and the selecting gate oxide layer to appropriate thicknesses.

Abstract: A semiconductor memory cell has a deep trench capacitor and a vertical transistor formed over the deep trench capacitor. The vertical transistor has a control gate electrode, a source/drain region at opposite sides of the control gate electrode, and a channel region surrounding the sidewall and top of the control gate electrode. This can increase the length of the channel region to reduce leakage current.

Abstract: When a control gate electrode is processed using a control gate electrode processing mask, the control gate electrode in a region where the floating gate electrode has been removed is partially left. Because of the presence of the left control gate electrode, the gate electrode interlayer insulating film and gate insulating film below the control gate electrode are not dug in the region where the floating gate electrode has been removed. Therefore, when the floating gate electrode is removed, the semiconductor substrate is not dug. In this way, since the semiconductor substrate is not dug, the semiconductor memory device can be manufactured stably and precisely.

Abstract: A read-only memory includes a semiconductor substrate; a memory cell matrix which is formed on the semiconductor substrate; and word and bit lines which define the locations of the memory cell matrix. The memory cell matrix includes field effect transistors, each of which turns off when accessed or addressed; and conducting regions, which keep conductive state all the time. Binary data stored in the memory cell matrix are determined by detecting current flowing through the selected bit line.

Abstract: A semiconductor device comprising a non-volatile memory cell, for storing at least one bit, in a semiconductor substrate (1) having, in the substrate, a source region (6), a drain region (7) and a channel region (10) between the source (6) and drain (7) regions, and having, on top of the substrate, a floating gate (9) separated from the channel region (10) by a floating gate insulating layer, a select gate (11) adjacent to the floating gate and separated from the channel region by a select gate insulating layer (8), and a control gate (5) separated from the floating gate (9) by a control gate insulating layer, the floating gate being a non-conducting charge trapping dielectric layer (9).

Abstract: A scaled stack-gate non-volatile semiconductor memory device having atapered floating-gate structure is disclosed by the present invention, in which a stack-gate structure including a masking dielectric layer over a control-gate layer over an intergate dielectric layer over a tapered floating-gate layer on a thin tunneling-dielectric layer is formed on a semiconductor substrate having an active region isolated by field-oxides and is oxidized. A deeper double-diffused source region having a graded doping profile formed near a gate edge and a shallow drain diffusion region are formed as the first embodiment of the present invention. The deeper double-diffused source and drain regions having a graded doping profile formed near two gate edges are formed as the second embodiment of the present invention. The shallower double-diffused source and drain regions having a graded doping profile formed near two gate edges are formed as the third embodiment of the present invention.