Abstract: A semiconductor memory device and fabricating method thereof, wherein the semiconductor memory device includes first and second conductive regions formed in parallel at predetermined regions of a semiconductor substrate, a storage node and a multiple tunnel junction layer pattern sequentially stacked on a channel region between the first and second conductive regions, a data line stacked on the multiple tunnel junction layer pattern, and a wordline covering both sidewalls of the storage node and of the multiple tunnel junction layer pattern, wherein both sidewalls of the storage node have undercut regions for increasing the overlapping area of the storage node and a wordline. The storage node is formed by alternately and repeatedly stacking first and second conductive layers having different etch rates, successively patterning the conductive layers to form a storage node pattern, and selectively and isotropically etching the first or second conductive layer of the storage node pattern.

Abstract: A non-volatile semiconductor memory device comprising a device isolation insulation layer, a floating gate, and control gate, and a booster electrode. The device isolation insulation layer is formed on a semiconductor substrate, and is for defining a device region. The floating gate is formed above the device region and has a pair of first side faces opposed to a side face of the device isolation insulation layer which is located on the device region side. The control gate is formed above the floating gate. The booster electrode has faces opposed to a pair of second surfaces of the floating gate which are substantially perpendicular to the pair of first side faces. A distance between the pair of first side faces of the floating gate is equal or not more than a width of the device region defined by the device isolation insulation layer. Dimensions of the floating gate are determined based on a coupling ratio between the floating gate and the booster electrode.

Abstract: A flash memory cell in the form of a transistor capable of storing multi-bit binary data is disclosed. A pair of floating gates are provided beneath a control gate. The control gate is connected to a word line while active doped regions (source and drain regions) are connected to respective digit lines. The floating gates are separately charged and read out by controlling voltages applied to the word line and digit lines. The read out charges are decoded into a multi-bit binary value. One or both of the floating gates has a side insulator which connects through a conductor to an associated active doped region thereby forming a capacitor across the side insulator between the floating gate. This capacitor and active region facilitates operation of the transistor as a flash memory cell. Methods of fabricating the memory cell and operating it are also disclosed.

Abstract: Memory cell array and process of fabrication in which a floating gate is formed on a substrate for each of a plurality of memory cells, a control gate is formed above and in vertical alignment with each of the floating gates, source regions are formed in the substrate between and partially overlapped by first edge portions of the floating gates in adjacent ones of the cells, bit lines are formed in the substrate midway between second edge portions of the floating gates in adjacent ones of the cells, and a select gate is formed across the control gates, the floating gates, the bit lines and the source regions.

Abstract: A method and structure for a EEPROM memory device integrated with high performance logic or NVRAM. The EEPROM device includes a floating gate and program gate self-aligned with one another. During programming, electron tunneling occurs between the floating gate and the program gate.

Abstract: The present invention relates to a non-volatile semiconductor memory device and a fabricating method thereof, which prevents a programming disturbance and enables to have a programming operated by a byte unit by achieving a programming and an erasing of a memory device through a F-N tunneling.

Abstract: The invention relates to a semiconductor structure and a method for minimizing non-idealities in a semiconductor structure, in which a drain; a source, a floating gate (102) and at least one input (108) capacitively connected'to the floating gate (102) are disposed on a substrate (105) so as to form a v-MOSFET transistor. According to the invention, a conductive layer insulated from the floating gate (102) and at least partially superimposed on the gate (102) is formed in the semiconductor structure and the conductive layer is connected to a constant potential.

Abstract: The present invention is related to a non-volatile memory cell, comprising a semiconductor substrate including a source region and a drain region with a channel region there between; a floating gate of a conductive material at least partially extending over a first portion of said channel region; a control gate of a conductive material and at least partially extending over a second portion of the channel region; an additional program gate of a conductive material and at least partially overlapping said floating gate and being capacitively coupled through a dielectric layer to said floating gate.

Abstract: A non-volatile semiconductor memory device and the fabricating method thereof, wherein control gates respectively formed at the active areas of the resultant structure for getting a corresponding pair of split floating gates continuously overlapped and buried diffusion areas formed at the substrate of the periphery of the field insulating layer positioned between neighboring source areas to prevent the source areas from being electrically disconnected by the field insulating layer, even if the floating gate pattern and the control gate pattern are respectively made by separate processes, so that there will be no mismatching between the aforementioned two patterns, thereby leading to no tendency of showing different characteristics of memory cells in accordance with odd/even numbered word lines, the schematic characteristic of cells makes it possible to program and erase a byte, and one contact hole is not used at each bit line, the number of contact holes gets small, thereby making it possible to scale down c

Abstract: A method and structure for textured surfaces in non volatile floating gate tunneling oxide (FLOTOX) devices, e.g. FLOTOX transistors, are provided. The present invention capitalizes on using “self-structured masks” and a controlled etch to form nanometer scale microtip arrays in the textured surfaces. The microtips in the array of microtips have a more uniform size and shape and higher density (˜1012/cm2) at the substrate/tunnel oxide (Si/SiO2) interface than in current generation FLOTOX transistors. This higher density is four orders of magnitude greater than that which has been in use with FLOTOX transistor technology. In result, the new method and structure produce significantly larger tunneling currents for a given voltage than attained in prior work. The new method and structure are advantageously suited for the much higher density, non volatile FLOTOX transistors desired for use in flash memories and in electronically erasable and programmable read only memories (EEPROMs).

Abstract: A nonvolatile memory device includes: a first insulating film, a selection gate, a second insulating film and an erase gate layered on a semiconductor substrate; sidewalls formed in contact with both sides of the selection gate, the erase gate and the second insulating film; a third insulating film formed over an upper surface and an edge of the erase gate; a fourth insulating film formed on the surface of the semiconductor substrate in contact with the sidewalls; a floating gate overlapping the erase gate at a certain width; a dielectric film formed on the floating gate; a source/drain formed in the semiconductor below the floating gate and one of the sidewalls; and a control gate formed on the entire surface including the erase and floating gate.

Abstract: A scaled stack-gate non-volatile semiconductor memory device having atapered floating-gate structure is disclosed by the present invention, in which a stack-gate structure including a masking dielectric layer over a control-gate layer over an intergate dielectric layer over a tapered floating-gate layer on a thin tunneling-dielectric layer is formed on a semiconductor substrate having an active region isolated by field-oxides and is oxidized. A deeper double-diffused source region having a graded doping profile formed near a gate edge and a shallow drain diffusion region are formed as the first embodiment of the present invention. The deeper double-diffused source and drain regions having a graded doping profile formed near two gate edges are formed as the second embodiment of the present invention. The shallower double-diffused source and drain regions having a graded doping profile formed near two gate edges are formed as the third embodiment of the present invention.

Abstract: To provide a non-volatile semiconductor memory device in which the word line resistance can be decreased in resistance without being accompanied by increase in chip area, and a manufacturing method for the non-volatile semi conductor memory device. In a non-volatile semiconductor memory device having a floating gate (203 of FIG. 2) and a control gate (205 of FIG. 2), a contact groove (407 of FIG. 4a) extending in the direction of a word line (102 of FIG. 1) is provided on an interlayer insulating film (404 of FIG. 4a) formed as an upper layer of the control gate, and an electrically conductive member of, for example, tungsten, is embedded in the contact groove to establish electrical connection between the wiring metal (409 of FIG. 4d) formed as an upper layer of the interlayer insulating film and the control gate with a large contact area.

Abstract: A memory cell for devices of the EEPROM type, formed in a portion of a semiconductor material substrate having a first conductivity type. The memory cell includes source and drain regions having a second conductivity type and extending at the sides of a gate oxide region which includes a thin tunnel oxide region. The memory cell also includes a region of electric continuity having the second conductivity type, being formed laterally and beneath the thin tunnel oxide region, and partly overlapping the drain region, and a channel region extending between the region of electric continuity and the source region. The memory cell further includes an implanted region having the first conductivity type and being formed laterally and beneath the gate oxide region and incorporating the channel region.

Abstract: An improved method for forming a flash memory is disclosed. A self-aligned source implanted pocket located underneath and around the source line junction is formed after the field oxide between adjacent word lines is removed, and before or after the self-aligned source doping is carried out, so that the configuration of the implanted boron follows the source junction profile.

Abstract: A dual gate transistor device and method for fabricating the same. First, a doped substrate is prepared with a patterned oxide layer on the doped substrate defining a channel. Next, a silicon layer is deposited to form the channel, with a gate oxide layer then grown adjacent the channel. Subsequently, a plurality of gate electrodes are formed next to the gate oxide layer and a drain is formed on the channel. After the drain is formed, an ILD layer is deposited. This ILD layer is etched to form a source region contact, a drain region contact, a first gate electrode contact, and a second gate electrode contact.

Abstract: Provided are a memory device capable of accurately reading out data, a method of manufacturing the same, and an integrated circuit. A first control electrode substantially faces a second control electrode with a conduction region and a storage region in between. At the time of “the reading of data”, an electric potential is applied to the first control electrode. During “the reading of data”, a change in an electric potential between the conduction region and the storage region is prevented, and therefore, unintentional writing or erasing of information is prevented, so that written information can be accurately read out.

Abstract: The instant invention describes a programmable neuron MOSFET structure formed on SOI substrates. A number of input capacitor structures (241, 231) are formed on a SOI substrate. The substrate region of the capacitors (330, 340) are completely isolated from each other by isolation structures (270). In addition the transistor structure (210) of the neuron MOSFET is completely isolated from the capacitor structures (241, 231) by the isolation structure (270). The neuron MOSFET also comprises a contiguous floating conductive layer (200, 230, and 240) which forms the gate structure of the capacitors (230, 240) and the floating gate (200) of the transistor structure.

Abstract: One aspect of the present invention relates to a non-volatile semiconductor memory device, containing a substrate, the substrate having a core region and a periphery region; a charge trapping dielectric over the core region of the substrate; a gate dielectric in the periphery region of the substrate; buried bitlines under the charge trapping dielectric in the core region; and wordlines over the charge trapping dielectric in the core region, wherein the core region is substantially planar.

Abstract: An efficient method for fabricating dual well type structures uses the same number of masks used in single well type structure fabrication. In a preferred embodiment, the current invention allows low voltage and high voltage n-channel transistors and low voltage and high voltage p-channel transistors to be formed in a single substrate. One mask is used for forming a diffusion well, a second mask for both forming a retrograde well and doping the well to achieve an intermediate threshold voltage in that well, and a third mask for both differentiating the gate oxides for the low voltage devices and doping the threshold voltages to achieve the final threshold voltages.

Abstract: An SRAM cell is described which has a reduced cell area, and a reduced processing cost from conventional SRAM's. A fabrication process is described where self-aligned contacts to substrate active area and contact to a first layer of polysilicon are formed in one etch step. Electrical connection between the substrate and polysilicon is provided through a conductive layer coupled to the contacts. Self aligned contacts are fabricated to contact the active area.

Abstract: In a semiconductor memory device, such as a flash memory device, a conductor layer of metal or metal compound having high refractoriness, such as titanium nitride, is formed on a conductor or wiring formed by a buried diffusion layer to reduce resistance thereof. In the present invention, such conductor layer is formed by using small number of process steps and without using photolithography process. For example, after forming the buried diffusion layer for source and drain regions by ion implantation using each floating gate and dummy gate as a mask, titanium nitride is deposited throughout a substrate. Thereafter, by using oxide film growth and etching back process, an oxide film layer remaining on the titanium nitride layer between the floating gate and the dummy gate is fabricated. Then, the titanium nitride layer on the floating gate and on the dummy gate is removed by using this remained oxide film layer as a mask, without using any photolithography process.

Abstract: A tunneling charge injector includes a conducting injector electrode, a grid insulator disposed adjacent the conducting injector electrode, a grid electrode disposed adjacent said grid insulator, a retention insulator disposed adjacent said grid electrode, and a floating gate electrode disposed adjacent said retention insulator. In the tunneling charge injector, charge is injected from the conducting injector electrode onto the floating gate. Electrons are injected onto the floating gate when the conducting injector electrode is negatively biased with respect to the grid electrode, and holes are injected onto the floating gate when the conducting injector electrode is positively biased with respect to the grid electrode. The tunneling charge injector is employed in a nonvolatile memory cell having a nonvolatile memory element with a floating gate such as a floating gate MOS transistor.

Abstract: In an EEPROM consisting of a NAND cell in which a plurality of memory cells are connected in series, the control gate voltage Vread of the memory cell in a block selected by the data read operation is made different from the each of the voltages Vsg1, Vsg2 of the select gate of the select transistor in the selected block so as to make it possible to achieve a high speed reading without bringing about the breakdown of the insulating film interposed between the select gate and the channel of the select transistor. The high speed reading can also be made possible in the DINOR cell, the AND cell, NOR cell and the NAND cell having a single memory cell connected thereto, if the control gate voltage of the memory cell is made different from the voltage of the select gate of the select transistor.

Abstract: Self-aligned etching process for providing a plurality of mutually parallel word lines in a first conducting layer deposited over a plagiarized architecture obtained starting from a semiconductor substrate on which is provided a plurality of active elements extending along separate parallel lines e.g., memory cell bit lines and comprising gate regions made up of a first conducting layer, an intermediate dielectric layer and a second conducting layer with said regions being insulated from each other by insulation regions to form said architecture with said word lines being defined photolithographically by protective strips implemented by means of: a vertical profile etching for complete removal from the unprotected areas of the first conducting layer of the second conducting layer and of the intermediate dielectric layer respectively, and a following isotropic etching of the first conducting layer.

Abstract: Structures and methods for novel DRAM technology compatible non volatile memory cells is provided. A non volatile memory cell structure is provided which includes a dynamic random access memory (DRAM) transistor. The non volatile memory cell includes a dynamic random access memory (DRAM) capacitor separated by an insulator layer from the DRAM transistor. An electrical via couples a first plate of the DRAM capacitor through the insulator layer to a gate of the DRAM transistor. The novel DRAM technology compatible non volatile memory cells can be fabricated on a DRAM chip with little or no modification of the DRAM optimized process flow. The novel DRAM technology compatible non volatile memory cells operate with lower programming voltages than that used by conventional non volatile memory cells, yet still hold sufficient charge to withstand the effects of parasitic capacitances and noise due to circuit operation.

Abstract: NAND-type flash memory devices and methods of fabricating the same are provided. The NAND-type flash memory device includes a plurality of isolation layers running parallel with each other, which are formed at predetermined regions of a semiconductor substrate. This device also includes a string selection line pattern, a plurality of word line patterns and a ground selection line pattern which cross over the isolation layers and active regions between the isolation layers. Source regions are formed in the active regions adjacent to the ground selection line patterns and opposite the string selection line pattern. The source regions and the isolation layers between the source regions are covered with a common source line running parallel with the ground selection line pattern.

Abstract: A method for forming a high performance photodiode with tightly-controlled junction profile for CMOS image sensor with STI process. The following steps are performed: providing a substrate; forming a hard mask layer for defining a pattern on the substrate; etching the substrate on the surface of the substrate not covered by the hard mask layer to form a shallow trench; growing an oxide lining in the shallow trench by a thermal oxidation process; performing a first thermal annealing; defining an n-well region in the shallow trench; implanting the n-well region; performing a second thermal annealing; forming a silicon oxide layer on the substrate to fill in the shallow trench; removing a portion of the silicon oxide layer on the substrate such that the portion in the shallow trench remains; removing the hard mask layer; and forming a transistor on the substrate, wherein the transistor comprises a gate structure, a source region, and a drain region.

Abstract: There is provided a quantum thin line producing method capable of forming a quantum thin line that has good surface flatness of silicon even after formation of quantum thin line and a complete electron confining region with good controllability as well as a semiconductor device employing the quantum thin line. A region of a nitride film 3 which covers a semiconductor substrate 1 on which a stepped portion 2 is formed is etched back with masking, consequently exposing an upper portion of a semiconductor substrate 1. Next, an oxide film 5 is formed by oxidizing the exposed portion of the upper portion of the semiconductor substrate 1, and a linear protruding portion 6 is formed on the semiconductor substrate along a side surface of the nitride film 3. Next, the oxide film 5 on the protruding portion 6 is partially etched to expose a tip of the protruding portion 6. Next, a thin line portion 7 is made to epitaxially grow on the exposed portion at the tip of the protruding portion 6.

Abstract: In this invention a micro vacuum tube is used to form a flash memory cell. The micro vacuum tube is position over a floating gate and is used to program, erase, read and deselect the flash memory cell. A first embodiment includes a source and drain with the floating gate to provide a means to produce bit line current to be read by the flash memory sense amplifiers. In a second embodiment the source and drain are eliminated and cathode gate current is used to indicate the state of the flash memory cell. In a third embodiment the floating gate is replace with a diffusion in the semiconductor substrate. The cathode tip is formed by filling a depression in a sacrificial material used to temporarily fill the volume that will be the vacuum chamber when the vacuum tube is completed. The tip can be a convex cusp producing a needle like point or an elongated convex cusp having an sharp line edge.

Abstract: A semiconductor device as a nonvolatile memory comprises dot elements which are formed out of the semiconductor or conductor fine particles and function as a floating gate. The dot elements are asymmetrically formed to a control gate and may be formed in a sidewall insulating film formed over the side face of the control gate or a select gate. When inclined or stepped portions having level differences are formed in a semiconductor substrate, the dot elements are formed on a specified portion of the inclined or stepped portions.

Abstract: The present invention discloses the new structure with regard to a nonvolatile semiconductor memory which can store therein an information corresponding to a plurality of bits. The nonvolatile semiconductor memory according to the present invention has a charge trapping layer 4 for accumulating electrons, in an end of a gate electrode. In the nonvolatile semiconductor memory according to the present invention, the electrons are stored in this charge trapping layer 4 to thereby store the information corresponding to the plurality of bits.

Abstract: A non-volatile memory cell, comprising a semiconductor substrate having a first conductivity type. A control region is formed of said first conductivity type in the substrate and a control region oxide formed over the control region. The cell includes a program element having a first active region of a second conductivity type formed in said substrate, a doped or implanted region adjacent to said first active region, and a gate oxide overlying at least the channel region. An active region oxide covers a portion of the first active region. A floating gate is formed over said semiconductor substrate on said active region oxide and said control region oxide.

Abstract: Nonvolatile memory, cell array thereof, and method for sensing a data therefrom, the method including the steps of: selecting a flash memory cell having a first floating gate and a second floating gate, a first control gate and a second control gate, and a drain and a source; flowing a current through a first channel under the first floating gate and detecting a current flow through a second channel under the second floating gate, thereby sensing a color state of the second floating gate; flowing a current through the second channel and conducting level writings on the first floating gate, thereby forming different threshold voltages; measuring a cell current of the first channel under the first floating gate; comparing the measured cell current to a reference current, thereby sensing a level state of the first floating gate; and sensing information bits stored in the flash memory cell according to a color state of the second floating gate and a level state of the first floating gate.

Abstract: A semiconductor device is provided which is capable of suppressing an increase in the layer resistance of the gate electrode and preventing an increase of the contact resistance of the gate electrode with the silicide layer. The above properties of the semiconductor device are provided by forming the gate electrode comprising multiple layers, and the lowermost layer of the gate electrode is doped with an impurity, and other upper layers are formed undoped.

Abstract: A tunnel oxide film 120, a first polysilicon layer 164, a poly-poly insulating film 132 and a second polysilicon layer 166 are formed on a semiconductor substrate in a memory cell area. After that, with two photo resists 168-S and 168-M as a mask, patterning is performed for the films, a layered product of the films formed according to the photo resist 168-S is taken as a gate electrode of a selection transistor S, and a layered product of the films formed according to the photo resist 168-M is taken as a gate electrode of a memory transistor M.

Abstract: A flash memory cell and a method for fabricating the same are provided. A first conductive film exposing a predetermined area of a semiconductor substrate is formed on the semiconductor substrate, and a tunnel oxide and a first interlevel dielectric film are formed on the surface of the semiconductor substrate exposed by the first conductive film and on the surface of the first conductive film, respectively. A floating gate covering the tunnel oxide and extending to the upper portion of the first conductive film in the vicinity of the tunnel oxide is formed as a second conductive film, and a second interlevel dielectric film is formed on the surface of the floating gate. A third conductive film electrically connected to the first conductive film in the vicinity of the floating gate is formed on a second interlevel dielectric film, thereby forming a control gate electrode comprised of the first conductive film and the third conductive film.

Abstract: On a SIMOX substrate having a plurality of STI layers and first conductivity type semiconductor layers disposed in the row direction, a stacked-layer structure SS is formed on a gate dielectric film formed on the first conductivity type semiconductor layer, the structure SS being made of a first polysilicon film, a second gate dielectric film and a second polysilicon film. Second conductivity type source and drain regions are formed in the first conductivity type semiconductor layer on both sides of the structure SS. In a plurality of source regions adjacent in the column direction between the stacked-layer structures SS, a common source line CSL is formed which is made of second conductivity type source region connecting semiconductor regions, source regions and conductive films formed on these semiconductor and source regions.

Abstract: A non-volatile memory device and a fabrication method thereof, wherein the non-volatile memory device includes first and second memory cells in a region of a semiconductor substrate where a word line crosses a bit line. Thus, one word line can control the operation of two memory cells, and the device requires less area. Further an intergate dielectric layer extends to the side walls of the floating gate allowing more area and a higher coupling ratio. A lower voltage may therefore be applied to the control gate. During an erasing operation the path of electrons can be redirected toward the substrate. Deterioration of a tunneling insulating layer is thereby reduced or eliminated.

Abstract: Array of electrically programmable non-volatile memory cells, each cell comprising a stacked-gate MOS transistor having a lower gate electrode, an upper gate electrode coupled to a row of the array, a first electrode associated with a column of the array and a second electrode separated from the first electrode by a channel region underlying said lower gate electrode, the first electrode, the second electrode and the channel region being formed in a layer of semiconductor material of a first conductivity type and having a second conductivity type, comprising at least one ROM memory cell which identically to the electrically programmable non-volatile memory cells comprises a stacked-gate MOS transistor and is associated with a respective row and a respective column of the array, the ROM cell including means for allowing or not allowing the electrical separation between said respective column and the second electrode of the ROM cell, if the ROM cell must store a first logic state or, respectively, a second logi

Abstract: A semiconductor integrated circuit having a multiple split gate is forming using a first polysilicon layer and a second polysilicon layer to form alternating first and second gate electrodes within an active area. The alternating gate electrodes are electrically isolated from one another by means of a gate insulating layer that is formed adjacent the side-walls of each firs gate electrode. Source and drain regions are formed adjacent the ends of the multiple split gate to define a channel region.

Abstract: The device includes a gate oxide formed on a semiconductor substrate. Oxide regions are respectively formed on the substrate and adjacent to the gate oxide. Textured oxides are formed on the substrate, between the gate oxide and the oxide regions. A floating gate consists of a first polysilicon portion, second polysilicon portions and a third portion that is composed of hemisperical grained silicon (HSG-Si). The first polysilicon portion is formed on the gate oxide. Isolations are formed on the side walls of the first polysilicon portion. The second polysilicon portions are respectively formed next to the isolations and over a portion of the oxide regions. The HSG-Si is formed on the upper surface of the first polysilicon portion and the second polysilicon portions. A dielectric layer is formed on the HSG-Si of the floating gate. A control gate is formed on the dielectric layer. The doped regions are formed in the substrate and under the textured oxides and the oxide regions.

Abstract: A nonvolatile memory includes five transistors. The memory has an MOS transistor in series with two pairs of transistors, where each pair includes a floating gate transistor and a metal-oxide-semiconductor transistor electrically connected in parallel. The memory structure may be formed with three levels of silicon-containing or metal-containing layers. The memory structure is less susceptible to read disturb errors compared to a prior art dual-bit nonvolatile memory structure.

Abstract: Non-volatile memory semiconductor device manufacturing throughput is increased by simultaneously patterning the floating gate layer and dielectric layer formed thereon. Embodiments include forming sidewall dielectric layers joined with one of the isolation insulating regions to enhance insulation of the floating gate electrode.

Abstract: The provision of an isolation gate connecting unassociated active areas of adjacent transistors formed in a semiconductor substrate provides effective isolation of the adjacent transistors with no additional process steps required. The isolation gate is tied to a reference to ensure that a channel between the unassociated active areas is not formed, and effective isolation is provided. The adjacent transistors are cross coupled to form sense amplifiers for dynamic random access memory devices.

Abstract: A semiconductor memory device comprising a source and a drain formed in a P-type semiconductor substrate and a floating gate and a control gate constituting a two-layer gate. Electric-field moderating layer is provided in the P-type semiconductor substrate to contact with a side face of the drain. P-type region is formed in contact with channel region side surface and bottom surface of the electric-field moderating layer. P-type region lower part of the P-type region in contact with the bottom surface of the electric-field moderating layer is given a lower impurity concentration than P-type region side part formed at the channel region side of the electric-field moderating layer. By this means it is possible to increase the writing speed of the semiconductor memory device while suppressing delay in the switching speed during reading operation.

Abstract: An article and method of manufacturing a semiconductor flash cell. The method includes producing an isolation formation layer on a silicon substrate, forming an oxide on the isolation formation layer, growing a tunnel oxide layer thereon, depositing a first poly silicon layer, masking and etching the first poly silicon layer, depositing a second poly silicon layer and performing a blanket etch back step, forming an oxide/nitride/oxide layer forming a third poly-silicon layer and depositing a silicide layer thereon.

Abstract: A method to make a self-aligned floating gate in a memory device. The method patterns the floating gate (FG) using the trench etch for the shallow trench isolation (STI). Because the floating gate (FG) is adjacent to the raised STI, sharp corners are eliminated between the FG and CG thereby increasing the effectiveness of the intergate dielectric layer. The method includes: forming an first dielectric layer (gate oxide) and a polysilicon layer over a substrate, etching through the first dielectric oxide layer and the polysilicon layer and into the substrate to form a trench. The remaining first dielectric layer and polysilicon layer function as a tunnel dielectric layer and a floating gate. The trench is filled with an isolation layer. The masking layer is removed. An intergate dielectric layer and a control gate are formed over the floating gate and the isolation layer.

Abstract: In order to easily and accurately manufacture a micromachine comprising a member which is made of a single-crystalline material and having a complicated structure, an uppermost layer (1104) of a single-crystalline Si substrate (1102) whose (100) plane is upwardly directed is irradiated with Ne atom currents from a plurality of prescribed directions, so that the crystal orientation of the uppermost layer (1104) is converted to such orientation that the (111) plane is upwardly directed. A masking member (106) is employed as a shielding member to anisotropically etch the substrate (1102) from its bottom surface, thereby forming a V-shaped groove (1112). At this time, the uppermost layer (1104) serves as an etching stopper. Thus, it is possible to easily manufacture a micromachine having a single-crystalline diaphragm having a uniform thickness. A micromachine having a complicated member such as a diagram which is made of a single-crystalline material can be easily manufactured through no junction.

Abstract: An electrically-programmable read-only-memory (EPROM) and a flash memory cell having source-side injection are formed with a gate dielectric material, and a pair of gates that are both formed on the gate dielectric material. The gate dielectric material has substantially more electron traps than hole traps so that the gate dielectric material is capable of having a negative potential which is sufficient to inhibit the formation of a conductive channel during a read operation.